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| Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor PSMN005-55B, PSMN005-55P FEATURES * 'Trench' technology * Very low on-state resistance * Fast switching * Low thermal resistance g SYMBOL d QUICK REFERENCE DATA VDSS = 55 V ID = 75 A RDS(ON) 5.8 m (VGS = 10 V) RDS(ON) 6.3 m (VGS = 5 V) s GENERAL DESCRIPTION SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:* d.c. to d.c. converters * switched mode power supplies The PSMN005-55P is supplied in the SOT78 (TO220AB) conventional leaded package. The PSMN005-55B is supplied in the SOT404 surface mounting package. PINNING PIN 1 2 3 tab gate drain1 source drain DESCRIPTION SOT78 (TO220AB) tab SOT404 (D2PAK) tab 2 1 23 1 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Continuous gate-source voltage Peak pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tj 150 C Tmb = 25 C; VGS = 5 V Tmb = 100 C; VGS = 5 V Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 15 20 752 752 240 230 175 UNIT V V V V A A A W C 1 It is not possible to make connection to pin:2 of the SOT404 package 2 maximum current limited by package October 1999 1 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS PSMN005-55B, PSMN005-55P TYP. - MAX. 0.65 - UNIT K/W K/W K/W SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint 60 50 AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS IAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 75 A; tp = 100 s; Tj prior to avalanche = 25C; VDD 15 V; RGS = 50 ; VGS = 5 V MIN. MAX. 268 75 UNIT mJ A ELECTRICAL CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 4.5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175C Gate source leakage current VGS = 10 V; VDS = 0 V Zero gate voltage drain VDS = 55 V; VGS = 0 V; current Tj = 175C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 75 A; VDD = 44 V; VGS = 5 V MIN. 55 50 1.0 0.5 TYP. MAX. UNIT 1.5 4.8 5.3 2 0.05 103 15 52 45 180 420 235 3.5 4.5 7.5 6500 1500 700 2.0 2.3 5.8 6.3 6.7 13.2 100 10 500 V V V V V m m m m nA A A nC nC nC ns ns ns ns nH nH nH pF pF pF IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss VDD = 30 V; RD = 1.2 ; VGS = 5 V; RG = 10 Resistive load Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz October 1999 2 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor PSMN005-55B, PSMN005-55P REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V IF = 20 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V TYP. MAX. UNIT 0.85 1.1 80 0.2 75 240 1.2 A A V V ns C October 1999 3 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor PSMN005-55B, PSMN005-55P Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 1 Transient thermal impedance, Zth j-mb (K/W) D = 0.5 0.2 0.1 0.1 0.05 0.02 P D tp D = tp/T 0.01 single pulse T 0.001 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) 400 ID/A 300 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 10.0 7.0 6.0 5.0 4.8 4.6 4.4 VGS\V = 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 0 2 4 VDS/D 6 8 10 200 100 0 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS) RDS(ON)/mOhm VGS/V = 1000 8.5 tp = 10 us 8 7.5 100 100 us 7 1 ms D.C. 10 10 ms 100 ms 3.0 6.5 6 5.5 3.2 3.4 3.6 4.0 5.0 0 20 40 ID/A 60 80 100 1 1 10 Drain-Source Voltage, VDS (V) 100 5 Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID) October 1999 4 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor PSMN005-55B, PSMN005-55P 100 ID/A 80 2.25 2 1.75 1.5 Threshold Voltage, VGS(TO) (V) maximum typical minimum 60 1.25 1 40 Tj = 175 25 0.75 0.5 20 0.25 0 -60 0 0.5 1 1.5 VGS/V 2 2.5 3 3.5 0 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) 150 gfs/S Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 1.0E-01 Drain current, ID (A) 1.0E-02 100 1.0E-03 minimum typical 1.0E-04 50 maximum 1.0E-05 1.0E-06 0 0 0 20 40 ID/A 60 80 100 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS Normalised On-state Resistance 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 100000 Capacitances, Ciss, Coss, Crss (pF) 10000 Ciss Coss 1000 Crss 100 0.1 1 10 Drain-Source Voltage, VDS (V) 100 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj) Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz October 1999 5 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor PSMN005-55B, PSMN005-55P 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Gate-source voltage, VGS (V) ID = 75 A Tj = 25 C 100 Maximum Avalanche Current, IAS (A) 25 C VDD = 11 V VDD = 44 V 10 Tj prior to avalanche = 150 C 0 25 50 75 100 125 150 175 Gate charge, QG (nC) 200 225 250 1 0.001 0.01 0.1 Avalanche time, tAV (ms) 1 10 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load 100 IF/A 80 60 Tj/C = 40 175 25 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VSDS/V 0.7 0.8 0.9 1 1.1 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj October 1999 6 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor MECHANICAL DATA PSMN005-55B, PSMN005-55P Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78 E P A A1 q D1 D L2(1) L1 Q L b1 1 2 3 b c e e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.39 1.27 b 0.9 0.7 b1 1.3 1.0 c 0.7 0.4 D 15.8 15.2 D1 6.4 5.9 E 10.3 9.7 e 2.54 L 15.0 13.5 L1 3.30 2.79 L2 max. 3.0 (1) P 3.8 3.6 q 3.0 2.7 Q 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g) Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". October 1999 7 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor MECHANICAL DATA PSMN005-55B, PSMN005-55P Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A E A1 mounting base D1 D HD 2 Lp 1 3 b c Q e e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.40 14.80 Q 2.60 2.20 OUTLINE VERSION SOT404 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". October 1999 8 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor MOUNTING INSTRUCTIONS Dimensions in mm 11.5 PSMN005-55B, PSMN005-55P 9.0 17.5 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1999 9 Rev 1.200 |
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