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FMS3110/3115
Triple Video D/A Converters
3 x 10 bit, 150 Ms/s Features
* * * * * * * * * * 10-bit resolution 150 megapixels per second 0.1% linearity error Sync and blank controls 1.0V p-p video into 37.5 or 75 load Internal bandgap voltage reference Double-buffered data for low distortion TTL-compatible inputs Low glitch energy Single +5 Volt power supply
Description
FMS3110/3115 products are low-cost triple D/A converters that are tailored to fit graphics and video applications where speed is critical. Two speed grades are available: FMS3110 FMS3115 100 Ms/s 150 Ms/s
Applications
* Video signal conversion - RGB - YCBCR - Composite, Y, C * Multimedia systems * Image processing * True-color graphics systems (1 billion colors) * Broadcast television equipment * High-Definition Television (HDTV) equipment * Direct digital synthesis
TTL-level inputs are converted to analog current outputs that can drive 25-37.5 loads corresponding to doubly-terminated 50-75 loads. A sync current following SYNC input timing is added to the IOG output. BLANK will override RGB inputs, setting IOG, IOB and IOR currents to zero when BLANK = L. Although appropriate for many applications the internal 1.235V reference voltage can be overridden by the VREF input. Few external components are required, just the current reference resistor, current output load resistors, and decoupling capacitors. Package is a 48-lead LQFP. Fabrication technology is CMOS. Performance is guaranteed from 0 to 70C.
Block Diagram
SYNC BLANK SYNC
G9-0
10
10 bit D/A Converter
IOG
B9-0
10
10 bit D/A Converter
IOB
R9-0 CLOCK
10
10 bit D/A Converter
IOR COMP RREF VREF
+1.235V Ref
Rev. 1.05 12/21/00
FMS3110/3115
PRODUCT SPECIFICATION
Functional Description
Within the FMS3110/3115 are three identical 10-bit D/A converters, each with a current source output. External loads are required to convert the current to voltage outputs. Data inputs RGB7-0 are overridden by the BLANK input. SYNC = H activates, sync current from IOS for sync-on-green video signals.
D/A Outputs
Each D/A output is a current source. To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. Normally, a source termination resistor of 75 Ohms is connected between the D/A current output pin and GND near the D/A converter. A 75 Ohm line may then be connected with another 75 Ohm termination resistor at the far end of the cable. This "double termination" presents the D/A converter with a net resistive load of 37.5 Ohms. The FMS3110/3115 may also be operated with a single 75 Ohm terminating resistor. To lower the output voltage swing to the desired range, the nominal value of the resistor on RREF should be doubled.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered on the rising edge of the CLK signal. Following one stage of pipeline delay, the analog output changes tDO after the rising edge of CLK.
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 1 and Table 1) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC = L turns off a current source that is connected to the green D/A converter. SYNC = H adds a 40 IRE sync pulse to the green output, SYNC = L sets the green output to 0.0 Volts during the sync tip. SYNC and BLANK are registered on the rising edge of CLK. BLANK gates the D/A inputs and sets the pedestal voltage. If BLANK = HIGH, the D/A inputs are added to a pedestal which offsets the current output. If BLANK = Low, data inputs and the pedestal are disabled.
Voltage Reference
All three D/A converters are supplied with a common voltage reference. Internal bandgap voltage reference voltage is +1.235 Volts with a 3K source resistance. An external voltage reference may be connected to the VREF pin, overriding the internal voltage reference. A 0.1F capacitor must be connected between the COMP pin and VDD to stabilize internal bias circuitry and ensure low-noise operation.
Power and Ground
data: 660 mV max.
pedestal: 54 mV sync: 286 mV
Required power is a single +5.0 Volt supply. To minimize power supply induced noise, analog +5V should be connected to VDD pins with 0.1 and 0.01 F decoupling capacitors placed adjacent to each VDD pin or pin pair. The high slew-rate of digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance.
Figure 1. Nominal Output Levels
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PRODUCT SPECIFICATION
FMS3110/3115
Table 1. Output Voltage Versus Input Code, SYNC and BLANK
VREF = 1.235 V, RREF = 590 , RL = 37.5 Blue and Red D/As RGB9-0 (MSB...LSB) 11 1111 1111 11 1111 1111 11 1111 1110 11 1111 1101 * * 10 0000 0000 01 1111 1111 * * 00 0000 0010 00 0000 0001 00 0000 0000 XX XXXX XXXX XX XXXX XXXX SYNC X X X X * * X X * * X X X X X BLANK 1 1 1 1 * * 1 1 * * 1 1 1 0 0 VOUT 0.7140 0.7140 0.7134 0.7127 * * 0.3843 0.3837 * * 0.0553 0.0546 0.0540 0.0000 0.0000 SYNC 1 0 1 1 * * 1 1 * * 1 1 1 1 0 Green D/A BLANK 1 1 1 1 * * 1 1 * * 1 1 1 0 0 VOUT 1.0000 0.7140 0.9994 0.9987 * * 0.6703 0.6697 * * 0.3413 0.3406 0.3400 0.2860 0.0000
Pin Assignments
G0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 NC 48 47 46 45 44 43 42 41 40 39 38 37
G1 G2 G3 G4 G5 G6 G7 G8 G9 BLANK SYNC VDD
1 2 3 4 5 6 7 8 9 10 11 12
LQFP FMS3110/3115
36 35 34 33 32 31 30 29 28 27 26 25
RREF VREF COMP IOR IOG OVDD VDD IOB GND GND CLOCK NC
NC B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 NC
13 14 15 16 17 18 19 20 21 22 23 24
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FMS3110/3115
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name CLK Pin Number 26 Value TTL Description Clock Input. The clock input is TTL-compatible and all pixel data is registered on the rising edge of CLK. It is recommended that CLK be driven by a dedicated TTL buffer to avoid reflection induced jitter, overshoot, and undershoot. Red Pixel Data Inputs. TTL-compatible Red Data Inputs are registered on the rising edge of CLK. Green Pixel Data Inputs. TTL-compatible Green Data Inputs are registered on the rising edge of CLK. Blue Pixel Data Inputs. TTL-compatible Blue Data Inputs are registered on the rising edge of CLK. Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA) current source which forms a sync pulse on the Green D/A converter output. SYNC is registered on the rising edge of CLK with the same pipeline latency as BLANK and pixel data. SYNC does not override any other data and should be used only during the blanking interval. Since this is a single-supply D/A and all signals are positive-going, sync is added to the bottom of the Green D/A range. So turning SYNC OFF means turning the current source ON. When a sync pulse is desired, the current source is turned OFF. If the system does not require sync pulses from the Green D/A converter, SYNC should be connected to GND. BLANK 10 TTL Blanking Input. When BLANK is LOW, pixel inputs are ignored and the D/A converter outputs fall to the blanking level. BLANK is registered on the rising edge of CLK and has the same pipeline latency as SYNC. Red Current Output. The current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Green Current Output. The current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Sync pulses may be added to the Green D/A output. Blue Current Output. The current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Clock and Pixel I/O
R9-0 G9-0 B9-0 Controls SYNC
47-37 48, 9-1 23-14
TTL TTL TTL
11
TTL
Video Outputs IOR 33 0.714 Vp-p
IOG
32
1 Vp-p
IOB
29
0.714 Vp-p
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PRODUCT SPECIFICATION
FMS3110/3115
Pin Descriptions (continued)
Pin Name VREF Pin Number 35 Value +1.235 V Description Voltage Reference Output/Input. An internal voltage source of +1.235 Volts is output on this pin. An external +1.235 Volt reference may be applied here which overrides the internal reference. Decoupling VREF to GND with a 0.1F ceramic capacitor is required. Current-Setting Resistor. Full-scale output current of each D/A converter is determined by the value of the resistor connected between RREF and GND. Nominal value of RREF is found from: RREF = 9.1 (VREF/IFS) where IFS is the full-scale (white) output current (in amps) from the D/A converter (without sync). Sync is 0.4 * IFS. D/A full-scale (white) current may also be calculated from: IFS = VFS/RL Where VFS is the white voltage level and RL is the total resistive load (in ohms) on each D/A converter. VFS is the blank to full-scale voltage. COMP 34 0.1 F Compensation Capacitor. A 0.1 F ceramic capacitor must be connected between COMP and VDD to stabilize internal bias circuitry. Power Supply. Ground. Voltage Reference
RREF
36
560
Power and Ground VDD GND 12, 30, 31 27, 28 +5 V 0.0V
Equivalent Circuits
VDD VDD
p Digital Input n n VDD p
OUT GND GND
Figure 2. Equivalent Digital Input Circuit
Figure 3. Equivalent Analog Output Circuit
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FMS3110/3115
PRODUCT SPECIFICATION
Equivalent Circuits (continued)
VDD
p RREF VREF
p
GND
27012B
Figure 4. Equivalent Analog Input Circuit
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter Power Supply Voltage VDD (Measured to GND) Inputs Applied Voltage (measured to GND)2 Forced Current3,4 Outputs Applied Voltage (measured to GND)2 Forced Current3,4 Short Circuit Duration (single output in HIGH state to ground) Temperature Operating, Ambient Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage -65 -20 110 150 300 220 150 C C C C C -0.5 -60.0 VDD + 0.5 60.0 Infinite V mA second -0.5 -10.0 VDD + 0.5 10.0 V mA -0.5 7.0 V Min Typ Max Unit
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
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REV. 1.05 12/21/00
PRODUCT SPECIFICATION
FMS3110/3115
Operating Conditions
Parameter VDD fS tPWH tPWL tW tS th tPWH tPWL VREF CC RL VIH VIL TA Power Supply Voltage Conversion Rate CLK Pulsewidth, HIGH CLK Pulsewidth, LOW CLK Pulsewidth Input Data Setup Time Input Date Hold Time CLK Pulsewidth, HIGH CLK Pulsewidth, LOW Reference Voltage, External Compensation Capacitor Output Load Input Voltage, Logic HIGH Input Voltage, Logic LOW Ambient Temperature, Still Air 2.0 GND 0 FMS3110 FMS3115 FMS3110 FMS3115 FMS3110 FMS3115 FMS3110 FMS3115 3.1 2.5 3.1 2.5 10 6.6 1.7 0 2 2 1.0 1.235 0.1 37.5 VDD 0.8 70 1.5 Min 4.75 Nom 5.0 Max 5.25 100 150 Units V Msps Msps ns ns ns ns ns ns ns ns ns ns V F V V C
Electrical Characteristics
Parameter IDD PD RO CO IIH IIL IREF VREF VOC CDI Power Supply Current2 Total Power Dissipation2 Output Resistance Output Capacitance Input Current, HIGH Input Current, LOW VREF Input Bias Current Reference Voltage Output Output Compliance Digital Input Capacitance Referred to VDD -0.4 IOUT = 0mA VDD = Max, VIN = 2.4V VDD = Max, VIN = 0.4V 0 1.235 0 4 +1.5 10 Conditions3 VDD = Max VDD = Max 100 30 -5 5 100 Min Typ1 Max 125 655 Units mA mW k pF A A A V V pF
Notes: 1. Values shown in Typ column are typical for VDD = +5V and TA = 25C. 2. Minimum/Maximum values with VDD = Max and TA = Min. 3. VREF = 1.235V, RLOAD = 37.5, RREF = 540
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FMS3110/3115
PRODUCT SPECIFICATION
Switching Characteristics
Parameter tD tSKEW tR tF Clock to Output Delay Output Skew Output Risetime Output Falltime 10% to 90% of Full Scale 90% to 10% of Full Scale Conditions2 VDD = Min Min Typ1 10 1 Max 15 2 3 3 Units ns ns ns ns
Notes: 1. Values shown in Typ column are typical for VDD = +5V and TA = 25C. 2. VREF = 1.235V, RLOAD = 37.5, RREF = 590.
System Performance Characteristics
Parameter ELI ELD EDM PSR Integral Linearity Error Differential Linearity Error DAC to DAC Matching Power Supply Rejection Ratio Conditions2 VDD, VREF = Nom VDD, VREF = Nom VDD, VREF = Nom Min Typ1 0.1 0.1 3 Max 0.25 0.25 10 0.05 Units %/FS %/FS % %/%
Notes: 1. Values shown in Typ column are typical for VDD = +5V and TA = 25C. 2. VREF = 1.235V, RLOAD = 37.5, RREF = 590.
Timing Diagram
tPWL CLK tPWH 1/fS
tS PIXEL DATA & CONTROLS DataN
tH
DataN+1
DataN+2
3%/FS
90% tD OUTPUT 50% tSET tF 10% tR
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PRODUCT SPECIFICATION
FMS3110/3115
Applications Discussion
Figure 5 illustrates a typical FMS3110/3115 interface circuit. In this example, an optional 1.2 Volt bandgap reference is connected to the VREF output, overriding the internal voltage reference source.
2.
Grounding
It is important that the FMS3110/3115 power supply is wellregulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The FMS3110/3115 has separate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages (VDD) come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. 3.
Power plane for the FMS3110/3115 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the FMS3110/3115 is the same as that of the system's digital circuitry, power to the FMS3110/3115 should be decoupled with 0.1F and 0.01F capacitors and isolated with a ferrite bead. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. If the digital power supply has a dedicated power plane layer, it should not be placed under the FMS3110/3115, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the FMS3110/3115 and its related analog circuitry can have an adverse effect on performance. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing.
4.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG) as short as possible and as far as possible from all digital signals. The FMS3110/3115 should be located near the board edge, close to the analog output connectors.
5.
Related Products
* FMS38XX Triple 8-bit 150 Msps D/A Converters * FMS9884A 3 x 8-bit 140 Ms/s A/D Converter
+5V 10F 0.1F
VDD RED PIXEL INPUT GREEN PIXEL INPUT BLUE PIXEL INPUT CLOCK SYNC BLANK R9-0 G9-0 B9-0 CLK SYNC BLANK
GND
Red IOR IOG 75 75 75 COMP 0.1F VREF RREF +5V 3.3k (not required without external reference) LM185-1.2 (Optional) 0.1F
ZO=75
75 75 75
Green w/Sync
ZO=75
Blue
ZO=75
FMS31XX Triple 10-bit D/A Converter
IOB
560
Figure 5. Typical Interface Circuit
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FMS3110/3115
PRODUCT SPECIFICATION
Mechanical Dimensions
48-Lead LQFP Package
Inches Min. A A1 A2 B D/E D1/E1 e L N ND ccc Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Pin 1 identifier is optional. 7 8 2 6 4 5 4. Dimension ND: Number of terminals. 5. Dimension ND: Number of terminals per package edge. 6. "L" is the length of terminal for soldering to a substrate. 7. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum B dimension by more than 0.08mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. 8. To be determined at seating place --C--
Symbol
.055 .063 .001 .005 .053 .057 .006 .010 .346 .362 .268 .284 .019 BSC .017 .029 48 12 0 7 .004
1.40 1.60 .05 .15 1.35 1.45 .17 .27 8.8 9.2 6.8 7.2 .50 BSC .45 .75 48 12 0 7 0.08
D D1
e
E E1
PIN 1 IDENTIFIER
C
L 0.063" Ref (1.60mm)
See Lead Detail
A
A2 B A1 Seating Plane
Base Plane -CLEAD COPLANARITY ccc C
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FMS3110/3115
PRODUCT SPECIFICATION
Ordering Information
Product Number FMS3110KRC FMS3115KRC Conversion Rate 100 Ms/s 150 Ms/s Temperature Range TA = 0C to 70C TA = 0C to 70C Screening Commercial Commercial Package 48-Lead LQFP 48-Lead LQFP Package Marking 3110KRC 3115KRC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 12/21/00 0.0m 003 Stock#DS30003110 2000 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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