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CXA2075M
RGB Encoder
Description The CXA2075M is an encoder IC that converts analog RGB signals to a composite video signal. This IC has various pulse generators necessary for encoding. Composite video outputs and Y/C outputs for the S terminal are obtained just by inputting composite sync, subcarrier and analog RGB signals. It is best suited to image processing of personal computers and video games. Compared to the CXA1645M, the CXA2075M has superior points as follows: 1. The number of parts reduced (5 parts) Clamp capacitor Regulator capacitor resistor Resistor for filter 2. External parts reduced by the internal TRAP (External TRAP can be also selected) 3. Higher band of R, G, B OUT Features * Single 5V power supply * Compatible with both NTSC and PAL systems * Built-in 75 drivers (RGB output, composite video output, Y output, C output) * Both sine wave and pulse can be input as a subcarrier. * Built-in band-pass filter for the C signal and delay line for the Y signal * Built-in R-Y and B-Y modulator circuits * Built-in PAL alternate circuit * Burst flag generator circuit * Half H killer circuit Block Diagram and Pin Configuration
CVOUT ROUT YTRAP GOUT GND2 BOUT Vcc2 YOUT COUT NC NC NC
24 pin SOP (Plastic)
Applications Video games and personal computers Structure Bipolar silicon monolithic IC Absolute Maximum Ratings 12 V * Supply voltage VCC * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 780 mW * Input pin applied voltage RIN, GIN, BIN, SCIN, NPIN, SYNCIN and Vcc pins voltage or below, GND pin voltage or above Recommended Operating Condition Supply voltage VCC1, 2 5.0 0.25 V
24
23
22
21
20 VIDEO OUT
19
18
17
16
15
14
13
TRAP SWITCH INTERNAL TRAP DELAY SYNC ADD
R-OUT
G-OUT
B-OUT
Y/C MIX
75 DRIVER
75 DRIVER
BPF R-Y Modulator REGULATOR B-Y Modulator PHASE SHIFTER 8 PULSE GEN 9 10 11 12
MATRIX
LPF
LPF
CLAMP
SIN-PULSE
1
2
3
4
5
6
7
GIN
BFOUT
RIN
NC
SYNCIN
GND1
NPIN
BIN
NC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
SCIN
-1-
Vcc1
NC
E96X23
CXA2075M
Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description Ground for all circuits other than RGB, composite video and Y/C output circuits. The leads to GND2 should be as short and wide as possible.
VCC1 100
1
GND1
0V
--
2 3 4
RIN GIN BIN
Black level when clamped
100 2 3 4
175
175
GND1 ICLP
5
NC
VCC1
350
2V
Analog RGB signal inputs. Input at 100% = 1Vp-p (max.). To minimize clamp error, input at as low impedance as possible. ICLP turns ON only in the burst flag period.
NO CONNECTION
6
SCIN
--
6
10P 40k 2.5V 100 GND1
Subcarrier input. Input 0.4 to 5.0Vp-p sine wave or pulse. Refer to Notes on Operation, Nos. 2 and 4.
VCC1 80k
7
NPIN
1.7V when open
68k 7 3k
Pin for switching between NTSC and PAL modes. NTSC: VCC, PAL: GND
32k GND1
VCC1 800
8
BFOUT
H : 3.6V L : 3.2V
8
1.6k
BF pulse monitoring output. Incapable of driving a 75 load.
65 GND1
65
-2-
CXA2075M
Pin No. 9
Symbol Pin voltage NC
Equivalent circuit
Description NO CONNECTION
VCC1 40k
10
SYNCIN
2.2V
10 4k
Composite sync signal input. Input TTLlevel voltages. L ( 0.8V): SYNC period H ( 2.0V)
2.2V GND1
11
NC
NO CONNECTION Power supply for all circuits other than RGB, composite video and Y/C output circuits. Refer to Notes on Operation, Nos. 3 and 8. NO CONNECTION NO CONNECTION
12
Vcc1
5.0V
--
13 14
NC NC
20 375
Vcc2 Vcc1
15
COUT
1.6V
15 2.8V 2.2k GND1 GND2
Chroma signal output. Capable of driving a 75 load. Refer to Notes on Operation, Nos. 5 and 7.
20 375
Vcc2 Vcc1
16
YOUT
Black level 1.35V
Y signal output. Capable of driving a 75 load. Refer to Notes on Operation, Nos. 5 and 7.
GND1 GND2
16
2.8V 2.2k
-3-
CXA2075M
Pin No.
Symbol Pin voltage
Equivalent circuit
Description Pin for reducing cross color caused by the subcarrier frequency component of the Y signal. When the CVOUT pin is in use, connect a capacitor or a capacitor and an inductor in series between YTRAP and GND. Decide capacitance and inductance, giving consideration to cross color and the required resolution. No influence on the YOUT pin. Internal TRAP can be also used. Refer to Notes on Operation, No. 6.
100
Vcc1 Y 1.5k 100 GND1
17
YTRAP
Black level 2.13V
17
30k
18
NC
NO CONNECTION Power supply for RGB, composite video and Y/C output circuits. Decouple this pin with a large capacitor of 10F or above as a high current flows. Refer to Notes on Operation, Nos. 3 and 8.
19
VCC2
5.0V
--
20 375
Vcc2 Vcc1
20
Black level CVOUT 0.97V
Composite video signal output. Capable of driving a 75 load. Refer to Notes on Operation, Nos. 5 and 7.
GND1 GND2
20
2.8V 2.2k
20 375
Vcc2 Vcc1
21 22 23
BOUT GOUT ROUT
Black level 1.2V
21 22 23 2.8V 2.2k GND1 GND2
Analog RGB signal outputs. Capable of driving a 75 load. Refer to Notes on Operation, Nos. 5 and 7.
24
GND2
0V
--
Ground for RGB, composite video and Y/C output circuits. The leads to GND1 should be as short and wide as possible.
-4-
CXA2075M
Electrical Characteristics
(Ta = 25C, VCC = 5V, See the Electrical Characteristics Measurement Circuit.)
S1 S2 S3 S4 Measurement conditions No input signal, SG5: CSYNC TTL level, SG4: SIN wave 3.58MHz 0.5Vp-p Fig. 1 Min. Typ. Max. Unit MeasureRIN SYNC ment pin GIN SCIN NPIN IN BIN ICC1 2.75V SG4 5V SG5
Item
Symbol
Current consumption 1 Current consumption 2 (R, G, BOUT)
ICC1
--
67
-- mA
ICC2
ICC2
--
40
--
VO (R) RGB output voltage VO (G) VO (B) fC (R) RGB output frequency characteristics fC (G) fC (B) (YOUT) Output sync level R100%: Y level G100%: Y level B100%: Y level White 100%: Y level VO (YS1/2) VO (YR1/2)
SG1 SG2 SG3 SG1 SG2 SG3 2V 2V
D E F D E F
SG1 to SG3: DC direct coupling 3.2VDC, 1.0Vp-p f = 200kHz Pin 9 = Clamp voltage Fig. 2 SG1 to SG3: DC direct coupling 3.2VDC, 1.0Vp-p f = 27MHz/200kHz Pin 9 = Clamp voltage Fig. 3
0.64
0.69
0.72
V
-5 -5 -5
-3.2 -3.4 -3.8
-- -- --
dB dB dB
SG1 0V VO (YG1/2) to SG3 VO (YB1/2) VO (YW1/2) SG1 to 0V SG3
5V SG5
B
SG1 to SG3: 100% color bar input, 1.0Vp-p (Max.) SG5: CSYNC TTL level Fig. 4 SG1 to SG3: DC direct coupling 3.2VDC, 1.0Vp-p f = 5MHz/200kHz Pin 9 = Clamp voltage
0.24 0.19 0.38 0.06 0.63
0.27 0.215 0.405 0.076 0.682
0.31 0.24 0.43 0.09 0.79 Vp-p
Output frequency characteristics
fC (Y1/2)
5V
2V
-1
-0.13
--
dB
(CVOUT) Output sync level R100%: Y level G100%: Y level B100%: Y level White 100%: Y level VO (YS1/2) VO (YR1/2) SG1 0V VO (YG1/2) to SG3 VO (YB1/2) VO (YW1/2) SG1 to 0V SG3 SG1 to SG3: 100% color bar input, 1.0Vp-p (Max.) SG5: CSYNC TTL level Fig. 4 SG1 to SG3: DC direct coupling 3.2VDC, 1.0Vp-p f = 5MHz/200kHz Pin 9 = Clamp voltage 0.22 0.18 0.35 0.055 0.61 0.24 0.208 0.376 0.071 0.66 0.27 0.23 0.41 0.085 0.75 Vp-p V V V V
5V SG5
C
Output frequency characteristics
fC (Y1/2)
5V
2V
-3.3
-1.53
--
dB
Clamp voltage: voltage appearing at Pin 9 when CSYNC is input. -5-
CXA2075M
S1 Item Symbol
S2
S3
S4 Measurement conditions Min. Typ. Max. Unit
MeasureRIN SYNC ment pin GIN SCIN NPIN IN BIN
(COUT) Burst level R chroma ratio R phase G chroma ratio G phase B chroma ratio B phase Burst width Burst position VO (BN1/2) R/BN1/2 R1/2 G/BN1/2 G1/2 B/BN1/2 B1/2 SG1 to SG4 SG3 SG1 to SG3: 100% color bar input, 1.0Vp-p (Max.) SG4: SIN wave, 3.58MHz 0.5Vp-p SG5: CSYNC TTL level Fig. 5 0.24 2.8 99 2.7 232 1.8 341 2.35 0.35 SG1 to SG3: No signal, SG4: SIN wave, 3.58MHz 0.5Vp-p SG5: CSYNC TTL level 3.58MHz component measured. Fig. 6 0.282 3.17 104 3.06 238 2.1 348 2.6 0.68 0.34 3.6 111 3.8 246 2.35 356 2.8 0.95 deg s s deg deg Vp-p
5V SG5
tW (B) 1/2 tD (B) 1/2
A
Carrier leak
VL1/2
SG1 to SG4 SG3
5V SG5
--
6
29
mVp-p
-6-
CXA2075M
S1 Item Symbol
S2
S3
S4 Measurement conditions Min. Typ. Max. Unit
MeasureRIN SYNC ment pin GIN SCIN NPIN IN BIN
(CVOUT) Burst level R chroma ratio R phase G chroma ratio G phase B chroma ratio B phase Burst width Burst position VO (BN1/2) R/BN1/2 R1/2 G/BN1/2 G1/2 B/BN1/2 B1/2 SG1 to SG4 SG3 SG1 to SG3: 100% color bar input, 1.0Vp-p (Max.) SG4: SIN wave, 3.58MHz 0.5Vp-p SG5: CSYNC TTL level Fig. 5 0.22 2.95 99 2.9 233 1.8 342 2.35 0.35 C SG1 to SG4 SG3 SG1 to SG3: No signal, SG4: SIN wave, 3.58MHz 0.5Vp-p SG5: CSYNC TTL level 3.58MHz component measured. Fig. 6 SG1 to SG3: No signal, SG4: SIN wave, 4.43MHz 0.5Vp-p SG5: CSYNC TTL level Fig. 6 SG1 to SG3: DC direct coupling 3.2VDC 1.0Vp-p f = 3.58MHz/200kHz YTRAP = 3.32k 0.264 3.3 105 3.23 239 2.02 349 2.52 0.66 0.32 3.7 111 3.5 247 2.3 357 2.8 0.95 deg s s deg deg Vp-p
5V SG5
tW (B) 1/2 tD (B) 1/2
Carrier leak
VL1/2
5V SG5
--
6
29
mVp-p
PAL burst level ratio
K (BP1/2) PAL1/2 SG1 to SG4 GND SG5 SG3
0.9 129 214
1.0 138 221
1.1 146 228 deg deg
PAL burst phase XPAL1/2
Internal TRAP attenuation frequency
fTRAP
SG1 to 0V SG3
5V
2V
C
-30
-21.6
-4
dB
-7-
Electrical Characteristics Measurement Circuit
47 75 D 220 3.32k open 75 YOUT 16 15 14 13 COUT NC NC 75 YTRAP 17 S5 CVOUT 20 VIDEO OUT TRAP SWITCH 75 DRIVER 75 DRIVER INTERNAL TRAP DELAY BPF R-Y Modulator REGULATOR LPF B-Y Modulator SYNC ADD B-OUT Y/C MIX 19 18 Vcc2 NC 0.01 Icc2 75 BOUT 21 5V 220 220 C B A 5V 75 75
75
75
75
F
E
220
220
220
75
75
75
GND2
ROUT
GOUT
24
23
22
R-OUT
G-OUT
CLAMP SIN-PULSE
MATRIX
-8-
LPF PHASE SHIFTER 8 NPIN S3 BFOUT PHASE SHIFTER 9 NC 10 4 BIN S1 0.1 SG3 S2 NC SCIN 5 6 7 5V 2V SG4 SIN 0.5Vp-p PAL NTSC
1
2
3
11 SYNC IN S4 NC
12 Vcc1 0.01 47 SG5 CSYNC Icc1 5V CXA2075M
GND1
RIN
GIN
S1
S1
0.1
0.1
2.75V
SG1
SG2
CXA2075M
Measuring Signals and Output Waveforms
SG4 0.5Vp-p SCIN SG5 SYNC IN 64s 4.5s f = 3.58MHz 2.0V 0.8V SG5 SYNC IN SG1 RIN SG2 GIN SG3 BIN SG1 to 3 RIN GIN BIN DEF point ROUT GOUT BOUT VO 2.5V 1.0Vp-p BC point YOUT CVOUT Vo (YB) Vo (YW) Vo (YG) Vo (YR) Vo (YS) 1.0Vp-p 64s 4.5s 10s 1.0Vp-p 2.0V 0.8V
Fig. 1
1.0Vp-p
f = 200kHz
Fig. 4
Fig. 2
SG4 0.5Vp-p SCIN f = 3.58MHz
SG1 to 3 RIN GIN BIN DEF BC point ROUT GOUT BOUT YOUT CVOUT 2.5V 1.0Vp-p
SG5 SYNC IN 64s 4.5s 10s VO Vo (27MHz) Vo (200kHz) SG2 GIN SG1 RIN
2.0V 0.8V
f = 200kHz/27MHz
1.0Vp-p
Fig. 3
fc = 20log
1.0Vp-p
SG3 BIN SG4 0.5Vp-p SCIN f = 3.58MHz/ 4.43MHz SG4 SYNC IN C point CVOUT Vo (BN) A point COUT VL K (BP) = Vo (BN) Vo (BN) Vo (BN) 64s 4.5s Vo (BN) VL Vo (BN) tW (B) 2.0V 0.8V A point COUT VO (BN) C point CVOUT tD (B) VO (BN) VO (CG) VO (CB) VO (CR) tW (B)
1.0Vp-p
R/BN = G/BN = B/BN =
VO (CR) VO (BN) VO (CG) VO (BN) VO (CB) VO (BN)
VO (CB) VO (CG) VO (CR)
Fig. 5
Fig. 6 -9-
CXA2075M
Application Circuit (NTSC internal TRAP mode)
47 220 220 75 GND2 24 23 ROUT 22 220 75 GOUT 21 220 75 240 43 BOUT 20 VIDEO OUT R-OUT G-OUT B-OUT Y/C MIX 0.01 CVOUT 19 Vcc2 NC 18 17 3.32k/1% for NTSC 220 75 YTRAP 16 220 75 YOUT 15 COUT NC 14 NC 13 Vcc +5V
TRAP SWITCH INTERNAL TRAP DELAY SYNC ADD
75 DRIVER
75 DRIVER
BPF R-Y Modulator REGULATOR B-Y Modulator PHASE SHIFTER 8 PHASE SHIFTER 9 NC 10 SYNC IN 11 NC 0.01 12 Vcc1 47
MATRIX
LPF
LPF
CLAMP
SIN-PULSE
1 GND1
2 RIN 0.1
3 GIN 0.1
4 BIN 0.1
5 NC
6 SCIN
7 NPIN
BFOUT
Metal film resistor 1%
Application Circuit (NTSC external TRAP mode)
47 220 220 75 GND2 24 23 ROUT 22 220 75 GOUT 21 220 75 240 43 BOUT 20 VIDEO OUT R-OUT G-OUT B-OUT Y/C MIX 0.01 CVOUT 19 Vcc2 NC 18 17 75 YTRAP 16 75 YOUT 15 COUT NC 14 NC 13 220 220 Vcc +5V
TRAP SWITCH INTERNAL TRAP DELAY SYNC ADD
75 DRIVER
75 DRIVER
BPF R-Y Modulator REGULATOR B-Y Modulator PHASE SHIFTER 8 PHASE SHIFTER 9 NC 10 SYNC IN 11 NC 0.01 12 Vcc1 47
MATRIX
LPF
LPF
CLAMP
SIN-PULSE
1 GND1
2 RIN 0.1
3 GIN 0.1
4 BIN 0.1
5 NC
6 SCIN
7 NPIN
BFOUT
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 10 -
CXA2075M
Application Circuit (PAL internal TRAP mode)
47 220 220 75 GND2 24 23 ROUT 22 220 75 GOUT 21 220 75 240 43 BOUT 20 VIDEO OUT R-OUT G-OUT B-OUT Y/C MIX 0.01 CVOUT 19 Vcc2 NC 18 17 2.61k/1% for PAL 220 75 YTRAP 16 220 75 YOUT 15 COUT NC 14 NC 13 Vcc +5V
TRAP SWITCH INTERNAL TRAP DELAY SYNC ADD
75 DRIVER
75 DRIVER
BPF R-Y Modulator REGULATOR B-Y Modulator PHASE SHIFTER 8 PHASE SHIFTER 9 NC 10 SYNC IN 11 NC 0.01 12 Vcc1 47
MATRIX
LPF
LPF
CLAMP
SIN-PULSE
1 GND1
2 RIN 0.1
3 GIN 0.1
4 BIN 0.1
5 NC
6 SCIN
7 NPIN
BFOUT
Metal film resistor 1%
Application Circuit (PAL external TRAP mode)
47 220 220 75 GND2 24 23 ROUT 22 220 75 GOUT 21 220 75 240 BOUT 43 20 VIDEO OUT R-OUT G-OUT B-OUT Y/C MIX 0.01 CVOUT 19 Vcc2 NC 18 17 75 YTRAP 16 75 YOUT 15 COUT NC 14 NC 13 220 220 Vcc +5V
TRAP SWITCH INTERNAL TRAP DELAY SYNC ADD
75 DRIVER
75 DRIVER
BPF R-Y Modulator REGULATOR B-Y Modulator PHASE SHIFTER 8 PHASE SHIFTER 9 NC 10 SYNC IN 11 NC 0.01 12 Vcc1 47
MATRIX
LPF
LPF
CLAMP
SIN-PULSE
1 GND1
2 RIN 0.1
3 GIN 0.1
4 BIN 0.1
5 NC
6 SCIN
7 NPIN
BFOUT
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 11 -
CXA2075M
Description of Operation Analog RGB signals input from Pins 2, 3 and 4 are clamped in the clamping circuit and output from Pins 23, 22 and 21, respectively. The matrix circuit performs operations on each input signal, generating luminance signal Y and color difference signals R-Y and B-Y. The Y signal enters the delay line to adjust delay time with the chroma signal C. Then, after addition of the CSYNC signal input from Pin 10, the Y signal is output from Pin 16. A subcarrier input from Pin 6 is input to the phase shifter, where its phase is sfited 90. Then, the subcarrier is input to the modulators and modulated by the R-Y signal and the B-Y signal. The modulated subcarriers are mixed, sent to the band-pass filter to eliminate higher harmonic components and finally output from Pin 15 as the C signal. At the same time, Y and C signals are mixed and output from Pin 20 as the composite video signal.
Burst Signal The CXA2075M generates burst signals at the timing shown below according to the composite sync signal input. H synchronization
SYNC IN (TTL level) tD (B) tW (B)
C VIDEO OUT Burst signal COUT
tD (B)
tW (B)
V synchronization
ODD SYNC IN EVEN
ODD C VIDEO OUT EVEN Burst signal Synchronizing signal
- 12 -
CXA2075M
Notes on Operation Be careful of the following when using the CXA2075M. 1. Be sure that analog RGB signals are input at 1.0Vp-p maximum and have low enough impedance. High impedance may affect color saturation, hue, etc. Inputting RGB signals in excess of 1.3Vp-p may disable the clamp operation. 2. The SC input (Pin 6) can be either a sine wave or a pulse in the range from 0.4 to 5.0Vp-p. However, when a pulse is input, its phase may be shifted several degrees from that of the sine wave input. In the IC, the SC input is biased to 1/2 VCC. Accordingly, when a 5.0Vp-p pulse is input and the duty factor deviates from 50%, High- and Low-level pulse voltages may exceed VCC and GND in the IC, which causes subcarrier distortion. In such a case, be very careful that the duty factor keeps to 50%. 3. When designing a printed circuit board pattern, pay careful attention to the routing of the VCC and GND leads. To decouple the VCC pin, use tantalum, ceramic or other capacitors with good frequency characteristics. Ground the capacitors by connections shown below as closely to each IC pin as possible. Try to design the leads as short and wide as possible. VCC1... GND1 VCC2... GND2 Design the pattern so that VCC is connected to GND via a capacitor at the shortest distance. 4. SC and SYNC input pulses Attach a resistor and a capacitor to eliminate high-frequency components of SC (Fig. A) and SYNC (Fig. B) before input.
2.2k 5P 2.2k 47P
Fig. A
Fig. B
Be careful not to input pulses containing high-frequency components. Otherwise, high-frequency components may flow into VCC, GND and peripheral parts, resulting in malfunctions. 5. Connecting an external resistor to the 75 driver output pin A capacitance of several dozen picofarads at each pin may start oscillation. To prevent oscillation, design the pattern so that a 75 resistor is mounted near the pin (see Fig. C).
75 Make these leads short.
Fig. C When any of the 75 driver output pins is not in use, leave it unconnected and design the pattern so that no parasitic capacitance is generated on the printed circuit board.
- 13 -
CXA2075M
6. YTRAP pin (Pin 17) There are the following three means of reducing cross color generated by subcarrier frequency components contained in the Y signal. (1) Install a capacitor of 30 to 68pF between YTRAP and GND. Decide the capacitance by conducting image evaluation, etc., giving consideration to both cross color and resolution. Relations between capacitance and picture quality are as follows: Capacitance Cross color Resolution 30pF 68pF Large Small High Low
17 C
(2)
Connect a capacitor C and an inductor L in series between YTRAP and GND. When the subcarrier 1 frequency is f0, the values C and L are determined by the equation f0 = . Decide the values in 2 LC image evaluation, etc., giving consideration to both cross color and resolution. Relations between inductor values and picture quality are as follows: Inductor value Cross color Resolution Small Large Large Small High Low
17 C L
For instance, L = 68H and C = 28pF are recommended for NTSC. It is necessary to select an inductor L with a sufficiently small DC resistance. Method (2) is more useful for achieving a higher resoluation than method (1). When an even higher resolution is necessary, use of the S terminal (YOUT and COUT) is recommended. (3) TRAP built in the IC can be used. Connect a resistor which determines to between YTRAP (Pin 17) and Vcc. Refer to Application Circuit. Be very careful of frequency characteristics and picture quality, and then use them.
17
NTSC mode PAL mode
R = 3.32k R = 2.61k
R Vcc
7. Driving COUT (Pin 15), YOUT (Pin 16), CVOUT (Pin 20), and B.G.R OUT (Pins 21, 22 and 23) outputs In Pin Description, "Capable of driving a 75 load" means that the pin can drive a capacitor +75 +75 load shown in the figure below. In other words, the pin is capable of driving a 150 load in AC.
75 PIN 75 220F
8. This IC employs a number of 75 driver pins, so oscillation is likely to occur when measures described in Nos. 3 and 5 are not taken thoroughly. Be very careful of oscillation in printed circuit board design and carry out thorough investigations in the actual driving condition.
- 14 -
CXA2075M
Package Outline
Unit: mm
24PIN SOP (PLASTIC)
+ 0.4 15.0 - 0.1 24 13
+ 0.4 1.85 - 0.15
0.15
+ 0.3 5.3 - 0.1
7.9 0.4
+ 0.2 0.1 - 0.05
0.45 0.1
1.27
+ 0.1 0.2 - 0.05
0.12 M
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SOP-24P-L01 SOP024-P-0300-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY/PHENOL RESIN SOLDER PLATING
COPPER ALLOY / 42ALLOY
0.3g
- 15 -
0.5 0.2
1
12
6.9

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