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| Datasheet File OCR Text: |
| HI-8020/HI-8120 January 2001 GENERAL DESCRIPTION The HI-8020 & HI-8120 high voltage display drivers are functional replacements for the AMI S5420 and Micrel MIC8013/8014 series. These CMOS products are designed to drive liquid crystal displays by converting 5 volt serial data to parallel segment and backplane waveforms with amplitudes up to 30 volts. The HI-8020 & HI-8120 differ from the HI-8010 by only the shift register clock and chip select gating logic. The HI-8020 has TTL logic inputs whereas the HI-8120 has CMOS logic inputs. Both devices can drive up to 38 segments and have 3 possible shift register data taps to provide options to cascade devices for larger displays. Data is clocked into a 38 stage shift register and parallel latched before the output translators by a Load input. The HI-8020 & HI-8120 are available in a variety of ceramic and plastic packaging including DIP; leaded and leadless chip carriers; and J-lead and gull-wing quad flat packs. PIN CONFIGURATION (Top View) S27 S28 S29 S30 S31 S32 N/C VSS CS CL LD 7 8 9 10 11 12 13 14 15 16 17 39 38 HI-8020J-85 & HI-8120J-85 44 - PIN PLASTIC PLCC 37 36 35 34 33 32 31 30 29 S17 S16 S15 VEE S14 S13 S12 S11 S10 S9 S8 (See page 3-6 for additional package pin configurations) FEATURES ! 5 volt input translated to 30 volts or less ! Pin-out adaptable to drive 30, 32 or 38 LCD segments ! RC oscillator or high voltage (BP) clock input ! TTL compatible inputs (HI-8020 only) ! CMOS compatible inputs (HI-8120 only) ! Low power consumption ! Industrial (-40C to +85C) & Military (-55C to +125C) temperature ranges ! Pin for pin compatible with the Micrel MIC8010/8011 series and the AMI S4520 series drivers ! Cascadable ! Military level processing available H i g h Voltage Buffer FUNCTIONAL BLOCK DIAGRAM DIN CL CS LD LCDO OPT LCDO Oscillator Divider Voltage Translator 38 Bit Latch DATA IN 38 Stage Shift Register CLK DOUT 38 DOUT 32 DOUT 30 Voltage Translators High Voltage Drivers ! Dichroic Liquid Crystal Displays ! Standard Liquid Crystal Displays ! Vacuum Fluorescent Displays HOLT INTEGRATED CIRCUITS 3-9 BP SEGMENTS (DS8020 Rev. B) 01/01 HI-8020/HI-8120 Series FUNCTIONAL DESCRIPTION Whenever a Logic "0" is applied to the Chip Select (CS) input, one bit of data is clocked into the shift register from the serial data input (DIN) with each negative transition of the Clock (CL) input. CS is internally tied to VSS on some versions. A Logic "1" present at the Load (LD) input will cause a parallel transfer of data from the shift register to the data latch. If the Load (LD) input is held high while data is clocked into the shift register, the latch will be transparent. All four logic inputs are TTL compatible on the HI-8020 and CMOS compatible on the HI-8120. To display segments, a Logic "1" is stored in the appropriate shift register bit position, and the segment output is out-ofphase with the backplane. The backplane output functions in 1 of 2 modes; externally driven or self-oscillating. When the LCDO input is externally driven with the LCDOOPT input open circuit (Figure 2), the backplane output will be in-phase with LCDO. Utilizing the self-oscillating mode, inputs LCDO and LCDOOPT are tied together and connected to an RC circuit (Figure 3). A 150KW resistor with a 470pF capacitor generates an approximate backplane frequency of 100Hz. The LCDO/LCDOOPT oscillator frequency is divided by 256 to determine the backplane output frequency. The resistor value (R) must be at least 30KW for proper self-oscillator operation. For displays having a number of segments greater than 38, two or more of the display drivers may be cascaded together by connecting the serial data output (DOUT) from the first driver, to the serial data input (DIN) of the following driver, etc.(See Figures 2 & 3). Data out (DOUT) will change state C R on the rising edge of the Clock (CL). Clock (CL), Load (LD) and Chip Select (CS) should be tied in common with each other, respectively, between all cascaded display drivers. INTERNAL OSCILLATOR CIRCUIT / 256 Q LCDO LCDO OPT TO BACKPLANE TRANSLATOR AND DRIVER Figure 1. TIMING DIAGRAM CL INPUT tCL DIN INPUT VALID tDS tDH CS INPUT tCSS tCSH LD INPUT tLCS tCSL tCDO DOUT OUTPUT VALID tLS tLW VALID HOLT INTEGRATED CIRCUITS 3-10 HI-8020/HI-8120 Series Voltages referenced to VSS = 0V VDD........................ 0V to 7V VEE................VDD-35V to 0V Voltage at any input, except LCDO..-0.3 to VDD+0.3V Voltage at LCDO input...............VDD-35 to VDD+0.3V DC Current any input pin...................................10 mA Supply Voltage Power Dissipation......................................................300 mW Operating Temperature Range - Industrial........-40 to +85C Operating Temperature Range - Hi-Temp/Mil..-55 to +125C Storage Temperature Range...........................-65 to +150C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER Operating Voltage Supply Current SYMBOL VDD IDD IEE CONDITION MIN 3.0 TYP MAX 7.0 200 150 UNITS V A A V V V V V V A pF W W mA mA Static, No Load Static, No Load fBP=100Hz 0 2 0 0.7 VDD VEE 3.5 VIN = 0 to 5V Input Low Voltage, HI-8020 (except LCDO) Input High Voltage, HI-8020 (except LCDO) Input Low Voltage, HI-8120 (except LCDO) Input High Voltage, HI-8120 (except LCDO) Input Low Voltage (LCDO) Input High Voltage (LCDO) Input Current Input Capacitance (not tested) Segment Output Impedance Backplane Output Impedance Data Out Current: VILTTL VIHTTL VILCMOS VIHCMOS VILX VIHX IIN CI RSEG RBP IDOH IDOL IL = 10A IL = 10A Source Current, VOH = 4.5V Sink Current, VOL = 0.5V 0.8 VDD 0.3 VDD VDD 3 VDD 1 5 10,000 450 -0.6 0.6 AC ELECTRICAL CHARACTERISTICS VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER Clock Period Clock Pulse Width Data In - Setup Data In - Hold Chip Select - Setup to Clock Chip Select - Hold to Clock Load - Setup to Clock Chip Select - Setup to Load Load Pulse Width Chip Select - Hold to Load Data Out Valid, from Clock SYMBOL tCL tCW tDS tDH tCSS tCSH tLS tCSL tLW tLCS tCDO VDD 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V MIN 1200 520 50 400 200 450 500 300 500 300 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns 800 ns HOLT INTEGRATED CIRCUITS 3-11 HI-8020/HI-8120 Series CASCADING - EXT. OSCILLATOR LD CL CS CS DIN CL LD DOUT CS DIN CL LD DOUT CS DIN CL LD DOUT CASCADING - RC OSCILLATOR LD CL CS CS DIN 150KW CL LD DOUT CS DIN CL LD DOUT CS DIN CL LD DOUT HI-8020J-85 LCDO BP HI-8020J-85 LCDO BP HI-8020J-85 LCDO BP HI-8120J-85 LCDO LCDO OPT BP HI-8120J-85 LCDO LCDO OPT BP HI-8120J-85 LCDO LCDO OPT BP 470pf SEGMENTS 1 - 33 SEGMENTS BACK 33 - 64 PLANE SEGMENTS 65 - 96 SEGMENTS 1 - 32 SEGMENTS BACK PLANE 33 - 64 SEGMENTS 65 - 96 Figure 2 Figure 3 PIN DESCRIPTIONS SYMBOL VSS CS CL LD DIN LCD0 LCD0OPT VDD VEE DOUT BP Segments FUNCTION POWER INPUT INPUT INPUT INPUT INPUT OUTPUT POWER POWER OUTPUT OUTPUT OUTPUT 0 Volts Logic input Logic input Logic input Logic input Analog input Analog output 5 Volts O Volts to -30 Volts Logic output Display drive output Display drive output DESCRIPTION Chip select Clocks shift register on negative edge and DOUT pins on positive edge Segment outputs equal shift register data if Load is high Shift register data input Display clock input and is always bonded out. Can swing from VEE to VDD Bonded out only if an RC oscillator is required Selected pinout can provide shift register taps at positions 30, 32, 34, or 38 Low resistance drive for the backplane and swings from VDD to VEE High resistance drive for each segment and swings from VDD to VEE ADDITIONAL HI-8020/HI-8120 PIN CONFIGURATIONS (See page 3-9 for 44-Pin Plastic PLCC) S17 S18 S19 BP DOUT 38 S20 S21 S22 S23 S24 S25 S26 7 8 9 10 11 12 13 14 15 16 17 18 42 HI-8020S-61 HI-8120S-61 HI-8020SM-62 & HI-8120SM-62 48 - PIN CERAMIC LCC 41 40 39 38 37 36 35 34 33 32 S5 S4 S3 S2 S1 S38 S37 VDD LCDO/LCDOOPT DIN LD CL S17 S18 S19 BP DOUT 38 S20 S21 S22 S23 S24 S25 S26 7 8 9 10 11 12 13 14 15 16 17 18 42 HI-8020S-63 HI-8120S-63 HI-8020SM-64 & HI-8120SM-64 48 - PIN CERAMIC LCC 41 40 39 38 37 36 35 34 33 32 S5 S4 S3 S2 S1 S38 S37 VDD LCDO DIN LD CL HOLT INTEGRATED CIRCUITS 3-12 HI-8020/HI-8120 Series ORDERING INFORMATION PART NUMBER OF MASTER PACKAGE TEMPERATURE BURN LEAD NUMBER TTL Input Logic HI-8020J-85 HI-8020S-61 HI-8020SM-62 HI-8020S-63 HI-8020SM-64 SEGMENTS 32 38 38 38 38 32 38 38 38 38 /SLAVE DESCRIPTION RANGE -40C TO +85C -40C TO +85C FLOW I I M I M I I M I M IN NO NO YES NO YES NO NO YES NO YES FINISH SOLDER GOLD SOLDER GOLD SOLDER SOLDER GOLD SOLDER GOLD SOLDER BOTH 44 PIN PLASTIC J LEAD MASTER 48 PIN CERAMIC LEADLESS CHIP CARRIER MASTER 48 PIN CERAMIC LEADLESS CHIP CARRIER -55C TO +125C SLAVE 48 PIN CERAMIC LEADLESS CHIP CARRIER -40C TO +85C SLAVE 48 PIN CERAMIC LEADLESS CHIP CARRIER -55C TO +125C BOTH MASTER MASTER SLAVE SLAVE 44 PIN PLASTIC J LEAD -40C TO +85C 48 PIN CERAMIC LEADLESS CHIP CARRIER -40C TO +85C 48 PIN CERAMIC LEADLESS CHIP CARRIER -55C TO +125C 48 PIN CERAMIC LEADLESS CHIP CARRIER -40C TO +85C 48 PIN CERAMIC LEADLESS CHIP CARRIER -55C TO +125C CMOS Input Logic HI-8120J-85 HI-8120S-61 HI-8120SM-62 HI-8120S-63 HI-8120SM-64 SEMI-CUSTOM PACKAGING The above part numbers represent some of the typical configurations of the HI-8020 & HI-8120 products. They can also be provided with a varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide variety of packages. Listed below are currently available packages. Please contact the Holt Sales Department for your specific requirements. PACKAGE DESCRIPTION PLASTIC DUAL-IN-LINE (PDIP) NO. LEADS 40 48 PLASTIC QUAD FLAT PACK (PQFP) PLASTIC J-LEAD CHIP CARRIER (PLCC) CERAMIC DUAL-IN-LINE (CDIP) 52 44 40 48 CERAMIC LEADLESS CHIP CARRIER (LCC) 40 48 CERAMIC J-LEAD CHIP CARRIER 44 48 CERAMIC LEADED CHIP CARRIER 40 48 HOLT INTEGRATED CIRCUITS 3-13 HI-8020/HI-8120 PACKAGE DIMENSIONS inches (millimeters) 44-PIN PLASTIC PLCC Package Type: 44J PIN NO. 1 .045 x 45 PIN NO. 1 IDENT .045 x 45 .050 .005 (1.27 .127) .690 .005 (17.526 .127) SQ. .653 .004 (16.586 .102) SQ. .031 .005 (.787 .127) .017 .004 (.432 .102) SEE DETAIL A .009 .011 .172 .008 (4.369 .203) .610 .020 (15.494 .508) DETAIL A .015 .002 (.381 .051) .020 MIN (.508 ) R .025 .045 48-PIN CERAMIC LEADLESS CHIP CARRIER Package Type: 48S PIN 1 IDENT. .090 MAX. (2.286 MAX.) .040 .007 (1.016 .178) PIN 1 IDENT. .563 .009 (14.300 .228) SQ. .020 TYP. (.508 TYP.) .040 TYP. (1.016 TYP.) HOLT INTEGRATED CIRCUITS 1 |
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