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ICs for Consumer Electronics
DDC-PLUS-Deflection Controller SDA 9361
Data Sheet 1998-02-01
Edition 1998-02-01 This edition was realized using the software system FrameMaker(R) Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SDA 9361 Revision History: Previous Version: Page Page (in previous (in current Version) Version) 33 35 35 35 37 37
Current Version: 1998-02-01 1997-04-07 Subjects (major changes since last revision)
Setup time of input HSYNC (CLEXT=1) changed from 6 ns to 4 ns Nom. average and max. stand-by current specified Specification of charge current pump of PLL pin LF is unnecessary
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA=25C and the nominal supply voltage. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit.
Edition 1998-02-01 Published by Siemens AG, Semiconductor Group Copyright (c) Siemens AG 1998. All rights reserved. Terms of delivery and right to change design reserved.
SDA 9361
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 3 3.1 3.2 4 5 5.1 5.2 5.3 5.4 5.5 6
Page 5 5 6 6 7 9 10 10 12 14 15 16 16 16 17 18 24
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC-Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Explanation of Some Control Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 37 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD- Output Voltage, 4/3-CRT and 16/9-Source . . . . . . . . . . . . . . . . . . . . . . Timing Diagram of SCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On/Off Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Mode, RESN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function of H,V Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 42 44 45 46
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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DDC-PLUS-Deflection Controller
SDA 9361
MOS 1 1.1 * * * * * * * * * * * * * * * * * * * * * Overview Features
Deflection - Protection - 16:9 / 4:3 No external clock needed 1 PLL and 2 PLL on chip 2C-Bus alignment of all deflection parameters P-MQFP-44-2 All EW-, V- and H- functions PW EHT compensation PH EHT compensation Compensation of H-phase deviation (e.g. caused by white bar) Upper/lower EW-corner correction separately adjustable V-angle correction: Vertical frequent linear modulation of H-phase V-bow correction: Vertical frequent parabolic modulation of H-phase Three reduced V-scan modes (75 %, 66 %, 50 % V-size) adjustable by only 2 Bits H-frequent PWM output signal for general purpose H- and V-blanking time adjustable Partial overscan adjustable to hide the cut off control measuring lines in the reducedscan modes Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different letterbox formats without annoying overscan Control signal SCAN as reference for vertical positioning of OSD, PIP etc. Vertical noise reduction with memory Standard and doubled line frequencies for NTSC and PAL, MUSE standard, ATV standard, HDTV standard Self adaptation of V-frequency/number of lines per field between 192 and 680 for each possible line frequency Protection against EHT run away (X-rays protection)
Type SDA 9361
Semiconductor Group
Ordering Code Q67107-H5167-A703
5
Package P-MQFP-44-2
1998-02-01
SDA 9361
* * * * *
Protection against missing V-deflection (CRT-protection) Selectable softstart of the H-output stage Clock generation on chip P-MQFP-44-2 package 5 V supply voltage General Description
1.2
The SDA 9361 is a highly integrated deflection controller for CTV receivers with standard or doubled line and field frequencies. It controls among others an horizontal driver circuit for a flyback line output stage, a DC coupled vertical saw-tooth output stage and an east/ west raster correction circuit. All adjustable output parameters are 2C Bus controlled. Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock system which includes the 1 and 2 control loops. 1.3 Pin Configuration
VDD(A3) HSYNC VREFC VSS(A3) VDD(D) VSS(D) SSD VSS(A4) LF VDD(A4) VOFFD
34 35 36 37 38 39 40 41 42 43 44
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11
SELFH1_2 CLEXT FH1_2 TEST HD VSYNC PWM 2 VREFH VREFL VSS(A2)
VDVD+ E/W VDD(A2) VREFP VREFN VSSA(1) ABL D/A VDDA(1) HPROT
CLKI X1 X2 SDAT SCLK RESN SCAN SCP VDD(D) VSS(D) VPROT
UEP10278
Figure 1
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SDA 9361
1.4
Pin Description Type I/TTL I Q IQ I I/TTL Q/TTL Q S S I I S Q I S IQ IQ S Q Q Q S IQ IQ I Q/TTL Description Input for external clock Reference oscillator input, crystal Reference oscillator output, crystal
Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 CLKI X1 X2 SDAT SCLK RESN SCAN SCP
2C-Bus data 2C-Bus clock
Reset input, active low Control signal for vertical positioning of OSD, PIP etc. Blanking signal with H- and color burst component (V-component selectable by 2C Bus) Digital supply Digital ground Watching external V-output stage (input is the V-sawtooth from feedback resistor) Watching EHT (input is e.g. H-flyback) Analog supply Output of an 2C Bus controlled DC voltage Input for a beam current dependent signal for stabilization of width, height and H-phase Analog ground Ground for VREFP, VREFH, VREFL Reference voltage for IBEAM ADC, DAC, HPROT / VPROT thresholds Analog supply Control signal output for east/west raster correction Control signal output for DC coupled V-output stage Like VD+ Analog ground Reference voltages for E/W-DAC, V-DAC Like VREFL Line flyback for H-delay compensation Control signal output
VDD(D) VSS(D)
VPROT HPROT
VDD(A1)
D/A ABL
VSS(A1) VREFN VREFP VDD(A2)
E/W VD+ VD-
VSS(A2) VREFL VREFH 2
PWM
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SDA 9361
1.4
Pin Description (cont'd) Type I/TTL Q I/TTL Description V-sync input Control signal output for H driver stage Switching normal operation (TEST = L) and test mode (TEST = H: pins 7, 27, 31, 32, 33, 40, 44 are additional test pins) Switching between 1FH mode (L) and 2FH mode (H) (Pin SELFH1_2 = 0) Switching between internal (L) and external clock (H)1) Selection of switching between 1FH mode and 2FH mode SELFH1_2 = 0:1FH/2FH selected via pin FH1_2 SELFH1_2 = 1:1FH/2FH selected via 2C-Bus register 00H, Bit D5 Analog supply HSYNC input (CLEXT = 1: TTL; CLEXT = 0: analog)1) Reference voltage for sync ADC Analog ground Digital supply Digital ground Disables softstart Analog ground PLL loop filter Analog supply Defines default value of VOFF-Bit (2C-Bus register 00H, Bit D7)
Pin No. Symbol 28 29 30 VSYNC HD TEST
31 32 33
FH1_2 CLEXT
I/TTL I/TTL
SELFH1_2 I/TTL
34 35 36 37 38 39 40 41 42 43 44
1)
VDD(A3)
HSYNC
S I I S S S I/TTL S IQ S I/TTL
VREFC VSS(A3) VDD(D) VSS(D)
SSD
VSS(A4)
LF
VDD(A4)
VOFFD
The external clock mode can not be used with 33.75 kHz and 35 kHz line frequency.
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SDA 9361
1.5
Block Diagram
SCP SCAN HPROT SSD VPROT
2
SCLK SDAT VOFFD SELFH1_2 FH1_2 TEST CLEXT VSYNC HSYNC
2C
Protection Start Up
H-Out
HD
V-Out Control EW-Corr
VD+ VD-
E/W
CLL CLKI
PWM
PWM
D/A
D/A
PLL LF PW/PH Corr
X1 X2
VREFC
VREFL
VREFH
VREFP
VREFN
ABL
UEB10277
Figure 2
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SDA 9361
2 2.1
System Description Functional Description
The main input signals are HSYNC with standard or doubled horizontal frequency and VSYNC with vertical frequencies of 50/100 Hz or 60/120 Hz. The VSYNC is processed in a noise reduction circuit to enable synchronization by worse transmission too. The output signals control the horizontal as well as the vertical deflection stages and the east/west raster correction circuit. The H-output signal HD compensates the delays of the line output stage and its phase can be modulated vertical frequent to remove horizontal distortions of vertical raster lines (V-Bow, V-Angle). Time reference is the middle of the front and back edge of the line flyback pulse. A positive HD pulse switches off the line output transistor. Maximal H-shift is about 4.5 s (for 1FH) or 2.25 s (for 2FH). Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the aspect ratio of the source signal. The V-output saw-tooth signals VD- and VD+ controls a DC coupled output stage and can be disabled. Suitable blanking signals are delivered by the IC. The east/west output signal E/W is a vertical frequent parabola of 4th order, enabling an additional corner correction, separately for the upper and lower part. The pulse width modulated horizontal frequent output signal PWM is for optional use. It can be modulated between 1 and 215 steps. The step width is 4*tH/864. The output D/A delivers a variable DC signal for general purpose. The picture width and picture height compensation (PW/PH Comp) processes the beam current dependent input signal ABL with effect to the outputs E/W and VD to keep width and height constant and independent of brightness. The alignment parameter Horizontal Shift Compensation enables to adjust the influence of the input signal ABL on the horizontal phase. The selectable start up circuit controls the energy supply of the H-output stage during the receiver's run up time by smooth decreasing the line output transistors switching frequency down to the normal operating value (softstart). HD starts with about double the line frequency and converges within 85 ms to its final value. The high time is kept constant.The normal operating pulse ratio H/L is 45/55. The protection circuit watches an EHT reference and the saw-tooth of the vertical output stage. H-output stage is switched off if the EHT succeeds a defined threshold or if the V-deflection fails (refer to page 46). HPROT: Input
Vi < V2 Vi > V1 V2 Vi < V1
Continuous blanking HD disabled Operating range
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Semiconductor Group
SDA 9361
VPROT:
Vertical saw-tooth voltage Vi < V1 in first half of V-period or Vi > V2 in second half: HD disabled
The pin SCP delivers the composite blanking signal SCP. It contains burst (Vb), Hblanking HBL (VHBL) and selectable V-blanking (control bit SSC). The phase and width of the H-blanking period can be varied by 2C Bus. For the timing following settings are possible: BD = 1 BD = 0, BSE = 0 (default value) BD = 0, BSE = 1(alignment range) : tBL = 0 : tHBL = tf (H-flyback time) : tHBL = (4 * H-blanking-time + 1) / CLL : tDBL = (H-shift + 4 * H-blanking-phase -2 * H-blanking-time + 43) / CLL : tBL = tVBL during V-blanking period : tBL is always tHBL
SSC = 0 SSC = 1
Input Signal HSYNC
t DB t DBL VOH VOHBL VOL t BL
tB
UED10260
Figure 3 BG-pulse width tB Delay to HSYNC tDB 54 / CLL if CLEXT = L-level: (76-4 * Internal-H-sync-phase) / CLL if CLEXT = H-level: (38-4 * Internal-H-sync-phase) / CLL
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SDA 9361
2.2
Circuit Description
The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase locked to the incoming horizontal sync pulse and exactly 864 times faster then the horizontal frequency. In order to lock the internal frequency to the external sync signal positive horizontal sync pulses are required (see figure 4).
tr V HSmax
V HSpp
V HSmin tW
UED10279
Figure 4 Incoming Signal HSYNC (CLEXT = 0) Pulse width tw for 2C-Bus Bit 'HSWID' = 0: 3 s ... 6.1 s 1.5 s ... 3.1 s 3 s ... 8.8 s 1.5 s ... 4.0 s low FH-range high FH-range low FH-range high FH-range
Pulse width tw for 2C-Bus Bit 'HSWID' = 1:
Rise time tr:100 ns minimum (CLEXT = 0) The described input signal is first applied to an A/D converter. Conversion takes place with 6 Bits and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to obtain defined slopes for further measurements (PAL/NTSC applications). In addition the actual high and low level of the signal as well as a threshold value is evaluated and used to calculate the phase error between internal clock and external horizontal sync
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SDA 9361
pulse. By means of digital PI filtering an increment is gained from this. The PI filter can be set by the 2C-Bus VCR bit so that the lock-in behavior of the PLL is optimal in relation to either the TV or VCR mode. Moreover it is possible to adapt the nominal frequency by means of 5 2C-Bus bits (INCR4..INCR0) to different horizontal frequencies. An additional bus bit GENMOD offers the possibility to use the PLL as a frequency generator which frequency is controlled by the INCR bits. Once an increment has been obtained, either from the PI-filter or the 2C Bus, it can be used to operate the Digital Timing Oscillator. The DTO generates a saw-tooth with a frequency that is proportional to the increment. The saw-tooth is converted into a sinusoidal clock signal by means of sin ROM's and D/A converters and applied to an analog PLL which multiplies the frequency by 2 or 4 (depends on mode 1FH or 2FH; for detailed explanation see pinning and 2C-Bus description) and minimizes residual jitter. In this manner the required line locked clock is provided to operate the other functional parts of the circuit. If no HSYNC is applied to pin 35 the system holds its momentary frequency for 2040 lines and following resets the PLL to its nominal frequency. The status bit CON indicates the lock state of the PLL. The system also provides a stable HS-pulse for internal use. The phase between this internal pulse and the external HSYNC is adjustable via 2C-Bus bits HPHASE. It can be shifted over the range of one TV line. An external clock (CLKI) can be provided by pin selection (CLEXT = H). The clock frequency has to be 864 * fHSYNC.The external clock mode can not be used with 33.75 kHz and 35 kHz line frequency. For effective noise suppression the VSYNC has to pass a window at first and is then processed in a flywheel logic. The window allows a VSYNC pulse only after a minimum number of lines from its predecessor and sets an artificial one after a maximum number of lines. The number of H-periods between two subsequent VSYNCs is stored and determines (after several checks) the following V-periods (internal synchronization). If incoincidence is detected between internal and external VSYNC, the system switches after a hysteresis of a defined number of V-periods to external synchronization and the checks are repeated. Values which influence shape and amplitude of the output signals are transmitted as reduced binary values to the SDA 9361 via 2C Bus. A CPU which is designed for speed reasons in a pipe line structure calculates in consideration of feedback signals (e.g.ABL) values which exactly represent the output signals. These values control after D/A conversion the external deflection and raster correction circuits. The CPU firmware is stored in an internal ROM.
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SDA 9361
2.3
Reset Modes
The circuit is completely reset at power-on/off (timing diagram see figure 11) or if the pin RESN has L-level (timing diagram see figure 12). During standby operation some parts of the circuit are not affected (timing diagram see figure 12): Power-On-Reset HD output H-protection V-protection Low Inactive Inactive Tristate External Reset (pin RESN = Low) Low Inactive Inactive Tristate Standby Mode (I2C Bit STDBY = 1) Active Inactive Inactive Ready
2C interface (SDA, SCL) 2C register 01H...1CH, 1FH 2C register 00H, 1DH, 1EH, 44H...48H
Status Bit PONRES
Set to default values Set to default values Set to default values Set to default values Set to default values Not affected Set to 11) Not affected Inactive Set to 11) Not affected Inactive Not affected Inactive Inactive
VREFP, VREFH. VREFL
CPU
1)
Can only be read after Power-On-Reset is finished
Note: Power-On-Reset and RESN = Low state are deactivated after ca. 32 cycles of the X1/X2 oscillator clock and ca. 42 cycles of the CLL clock. Standby state is deactivated after ca. 42 cycles of the CLL clock.
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SDA 9361
2.4 H
Frequency Ranges V 50 Hz 60 Hz 50 Hz 100 Hz 60 Hz 70 Hz 120 Hz 60 Hz 60 Hz 66.7 Hz nL 625 I 525 I 625 NI / 1250I 625 I 525 NI / 1050 I 449 NI 525 I 1080 I 1125 I 525 NI
15.625 kHz 15.75 kHz 31.25 kHz 31.5 kHz
32.4 kHz 33.75 kHz1) 35 kHz1)
1)
Only with internal clock generation
The allowed deviation of all input line frequencies is max. 4.5 %. nL: I: NI: number of lines per frame interlaced non interlaced
If NSA = 0 (subaddress 01H/D5H) number of lines per field is selfadaptable between 192 and 680 for each specified H-frequency.
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SDA 9361
2.5
I2C-Bus Control
2.5.1 I2C-Bus Address 1000110 2.5.2 I2C-Bus Format write: S10001100A read: S10001101A Status byte A Data Byte n A ***** NA P Subaddress A Data Byte A ***** A P
Reading starts at the last write address n. Specification of a subaddress in reading mode is not possible. S: A: P: NA: Start condition Acknowledge Stop condition Not Acknowledge
An automatically address increment function is implemented. After switching on the IC, all bits are set to defined states.
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SDA 9361
2.5.3 I2C-Bus Commands
Subaddr. Control item Deflection control 0 Deflection control 1 Vertical shift Vertical size Vertical linearity Vertical S-correction Vertical EHT compensation 1) Horizontal size Pin phase Pin amp Upper corner pin correction Lower corner pin correction Horizontal EHT compensation 1) Horizontal shift Vertical angle Vertical bow PWM start D/A 1) Vertical blanking time 1) Horizontal blanking time Start vertical scan 1) Horizontal blanking phase Vertical scan width 0 1) Vertical scan width 1 1) Guard band 1) Start reduced scan 1) Vertical sync control Min. No. of lines / field 1) Max. No. of lines / field 1) AFC EHT compensation1) Internal PLL control Internal H-sync phase PWM width Universal register 1 Universal register 3 Internal voltage Ref control
1)
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH
D7 D6 D5 D4 D3 D2 D1 D0 Allowed Effective Can be Default Range Range Disabled Value if by Bit Disabled see below - - - - see below - - - - B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 - - B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 - - B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 - - B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 - - B7 B6 B5 B4 B3 B2 B1 B0 0..255 0..255 - - B7 B7 B7 B7 B6 B6 B6 B6 B5 B5 B5 B5 B4 B4 B4 B4 B3 B3 B3 B3 B2 B2 B2 B2 B1 B1 B1 B1 B0 B0 B0 B0 -128..127 -128..127 -128..127 -128..127 -128..127 -128..127 -128..127 -128..127 - - - - - - - - - - - -
Unit - - - - - - - - - - - - - 1/CLL - - 4/CLL - lines 4/CLL line 4/CLL 256 lines lines half lines line - 2 lines 2 lines - - 4/CLL 4/CLL - - -
0BH B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 0CH B7 B6 B5 B4 B3 B2 B1 B0 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H B6 B7 B7 B7 B5 X X B7 B5 B5 B6 B6 B6 B4 B6 X B6 B4 B4 B5 B5 B5 B3 B5 B5 B5 B3 B3 B4 B4 B4 B2 B4 B4 B4 B2 B2 B3 B3 B3 B1 B3 B3 B3 B1 B1 B2 B2 B2 B0 B2 B2 B2 B0 B0 B1 B1 B1 X B1 B1 B1 X B0 B0 B0 X B0 B0 B0 0..255 -64..63 -128..127 -128..127 0..255 -32..31 0..127 0..63 -128..127 -32..31 0..+3 0..255 0..63 0..63 0..255
-64..63 - - -128..127 - - -128..127 - - 0..215 - - -32..31 - - a) BSE = 0 b) 0..63 BSE = 0 H-flyback c) SSE = 0 9 -32..31 - - d) d) 0..63 0, 2..63 - 0..255 0..255 -32..31 STE = 0 STE = 0 GBE = 0 SRSE = 0 - - - - - - PWM width=0 - - - e) e) 3 2 - - - - - - 15 - - -
15H B9 B8 16H B7 B6 B5 B4 B3 B2 B1 B0 17H X X B5 B4 B3 B2 B1 B0 18H X X B5 B4 B3 B2 B1 B0
see below - 19H 1AH B7 B6 B5 B4 B3 B2 B1 B0 0..255 1BH B7 B6 B5 B4 B3 B2 B1 B0 0..255 1CH B5 B4 B3 B2 B1 B0 X X -32..31
see below - - 1DH 1EH B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -96..119 1FH B7 B6 B5 B4 B3 B2 B1 B0 0..255 0..215 45H 47H 48H see below see below see below - - - - - -
see 2.5.5: Explanation of some control items
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a) The effective range for Vertical Blanking Time: 16 ... 127 (absolute value) if STE = 0 0 ... 127 (offset value) if STE = 1. b) The "default value if disabled" for Vertical Blanking Time: 21 (absolute value)if STE = 0 8 (offset value)if STE = 1. c) The effective range for Start Vertical Scan: 2 ... 127 (absolute value) -128 ... 127 (offset value) if STE = 0 if STE = 1 and NSA = 1 if STE = 1 and NSA = 0.
d) The effective range for Vertical Scan (total width: 10 Bit): 160 ... 684 lines. e) The "default value if disabled" for Vertical Scan equals the number of lines of the source signal reduced by the control value for Start Vertical Scan. (E.g.: input signal: 262 lines per field; Start vertical scan = 8 lines; then (if SSE = 1, STE = 0) vertical scan = 262 - 8 = 254 lines. At power on the RAM containing the control items is cleared. Therefore all data are zero by default (if not otherwise defined) before transferring individual values via 2C Bus. Allowed values out of the effective range are limited, e. g. Vertical blanking time = 3 is limited to 16 if STE = 0 (that means a minimum of 16 lines is blanked). There are five bits (SRSE, BSE, SSE, STE, GBE) in the deflection control byte 1 for disabling some control items. If one of these bits is "0", the value of the corresponding control item will be ignored and replaced by the value "default value if disabled" in the table above. 2.5.4 Detailed Description The Deflection Control Byte 0 includes the following bits: VOFF STDBY 2FH BD RABL VR1 VR0 HDE
VOFF:
Vertical off 0: normal vertical output due to control items 1: vertical saw-tooth is switched off, vertical protection is disabled Default value depends on pin 44 (VOFFD) VOFFD = Low: 0 VOFFD = High: 1
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SDA 9361
STDBY:
Stand-by mode 0: normal operation 1: stand-by mode (all internal clocks are disabled) Setting of line frequency 0: low range of line frequency (14900 Hz ... 17650 Hz) 1: high range of line frequency (29800 Hz ... 35300 Hz)
2FH:
Note: this bit is don't care if pin SELFH1_2 has L-level
BD: Blanking disable 0: horizontal and vertical blanking enabled 1: horizontal and vertical blanking disabled ABL input range 0: 2 V ... 3 V 1: 0 V ... 4 V Reduction of the vertical size 00: 100 % V-size (16:9 source on 16:9 display) 01: 75 % V-size (16:9 source on 4:3 display) 10: 66 % V-size (two 4:3 sources on 16:9 display) 11: 50 % V-size (two 16:9 sources on 16:9 display) HD enable 0: line is switched off (HD disabled, that is L-level) 1: line is switched on (HD enabled) Default value depends on pin 40 (SSD) SSD = Low: 0 SSD = High: 1
RABL:
VR1 ... VR0:
HDE:
The Deflection Control Byte 1 includes the following bits: 0 X NSA STE GBE SRSE SSE BSE
NSA:
No self adaptation 0: self adaptation on 1: self adaptation off
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SDA 9361
STE:
Scan time enable 0: control items for vertical scan width 0 and width 1 are disabled 1: control items for vertical scan width 0 and width 1 are enabled Guard band enable 0: control item for guard band is disabled 1: control item for guard band is enabled Start reduced scan enable 0: control item for start reduced scan is disabled 1: control item for start reduced scan is enabled Start scan enable 0: control item for start vertical scan is disabled 1: control item for start vertical scan is enabled Blanking select enable 0: control items for blanking times are disabled 1: control items for blanking times are enabled
GBE:
SRSE:
SSE:
BSE:
The Vertical Sync Control Byte includes the following bits: X X SSC NR NI NL2 NL1 NL0
SSC:
Sandcastle without VBL 0: output SCP with VBL component 1: output SCP without VBL component Noise reduction 0: no noise reduction of the vertical sync 1: noise reduction of the vertical sync Non interlace 0: interlace depends on source 1: no interlace
NR:
NI:
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SDA 9361
NL2 ... NL0:
Number of lines per field when NR = 1 and no vertical sync at the input is detected
NL2 0 0 0 0 1
NL1 0 0 1 1 X
NL0 0 1 0 1 X
Number of Lines per Field 262.5 312.5 525 562.5 625
The Internal PLL Control Byte includes the following bits: HSWID GENMOD VCR INCR4 INCR3 INCR2 INCR1 INCR0
HSWID:
Maximum width of HSYNC 0: 6.1 s for low FH-range 3.1 s for high FH-range 1: 8.8 s for low FH-range 4.0 s for high FH-range Clock generator mode 0: normal PLL mode 1: generator mode (fixed frequency output, controlled by INCR..) PLL filter optimized for 0: TV mode 1: VCR mode Nominal PLL output frequency for low FH-range: INCR = INT((FH * 110592) / FQ - 64.625) for high FH-range: INCR = INT((FH * 55296) / FQ - 64.625) (for typical values see table below)
GENMOD:
VCR:
INCR4 ... 0:
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specified range for: GENMOD = 0: 6 GENMOD = 1: 3 (FQ = 24.576 MHz)
INCR 14 INCR 18
Application PAL NTSC PAL (100 Hz) NTSC (120 Hz) ATV MUSE Macintosh Default value: INCR = 6
FH[Hz] 15625 15750 31250 31500 32400 33750 35000
INCR 6 6 6 6 8 11 14
Warning: 1)A change of INCR or 2FH causes spontaneous changes of the generated clock frequency greater than the specified 4.5 %. Switching from PLL mode to Generator mode (GENMOD) with constant INCR values does not result in exceeding the specified frequency deviation range. 2)If pin SSD has H-level the output signal HD starts immediately after power on. In this case the starting horizontal frequency is either 15.75 kHz (if SELFH1_2 has H-level or if SELFH1_2 and FH1_2 have L-level) or 31.5 kHz (if SELFH1_2 has L-level and FH1_2 H-level). Starting with Muse or Macintosh standard requires L-level at SSD so that INCR can be changed before enabling HD with HDE = 1. 3)Using external clock at pin 1, CLKI, (pin 32, CLEXT = 1): no internal protection against missing clock pulses is provided. 4)In order to guarantee error free operation of the build in soft start circuit the input frequency has to be inside the lock range of the PLL (+/-4.5 % of standard input frequency)
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SDA 9361
The Universal Register 1 (Subaddress 45H) includes the following bit: 0 0 NOISY VCR 0 0 0 0 0
NOISYVCR:
Handling of noisy input signals in VCR mode 0: normal handling 1: improved handling Note: this bit is don't care if bit VCR = 0 (TV mode)
The Universal Register 3 (Subaddress 47H) includes the following bits: 0 0 0 KILL_ZIP TC_3RD 0 0 0
KILL_ZIP:
Top flutter suppression 0: no top flutter suppression 1: top flutter suppression (phase jumps max. 12 s for low FH-range rsp. max. 6 s for high FH-range) Third time constant 0: slow VCR time constant 1: fast VCR time constant
TC_3RD:
Note: this bit is don't care if bit VCR = 0 (TV mode)
The Internal Voltage Ref. Control Byte includes the following bits: BANDG4 BANDG3 BANDG2 BANDG1 BANDG0 BANDG BANDG4 OFF OFF 0
BANDG4 ... BANDG0:
Adjustment of internal bandgap reference 10000: Reference Output voltage min : 01111: Reference Output voltage max Typical adjustment range is 0.5 V.
BANDGOFF: Bandgap Off 0: VREFH, VREFL derived internally from VREFP
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SDA 9361
1:
external references on VREFP, VREFH, VREFL have to be applied (in this case BANDG4OFF must be = 1)
BANDG4OFF: Bandgap 4 V Off 0: internal bandgap reference is used for VREFP 1: external reference on VREFP (4 V) has to be applied The Status Byte includes the following bits: HPON VPON CON PONRES
HPON:
protection on 0: normal operation of the line output stage 1: high level on input HPROT has switched off the line V-protection on 0: normal operation of the vertical output stage 1: incorrect signal on input VPROT has switched off the line Coincidence not 0: H-coincidence detected 1: no H-coincidence detected Power-On-Reset 0: after bus master has read the status byte 1: after each detected reset
VPON:
CON:
PONRES:
Note: PONRES is reset after this byte has been read.
2.5.5 Explanation of Some Control Items D/A This item controls directly a 6 Bit D/A Converter at the output D/A that can be used for general purpose. Start Vertical Scan If enabled (SSE = 1) this control item defines the start of calculation of the vertical sawtooth, the east/west parabola and the vertical function required for the vertical modulated output HD.
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SDA 9361
Vertical Scan (width0 and width1) The total width of this control item is 10 Bit. Therefore two registers (width0 and width1) are necessary. If enabled (STE = 1) it defines the duration of the vertical scan. When the vertical period has more lines than the sum of Start Vertical Scan and Vertical Scan, the calculation of the vertical saw-tooth, the east/west parabola and the vertical parabola required for HD stops so that the corresponding output signals remain unchanged till the next vertical synchron pulse. Guard Band This control item is useful for optimizing self adaptation. Video signals with different number of lines in consecutive fields (e. g. VCR search mode) must not start the procedure of self adaptation. But switching between different TV standards has to change the slope of the vertical saw-tooth getting always the same amplitude (self adaptation). To avoid problems with flicker free TV systems which have alternating number of lines per field an average value of four consecutive fields is calculated. If the deviation of these average values (e.g. PAL: 312.5 lines or 625 half lines) is less or equals Guard Band, no adaptation takes place. When it exceeds Guard Band, the vertical slope will be changed. Start Reduced Scan If enabled (SRSE = 1) this item defines the start of the D/A conversion of the calculated vertical saw-tooth. From begin of the vertical flyback to the line defined by Start Reduced Scan the output signals VD+, VD- remain unchanged (flyback level). Other outputs are not affected. a) control bits VR1, VR0 # 00 (reduction of vertical size) In this case the byte is useful for e.g. displaying 16/9 source format on 4/3 picture tubes without visible RGB lines generated of the automatic cut-off control (partial overscan). It defines the start of the reduced amplitude (factors 0.5, 0.66, 0.75) of the vertical saw-tooth (refer page 39). When Start Reduced Scan = 0 the reduction takes place over all lines including vertical flyback. b) control bits VR1, VR0 = 00 (no reduction of vertical size) If Start Reduced Scan > Start Vertical Scan the D/A conversion of the saw-tooth starts (Start Reduced Scan - Start Vertical Scan) lines after begin of the calculation. This causes a jump of the output voltage VD+, VD- from flyback to scan level. It may be useful to hide the automatic cut-off control lines if no overscan is desired (e.g. for VGA display). If Start Reduced Scan <= Start Vertical Scan this byte has no effect.
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SDA 9361
Vertical EHT Compensation This item controls the influence of the beam current dependent input signal ABL on the outputs VD+ and VD- according to the following equation: Vertical EHT compensation 1) V VDPP = V ABL * ----------------------------------------------------------------------- * 0,57 512 Vertical EHT compensation 1) V VDPP = V ABL * ----------------------------------------------------------------------- * 0,57 2048 (if RABL = 0)
(if RABL = 1)
VVDPP: variation of VD+ and VD- peak-to-peak voltage VABL: variation of ABL input voltage
1)
The factor 0.57 depends on VREFP, VREFH, VREFL
If Vertical EHT Compensation = 0 the outputs VD+ and VD- are independent of the input signal ABL. Horizontal EHT Compensation This item controls the influence of the input signal ABL on the output E/W according to the following equation: Horizontal EHT compensation 1) V EW = V ABL * ---------------------------------------------------------------------------------- * 2,12 128 Horizontal EHT compensation 1) V EW = V ABL * ---------------------------------------------------------------------------------- * 2,12 512 (if RABL = 0)
(if RABL = 1)
VEW: variation of E/W output voltage VABL: variation of ABL input voltage
1) The factor 2.12 depends on
VREFP, VREFH, VREFL
If Horizontal EHT Compensation = 0 the output E/W is independent of the input signal ABL. AFC EHT Compensation Deviation of the horizontal phase caused by high beam current (e.g. white bar) can be eliminated by this control item. The beam current dependent input signal ABL is multiplied by AFC EHT Compensation.
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SDA 9361
Additional to the control items Vertical angle, Vertical bow and Horizontal shift, this product influences the horizontal phase at the output HD according to the following equation: AFC EHT compensation 52 = V ABL * --------------------------------------------------------------- * ---------CLL 64 AFC EHT compensation 52 = V ABL * --------------------------------------------------------------- * ---------CLL 256
1) 1)
(if RABL = 0)
(if RABL = 1)
VABL CLL
1)
:variation of horizontal phase at the output HD (positive values: shift left, negatives values: shift right) :variation of ABL input voltage (units: Volt) :864 * FH
The factor 52 depends on VREFP
Vertical Blanking Time (VBT) VBT defines the vertical blanking pulse VBL which is part of the output signal SCP. VBL is synchronized with the leading edge of HSYNC. It always starts and stops at the beginning of line and never in the center. a) Case of STE = 0 In this case the control item Vertical blanking time defines the duration of the V-blanking pulse (VBL) exactly in number of lines. Because of IC internal limitations 16 through 127 lines can be blanked. If BSE = 0 the control item Vertical blanking time is disabled and always 21 lines (default value if disabled) are blanked. After power on the control bit BSE is 0. Therefore 21 lines will be blanked before any programming of the IC. If Vertical Blanking Time is less or equals 21 lines, VBL starts (point A in fig. above) always 0 ... 0.5 line (new odd field) or 0.5 ... 1 line (new even field) prior to the vertical flyback. Otherwise VBL is concentric to a fictitious vertical flyback period of 21 lines, that means VBL starts (VBT - 21) / 2 lines at the end of an odd field or (VBT - 20) / 2 at the end of an even field prior to point A. Possible start points are only the beginning of line.
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SDA 9361
HSYNC
1
2
14
15
16
17
18
19
20
21
22
23
24
25
~ ~
VSYNC 1 Line
Start of odd Field VD-
Start of even Field
~ ~ ~ ~
~ ~
VBL (BSE = 0) VBL (BSE = 1, VBT = 16) 2 Lines VBL (BSE = 1, VBT = 25) 3 Lines VBL (BSE = 1, VBT = 26) A
21 Lines
~ ~
16 Lines
~ ~
2 Lines
25 Lines
~ ~
26 Lines
UED10261
Figure 5 Vertical Blanking Pulse VBL when STE = 0 and Number of Lines per
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SDA 9361
Field = Constant b) Case of STE = 1 In this case the control item Vertical blanking time is an extension for the V-blanking pulse. - If BSE = 1 and VBT = 0 the V-blanking pulse has its minimum: it starts always at end of scan (line B in Fig. below) and ends at start of scan (line C) defined by the control items Start Vertical Scan (if SSE = 1) and Vertical Scan. - BSE = 1 and (128 > VBT > 0) extend the V-blanking pulse according to the following relationship (If VBT > 127 this value is ignored and replaced by VBT - 128): VBL starts VBT / 2 lines (even field) respectively (VBT + 1) / 2 lines (odd field) prior to line B. VBL ends (VBT + 1) / 2 lines (even field) respectively VBT / 2 lines (odd field) after end of line C. Possible start points are only the beginning of line. - If BSE = 0 (after power on) the control item Vertical Blanking Time is disabled and VBL starts 4 lines prior to end of scan (line B) and ends 4 lines after start of scan (line C).
HSYNC
B
1
2
3
C
~ ~
~ ~
VSYNC
Start of odd Field VD4 Lines
~ ~ ~ ~
~ ~
1 Line
Start of even Field
~ ~
Even 4 Lines
~ ~
VBL (BSE = 0) VBL (BSE = 1, VBT = 0) 3 Lines VBL (BSE = 1, VBT = 7) B
~ ~
Figure 6 Vertical Blanking Pulse VBL when STE = 1
Semiconductor Group 29 1998-02-01
~ ~ ~ ~
3 Lines
~ ~
C
UED10262
SDA 9361
Minimum Number of Lines per Field It defines the minimum number of lines per field for the vertical synchronisation. If the TV standard at the inputs VSYNC and HSYNC has less lines per field than defined by Minimum Number of Lines per Field no synchronisation is possible.The relationship between Minimum Number of Lines per Field and the minimum number of lines is given in the following table: Minimum Number of Lines per Field 0 1 ... 127 128 ... 254 255 Minimum Number of Lines per Field 192 194 ... 446 448 ... 700 702
Maximum Number of Lines per Field It defines the maximum number of lines per field for the vertical synchronisation. If the TV standard at the inputs VSYNC and HSYNC has more lines per field than defined by Maximum Number of Lines per Field no synchronisation is possible. The relationship between Maximum Number of Lines per Field and the maximum number of lines is given in the following table: Maximum Number of Lines per Field 0 1 2 ... 127 128 ... 255 Maximum Number of Lines per Field 702 192 194 ... 444 446 ... 700
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SDA 9361
Most Important V-Deflection Modes for 4:3 CRT
Mode Description Characteristics Self adaptation scan start = line 9 start of V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines Notes Mode after power on VR1 NSA SRSE GBE STE SSE VR0 00 0 0 0 0 0
N0 Normal mode (for 4:3 source, Letterbox) with default settings N1 Normal mode (for 4:3 source, Letterbox) with user defined values
Start of scan Self adaptation adjustable scan start = Start Vertical Scan if (Start Reduced Scan>Start Vertical Scan) start of start of V-ramp = Start Reduced Scan V-ramp adjustable else guard band start of V-ramp = Start Vertical Scan adjustable scan time: depends on source signal guard band = Guard Band/2 [lines] Self adaptation scan start = line 9 start of reduced V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines
00
0
1
1
0
1
S0 Shrink mode 75% (for 16:9 source) with default settings
01
0
0
0
0
0
Start of scan Self adaptation S1 Shrink adjustable scan start = Start Vertical Scan mode 75% (for 16:9 source) if (Start Reduced Scan>Start Vertical Scan) start of reduced start of reduced V-ramp = with user V-ramp Start Reduced Scan defined values adjustable else guard band start of reduced V-ramp = adjustable Start Vertical Scan scan time: depends on source signal guard band = Guard Band/2 [lines]
01
0
1
1
0
1
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SDA 9361
Most Important V-Deflection Modes for 16:9 CRT
Mode Description Characteristics Self adaptation scan start = line 9 start of V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines Notes Mode after power on VR1 NSA SRSE GBE STE SSE VR0 00 0 0 0 0 0
N0 Normal mode (for 16:9 or 4:3 source) with default settings N1 Normal mode (for 16:9 or 4:3 source) with user defined values
Start of scan 00 Self adaptation adjustable scan start = Start Vertical Scan if (Start Reduced Scan>Start Vertical Scan) start of start of V-ramp = Start Reduced Scan V-ramp adjustable else guard band start of V-ramp = Start Vertical Scan adjustable scan time: depends on source signal guard band = Guard Band/2 [lines]
0
1
1
0
1
Z
00 Zoom mode scan start = Vertical (for 4:3 source, (number_of_lines - Vertical Scan)/2 + 8 scan Letterbox) scan time = Vertical Scan controls zoom factor Like above; 00 Start vertical scan can be additionally used for adjustment of picture phase Scan start and scan time are separately adjustable 00
0
X
X
1
0
Scan start = SC Scroll mode (number_of_lines - Vertical Scan)/2 + 8 (for 4:3 source, + Start Vertical Scan Letterbox) scan time = Vertical Scan
0
X
X
1
1
M
Manual mode Scan start = Start Vertical Scan (for 4:3 source, scan time = Vertical Scan Letterbox)
1
X
X
1
X
S2 Shrink mode 66% (for two 4:3 sources) with default settings S3 Shrink mode 50% (for two 16:9 sources) with default settings
Self adaptation scan start = line 9 start of reduced V-ramp = line 9 scan time: depends on source signal guard band =1.5 lines Self adaptation scan start = line 9 start of reduced V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines
10
0
0
0
0
0
11
0
0
0
0
0
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3
Absolute Maximum Ratings Symbol min. Limit Values max. 70 125 125 260 C C C C -20 -40 Unit Remark
Parameter Operating temperature Storage temperature Junction temperature Soldering temperature Input voltage Output voltage Supply voltages Supply total voltage differentials Total power dissipation Latch-up protection
1)
TA Tstg Tj TS VI VQ VDD
VSS - 0.3 V VDD + 0.3 V VSS - 0.3 V VDD + 0.3 V
-0.3 -0.25 6 0.25 0.85 -100 100 V V W mA All inputs/outputs
1)
Ptot
Between any internally non-connected supply pin of the same kind. All VDD(D) - and VDD(A) - Pins are connected internally by about 3 The VSS(D)-Pins are connected internally by about 3
Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied.
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3.1
Recommended Operating Conditions Symbol min. 4.5 -20 Limit Values nom. 5 25 max. 5.5 70 V C For analog parameters: 0C Unit Remark
Parameter Supply voltages
VDD Ambient temperature TA
TTL Inputs: CLKI, VSYNC, TEST, FH1_2, SELFH1_2, CLEXT, SSD, VOFFD, RESN H-input voltage L-input voltage Input VPROT Threshold V1 Threshold V2 Input HPROT Threshold V1 Threshold V2 Input ABL L-input voltage 3.9 2.1 4 2.4 2 0 Full range input voltage 3 4 4.1 2.7 V V V V V V V V V V V Independent of register 48H, max = VDD 1.4 0.9 1.5 1.0 1.6 1.1 V V
VIH VIL
2.0 0
VDD
0.8
V V
VREFP = 4 V VREFP = 4 V VREFP = 4 V VREFP = 4 V VREFP = 4 V
RABL = 0
VIL
VREFP = 4 V RABL = 1 VREFP = 4 V
RABL = 0
VREFP = 4 V RABL = 1
Reference Voltage Input Pins (Internal Voltage Ref. Control Byte Reg 48H = 00000110)
VREFP input voltage VREFH input voltage VREFL input voltage VREFN input voltage VREFC input voltage
VVREFP VVREFH VVREFL VVREFN VVREFC
4 2.5 1.2 0 5
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3.1
Recommended Operating Conditions (cont'd) Symbol min. Limit Values nom. max. 0.7 V V V V Unit Remark
Parameter Input 2 L-input voltage H-input voltage Input voltage range
VIL VIH
0 2.0 2 0
VDD VDD VDD
VREFP = 4 V VREFP = 4 V
See page 12 See page 12 See page 12 Low FH-range High FH-range Low FH-range High FH-range
Input HSYNC (CLEXT = 0)
VHSpp Input voltage low level VHSmin Input voltage high level VHSmax Pulse width tw
(HSWID = 0)
3.0 1.5
6.1 3.1 8.8 4.0
s s s
s ns
Pulse width (HSWID = 1) Rise time L-input voltage H-input voltage Setup time Hold time Input VSYNC Pulse width high Pulse width high Pulse width high
tw
3.0 1.5
tr VIL VIH tSU tH
100 0 2.0 4 12 0.8
Input HSYNC (CLEXT = 1) V V ns ns Referred to falling edge of CLKI Referred to falling edge of CLKI FH1_2 = 1, NI = 0 FH1_2 = 0, NI = 0 NI = 1
VDD
100 200 1.5/fH
100/fH ns 100/fH ns 100/fH
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3.1
Recommended Operating Conditions (cont'd) Symbol min. Limit Values nom. 13.5 27 24.576 max. 15 30 MHz MHz MHz Low FH-range High FH-range Fundamental crystal type, e.g. Saronix 9922 520 00282 Unit Remark
Parameter
Input CLKI (External Clock Generation, CLEXT = High) Input frequency
fI
12.5 25
Quartz Oscillator Input / Output X1, X2 Crystal frequency
Crystal resonant impedance External capacitance 27
40
pF See Application information
I2C Bus (All Values are Referred to min.(VIH) and max.(VIL) High-level input voltage Low-level input voltage Rise times of SCLK, SDAT Fall times of SCLK, SDAT Set-up time DATA Hold time DATA Load capacitance
VIH VIL
3 0 0
VDD
1.5 400 0.3 0.3
V V kHz
SCLK clock frequency fSCLK
tR tF tSU;DAT tHD;DAT CL
100 0
s s
ns ns
fSCLK = 400 kHz
400
pF
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3.2
Characteristics (Assuming Recommended Operating Conditions) Symbol min. Limit Values nom. 90 max. 150 25 mA mA Unit Remark
Parameter Average supply current Stand-by supply current
ICC
Output Pins: SCAN, PWM Output low level Output high level Input / Output SDAT Output low level Output SCP Output low level Output HBL level Output high level DAC Output D/A DAC resolution DAC output low DAC output high Load capacitance Output load Offset error Gain error INL DNL DAC Output E/W DAC resolution DAC output low 10 1.45 Bit V Linear range: 100 ... 900 Input data = 1001) 6 1 3.953 Bit V V 30 20 -3 % -3 % -1 -0.5 3% 3% 1 0.5 LSB LSB pF k
VOL VOH VOL VOL VOHBL VOH
0.4 2.8 0.6 0 -0.4 V 4.0 1 +0.4 V
V V V V
IO = 1 mA IO = -1 mA IO = 6 mA IO = 1 mA | IO | = 100 A IO = -1 mA
VDD / 2 VDD / 2 VDD / 2 VDD
V
VREFP = 4 V VREFP = 4 V
CL
VREFP = 4 V VREFP = 4 V
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3.2
Characteristics (Assuming Recommended Operating Conditions) (cont'd) Symbol min. Limit Values nom. 3.48 max. V 30 20 -2 % -5 % -0.2 % -0.1 % 2% 5% 0.2 % 0.1 % pF k DAC output voltage = 2.5 V2)
2) 2) 2)
Parameter DAC output high Load capacitance Output load Zero error Gain error INL DNL
1) 2)
Unit
Remark Input data = 9001)
CL
VREFH = 2.5 V, VREFL = 1.2 V VREFH = 2.5 V, VREFL = 1.2 V, Input range = 100 ... 900
DAC Output VD+, VDDAC resolution DAC output low (VD-) DAC output high (VD-) DAC output low (VD-) - (VD+) DAC output high (VD-) - (VD+) Load capacitance Output load Zero error Gain error INL DNL
1) 2)
14 1.44 3.58 -2.12 2.16
Bit V V V V 30 pF k 1% 5% 0.5 %
Linear range: 1500 ... 15000 Input data = 15001) Input data = 150001) Input data = 15001) Input data = 150001)
CL
20 -1 % -5 % -0.5 % Monotonous
(VD-) - (VD+) = 0 V2)
2) 2)
Guaranteed by design
VREFH = 2.5 V, VREFL = 1.2 V VREFH = 2.5 V, VREFL = 1.2 V, Input range = 1500 ... 15000
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3.2
Characteristics (Assuming Recommended Operating Conditions) (cont'd) Symbol min. Limit Values nom. max. Unit Remark
Parameter
Reference Output VREFP (Adjustable by Reg 48H, Bit D7 ... D3) (Reg 48H, Bit D2 = 0, Bit D1 = 0) Output voltage min Output voltage max Output current Output voltage Output voltage Output HD Output low level Output high level 4.0 4.0 V V 0 2.5 1.2 2.6 1.3 1 Bit D7 ... D3 = 10000 Bit D7 ... D3 = 01111
IQ VQ VQ VOL VOH
-50 2.4 1.1 0
A
V V V
Reference Output VREFH (Reg 48H, Bit D2 = 0)
VREFP = 4 V VREFP = 4 V IO = 8 mA IO = -8 mA
Reference Output VREFL (Reg 48H, Bit D2 = 0)
VDD
-1 V
VDD
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4
Application Information
VB
SCP SCAN VPROT HPROT 2
EHT
ABL
TV Contr.
2C +
NVM 27 pF X1 24.576 MHz X2 27 pF VSYNC Source Sel Synch Sep HSYNC VD+
HD
H-Coil
SDA 9361
E/W
+
VD+
VPROT
RESN
PWM
D/A
ABL
Figure 7
Semiconductor Group 40 1998-02-01
_
LF
V-Coil
UES10280
SDA 9361
5 5.1
Waveforms VD- Output Voltage, 4/3-CRT and 16/9-Source
VVDV0(max)
1 V 16/9 2V
1 V 4/3 = 1 VV 16/9 2 0.75 2V
V0(min)
0 SRSE = 1
2 SRS
63
n z (Line No.)
Start Reduced Scan (SRS) selectable (line 0, 2...63)
UED10264
Figure 8
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SDA 9361
5.2
Timing Diagram of SCAN
HSYNC (odd field) HSYNC (even field) 2 * FH (internal)
1
2
3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
~ ~
1
2
3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
~ ~ ~ ~
d0 VSYNC
~ ~
21 Lines
~ ~
VBL (BSE = 0) 1 Line VD(SSE = 0)
appr. 1 Line + d0
Start of Scan appr. 8.5 Lines
~ ~ ~ ~
SCAN (SSE = 0) appr. 0.5 Lines VD(SSE = 1, start vert. scan = 12) SCAN (SSE = 1, start vert. scan = 12)
Start of Scan
~ ~
appr. 11.5 Lines
~ ~
UED10281
Figure 9 Timing Diagram of SCAN if STE = 0
Semiconductor Group 42 1998-02-01
SDA 9361
HSYNC (odd field) HSYNC (even field) 2 * FH (internal)
1
2
3
~ ~ ~ ~ ~ ~
~ ~
1
2
3
~ ~ ~ ~
d0 VSYNC
~ ~
End of Scan
~ ~
~ ~
1 Line
VDStart of Scan
~ ~
~ ~
~ ~
VBL (BSE = 0) 4 Lines SCAN
appr. 1 Line + d0 appr. 0.5 Line + d0
~ ~ ~ ~
UED10282
5.5 Lines
Figure 10 Timing Diagram of SCAN if STE = 1
Semiconductor Group 43 1998-02-01
SDA 9361
5.3
Power On/Off Diagram
Supply Voltage PowerOnReset 32 Cycles X1, X2 SSD = 0: ~ 250 s1) SSD = 1: ~ 380 s1) HD 2 C Registers 01 H ...1C H , 1F H Programmable 2 C Bus Tristate Ready
Tristate
32 Cycles
SSD = 0: ~ 250 s1) SSD = 1: ~ 380 s1) 2 C Registers 01 H ...1C H ,1F H Programmable Ready Tristate
VREFP , VREFH, VREFL
Protection 2 C Reg. 00 H, 1D H, 1E H, 44 H ... 48 H 2 C Reg. 01H ...1C H , 1F H CLL ~ 42 Cycles CPU Active Inactive ~ 42 Cycles Active Inactive
Default Default Default
Programmable
Programmable
Default
Programmable
Default
Programmable
Default
Power On
1)
Glitch
Power Off
UED10283
For low FH-range this time has to be multiplied by 2
Figure 11
Semiconductor Group 44 1998-02-01
SDA 9361
5.4
Standby Mode, RESN Diagram
Standby
RESN SSD = 0: ~ 250 s1) SSD = 1: ~ 380 s1)
Free Run
HD
2-Loop
Free Run
2-Loop ~ 42 CLL Cycles
32 x 1 Cycles
~ 42 CLL Cycles
Active CPU Inactive Active Inactive Active Inactive
VREFP , VREFH, VREFL
Protection
2 C Bus 2 C Reg. Programmable 01H ...1C H , 1F H 2 C Reg. 00 H, 1D H, 1E H 44 H ... 48 H
Ready
Tristate
Ready
Default Values
Programmable
Default Values
Programmable
Programmable
Default Values
Programmable
Standby Mode
1)
External Reset
UED10284
For low FH-range this time has to be multiplied by 2
Figure 12
Semiconductor Group 45 1998-02-01
SDA 9361
5.5
Function of H,V Protection HPROT VPROT Mode SCP HPON2) I2C Bus VPON2) I2C Bus
1
V1 V2
Start up
Continuous blanking
0
0
2
or
V1 V2
H, V operation
1)
0
0
3
EHT overvoltage
Continuous blanking after t2
1 after t2
0
4
or
or
_ t0 < t < t1
Continuous H operation blanking V short after t0 if failure SSC = 0
0
0
5
or
or
t V longer failure H off after t1
Continuous blanking after t0 if SSC = 0
0
1 after t1
6
or
EHT short overvoltage
Continuous blanking after t2
1 after t2
1 after t1
t t0 = 2 / fv ... 3 / fv
2)
t1 = 64 / fv ... 128 / fv
t2 = 1 / fv ... 2 / fv
1) Depends on 2C-control items
HPON or VPON = 1:HD = 0 (OFF)
Semiconductor Group
46
1998-02-01
SDA 9361
6
Package Outlines
P-MQFP-44-2 (Plastic Metric Quad Flat Package)
2.45 max.
0.25 min.
0.8 0.3 +0.15 8 13.2 10
1)
0.88 0.15 C 0.1 0.2 M A-B D C 44x 0.2 A-B D 44x 0.2 A-B D H 4x D
A
B 13.2 10 1)
44 1 Index Marking
1)
0.6 x 45
GPM05622
Does not include plastic or metal protrusions of 0.25 max per side
Figure 13
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information".
SMD = Surface Mounted Device Semiconductor Group 47 Dimensions in mm 1998-02-01
7 max.
H
0.15 +0.08 -0.02
2 +0.1 -0.05

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