View AND8079_158740.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

AND8079/D A Low Cost DDR Memory Power Supply Using the NCP1571 Synchronous Buck Converter and a LM358 Based Linear Voltage Regulator
Prepared by: Jim Lepkowski Senior Application Engineer
http://onsemi.com
APPLICATION NOTE
INTRODUCTION This application note describes a low cost power supply circuit for a DDR (Double Data Rate) memory system. The design is based on the NCP1570/NCP1571 low voltage synchronous buck converter. The reference design created to evaluate the system uses a 3.80 by 2.15 two layer printed circuit board, optimized for a small solution size at an economical cost. DDR memories bring new challenges to the power supply by requiring an efficient main power of 2.5 V (Vdd) and a second voltage (Vtt) that accurately tracks one half of Vdd (i.e. 1.25 V) that is capable of both sourcing and sinking current. In addition, a third voltage is required (VREF) that also tracks Vdd/2. A low voltage synchronous buck converter is used to create an 8.0 A output at 2.5 V, while the Vtt and VREF voltages are created using a unique operational amplifier linear regulator circuit. The demonstration circuit is designed for low power DDR systems such as desktop PCs, but the circuit's output power capability can be increased with the selection of the external inductor and capacitors for high power systems such as PC workstations. DDR Memory Power Supply Requirements Figure 1 shows a simplified schematic of the DDR memory system. Voltage Vdd powers the memory ICs, in addition to the buffer interface circuits. The termination voltage Vtt is used for the pull-up resistors and must be able to either sink or source current. For example, if all of the driver circuits are at a logic high state (i.e. VOH = Vdd = 2.5 V), the Vtt supply will have to sink current in order to maintain its 1.25 V. In contrast, if all of the driver circuits are at a logic low state (i.e. VOL = Vss = 0 V), the Vtt supply will have to source current because the termination resistors will be effectively connected to ground.
Vdd
Vtt = Vdd/2 RT 25 Receiver
RS Transmitter 22
VREF
Figure 1. DDR Memory Simplified Schematic
Vtt is equal to Vdd/2 instead of Vdd in order to save power. The power dissipated in the resistors is equal to voltage squared divided by the bus resistance, thus a termination voltage of Vdd/2 provides a factor of four power savings. The third voltage is used as a reference voltage to the differential amplifier input section of the receiver ICs. A summary of the specifications for the DDR memory system is listed below. The transient requirements are not defined in the industry JEDEC standards.
DDR Voltage Vdd Vtt Output Voltage 2.5 V Vdd/2 (^1.25 V) Vdd/2
Tolerance "200 mV Vdd/2 " 3% (1.250 V " 37.5 mV) Vtt " 40 mV
Output Current 8.0 A "2.0 A (Sink and Source) 5.0 mA
VREF
(c) Semiconductor Components Industries, LLC, 2002
1
October, 2002 - Rev. 1
Publication Order Number: AND8079/D
AND8079/D
Many industry experts have predicted that DDR memory will soon become the standard for desktop computers, with notebooks shortly behind. Next generation DDR-II generation systems are likely to have a lower Vdd voltage of 1.8 V with a Vtt and VREF voltage equal to 900 mV. This lower voltage will be required to satisfy the consumer's requirement for more memory without a large increase in required power. Supply Voltage (Vdd) The Vdd 2.5 V power supply is created with the NCP1571 low voltage synchronous buck controller. The NCP1571 controller contains the required circuitry for a synchronous N-channel MOSFET buck regulator. The V2t control method is used to achieve a fast 200 ns transient response and an output regulation of 1.0%. The IC operates at a fixed internal frequency of 200 kHz. In addition, the NCP1571 provides the following features: undervoltage lockout protection, programmable soft start, power good signal with delay and overvoltage protection. Note the NCP1570 and NCP1571 are functionally and pin for pin equivalent. The NCP1571's under voltage lockout operation (UVLO) feature has been modified for applications that require a parallel standby power supply in addition to the main power supplied by the buck converter. Termination Supply Voltage (Vtt) and Reference Voltage (VREF) The Vtt supply voltage is equal to one half of the Vdd voltage, or approximately 1.25 V. Operational amplifiers U2A and U2B function as voltage followers to create the Vtt voltage. The input to U2B is created by the resistive voltage divider formed by R5 and R6 and divides the 2.5 V Vdd supply by two to form the VREF reference voltage. Also, U2B provides filtering to remove any of the high frequency switching noise that is results from the synchronous buck converter. The Vtt output of the circuit formed by U2A and transistors Q4 and Q5 tracks the voltage at the non-inverting terminal by virtue of the voltage follower circuit configuration. Thus, the output of voltage of the Vtt supply is referenced to 50% of the 2.5 V Vdd supply, rather than an absolute 1.25 V reference. The sink and source ability of the Vtt supply is provided by MOSFETs Q4 and Q5 which are used to extend the current capability of the operational amplifier circuit. When the Vtt supply is in the current sinking mode of operation, Q4 is "OFF" and Q5 is "ON". The output of U2A will be at a negative voltage (i.e. -5.0 V) to control the Vgs of the P-channel MOSFET (Q5) in order to maintain the Vtt voltage of 1.25 V. In a similar manner, when the Vtt supply is in the current sourcing mode of operation, Q4 is "ON" and Q5 is "OFF". The output of U2A will reach a positive voltage (i.e. + 4.5 V) to control the Vgs of the N-channel MOSFET (Q5) in order to maintain the Vtt voltage of 1.25 V. Resistor R7 is used to isolate the output of U2B from Vtt and the bulk capacitor C20. The slew rate of the operational amplifier and the ability of the bulk capacitors to hold the voltage at 1.25 V under the load conditions control the transient response of the Vtt control loop. Note that the bulk capacitors maintain the Vtt voltage at approximately 1.25 V; therefore, the operational amplifier is only required to slew its output a relatively small amount; therefore, the relatively slow slew rate of the LM358 operational amplifiers is not a limiting factor in the design. Standby Power Operation The demonstration PCB has the provision of providing a low power standby mode of operation to the DDR memory system. This mode could be used to provide a 2.5 V low current standby voltage to the memory ICs when the main 5.0 V input power is not available. A MC33375 (U3) 300 mA low dropout voltage regulator (LDO) was chosen for the design to provide the 2.5 V standby power. The MC33375 has an ON/OFF enable pin and is available in a SOT-223 package. The performance of the standby regulator was not verified. Q1, a N-Channel MOSFET, serves as a diode to prevent current flow back to the main 5.0 volt input power supply during the standby mode. The MOSFET was chosen instead of a Schottky diode in order to minimize the voltage drop and power consumption of the diode.
http://onsemi.com
2
Q1 MTB1306 D2 PAK L1 TP5 5 V_Input C1 1800mF 10V C2 1800mF 10V C3 1800mF 10V C4 0.1mF C5 1800mF 10V Prov. 1mH Q2 MTB1306 D2 PAK L2 2.2mH D1 MBRM110LT PowerMite Prov. Q3 R1 10 1 TP8 V_Logic C12 0.1mF R2 47k C13 0.01mF 2 3 4 PWRGD PGDELAY COMP C14 0.1mF MC33375ST-2.5T3 SOT-223 U3 Prov. TP9 V_5P0_STBV 1 VIN 2 C24 1mF ON OFF VOUT 3 GND 4 U2A LM358 Micro8 4 2 3 NCP1571 SO-8 8 GND Vfb GATE(L) GATE(H) 7 6 5 C6 100pF C16 VTT (+1.25V, 2A) TP2 1.25V_Vtt Q4 NTD4302 D2 PAK
To = 1.0%
4
TP6 GND_Input TP7 12 V_Input
R3 20k R4 13k
TP1 2.5V C7 1800mF 6.3V Prov. C8 C9 1800mF 0.1mF 6.3V C11 C10 1800mF 1800mF 6.3V 6.3V VDDQ (+2.5V, 8A)
Tol = 1.0%
U1 VCC
MTB1306 D2PAK
http://onsemi.com
AND8079/D
3
-
V- 0.1mF 1 OUT V+ 8 C17
R7 1k C20 1800mF 6.3V Prov. C21 C22 1800mF 0.1mF 6.3V Prov. C23 1800mF 6.3V
+
TP3 GND_Output
0.1mF
Q5 MTD20P03HDL DPAK
C18 TP10 -12 V_Input Tol. = 1.0% R5 10K U2B LM358 6 0.15mF
VREF (+1.25V, 2mA)
TP4 1.25V_Ref
-
OUT
7
R8 200
+
5 Tol. = 1.0% R6 10K C15 1mF
R9 100
C19 2mF
Note: The provisional components were not used in the verification of the reference design.
Figure 2. DDR Memory Reference Design
AND8079/D
Component Selection
Input Inductor
The input inductor (LIN) is used to isolate the input power supply from the switching portion of the buck regulator. LIN also limits the inrush current into the bulk input capacitors and limits the input current slew rate that results from the transient load. The inductor blocks the ripple current and transfers the transient current requirement to the bulk input capacitor bank. The design equations for LIN are listed below and for connivance an inductance of 1.0 mH is chosen. The cut-off frequency of the second order LC filter provides adequate attenuation for the 200 kHz switching frequency of the NCP1571.
DV LIN + + 5 V * 2.5 V 10 A (dI dt)Max f * 3db + 1 + 2p 2p LIN CIN + 216 Hz 5 ms + 1.25 mH 1 1 mH
Output Capacitors The output capacitors are selected to meet the desired output ripple requirements. The key specifications for the capacitors are their ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance). In order to obtain a good transient response, a combination of low value/high frequency ceramic capacitors and bulk electrolytic capacitors are placed as close to the load as possible. The voltage change during the load current transient is:
DVOUT + DIOUT ^ DIOUT ESL ) ESR ) tr Dt COUT ESR
Empirical data indicates that most of the output voltage change that results from the load current transients is determined by the capacitor ESR; therefore, the maximum allowable ESR can be approximated from the following equation.
ESR max ^ DVOUT + 75 mV + 7.5 mW 10 A DIOUT
5400 mF
where: LIN = input inductor CIN = bulk input capacitor(s) dI/dt = 10 A in 5.0 ms Input Capacitors The input filter capacitors provide a charge reservoir that minimizes the supply voltage variations due to the pulsating current through the MOSFETs. The input capacitors are chosen primarily to meet the ripple current rating of the capacitors. The design equation is listed below.
ICin(RMS) + D + .5 (1 * .5) (1 * D) 102 + 5 A Iout2
The number of capacitors is calculated by using the equation listed below.
Number of capacitors + ESRCAP + 19 mW + 2.5 7.5 mW ESR max
The ESR of the Rubycon 6.3 V 1800 mF capacitors is specified at 19 mW; therefore, 3 capacitors are used in the design. MOSFET Selection The output switch MOSFETs are chosen based on the gate charge/gate-source threshold voltage, gate capacitance, on resistance, current rating and the thermal capacity of the package. In this DDR design, the MOSFETs were chosen for economical reasons and have a current and power rating that is much better than needed for this design. In addition, the MOSFETs selected were verified by measuring the thermal characteristics of the devices on the PCB. The power dissipation design equation for selecting the MOSFETs is given below.
P + IMAX2 RDS(ON) VDS 2 I D ) MAX Tf FS VDS 2 Tr FS
where: D = duty cycle = VOUT/VIN = 2.5 V/5.0 V = 0.5 IOUT = maximum output current The Rubycon 10 V 1800 mf capacitors have a ripple current rating of 2.55 A. Thus only 2 of the capacitors are needed to meet the ripple requirements; however, 3 capacitors were chosen to be conservative. Output Inductance The main criterion in selecting the output filter inductance (LOUT) is to provide a satisfactory response to the load transients. The inductance affects the output voltage ripple by limiting the rate at which the current can either increase or decrease. The design equation used for selecting LOUT is listed below. A 2.2 mH inductor was chosen for the design.
LOUT + (VIN * VOUT) DI + 2.5 mH tr + (5 V * 2.5 V) 10 A 10 ms
I ) MAX
where: Tr = rise time or turn-on time of MOSFET Tf = fall time or turn-off time of MOSFET FS = switching frequency
where: tr = output transient load time
http://onsemi.com
4
AND8079/D
Schottky Diode for Synchronous MOSFET The efficiency of the buck converter can be improved slightly by placing a Schottky diode (D1) in parallel with the bottom MOSFET (Q3). The body diode of Q3 is used to conduct current during the non-overlap time when both the top (Q2) and bottom (Q3) MOSFETs are turned OFF. But because the non-overlap time is only approximately 50 ns for the NCP1571's 200 kHz switching speed, the efficiency savings will be only approximately 1.0%. The demonstration board included a provision for D 1; however, the performance of the circuit was not testing with this diode. Experimental Results The experimental results of the demonstration PCB are shown in Figures 4 through 20. Figure 3 shows the test setup used to create the current load transients for the Vtt supply voltage. The transient current load tests for the Vdd and Vtt supply voltages were created using a Kikusui Electronic Load Controller. Unless noted, the standard test conditions are as listed below: 1. Ambient Temperature = 23_C 2. Vdd Current Load (IVdd) = 8.0 A 3. Vtt Current Load (IVtt) = 1.25 A source load 4. VREF Current Load (IREF) = 2.5 mA 5. 5.0 V Input Voltage = 5.00 V 6. 12 V Input Voltage = 12.00 V 7. -12 V Input Voltage = -12.00 V
Vtt DDR Circuit
2.5 V Vdd
Q4
+
2.0 A DC Current Source
VREF U2A
OUT +
R7 + C22 Q5 + C23 + -
Vtt Pulsating Current Source
Pulse Width = 100 ms Period = 200 ms l1 = 0 A l2 = 4.0 A Rise Time = 50 ms Fall Time = 50 ms
DC Current Source 2 .0 A 2.0 A Vtt Circuit 0A Pulsating Current Source 2.0 A Current Sink Test Vtt Vtt Circuit
DC Current Source 2 .0 A 2.0 A Vtt 4A Pulsating Current Source 2.0 A Current Source Test
Figure 3. Vtt Transient Load Test Setup for a 2.0 A Sink to 2.0 A Source Test
http://onsemi.com
5
AND8079/D
2.6 2.4 OUTPUT VOLTAGE (V) 2.2 2.0 1.8 1.6 1.4
JVtt
2.475 Vdd Vdd VOLTAGE (V) 2.470 2.465 2.460 2.455 2.450 2.445
YVref
Vdd
1.2 1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
2.440 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Vdd LOAD (A) Vdd LOAD (A)
Figure 4. Output Voltage vs. Vdd Load
Figure 5. Vdd Voltage vs. Vdd Load
1.234 1.232 VOLTAGE (V) Vtt & Vref 1.230 1.228 1.226 1.224 1.222 1.220 1.218 1.216 1.214 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Vtt Vref VOLTAGE OUTPUT (V)
2.6 2.4 2.2 2.0 1.8 1.6 1.4
JVtt
Vdd
1.2 1.0 3.5
YVref
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
Vdd LOAD (A)
INPUT VOLTAGE (V)
Figure 6. Vtt and Vref vs. Vdd Load
Figure 7. Output Voltage vs. Input Voltage
0.90 0.85 EFFICIENCY (%) 0.80 0.75 0.70 0.65 EFFICIENCY EFFICIENCY (%)
0.82 0.81 EFFICIENCY 0.80 0.79 0.78 0.77 0.76 0.75
0.60 0 1 2 3 4 5 6 Vdd LOAD CURRENT (A) 7 8
0.74
3
4
5
6 7 8 INPUT VOLTAGE (V)
9
10
Figure 8. Efficiency vs. Vdd Load
Figure 9. Efficiency vs. Input Voltage
http://onsemi.com
6
AND8079/D
Channel 1: L2 Inductor Voltage Channel 2: Bottom (Q3) Buck MOSFET Gate Drive Channel 3: Top (Q2) Buck MOSFET Gate Drive
Figure 10. L2 Inductor Voltage, Top (Q2) and Bottom (Q3) Buck MOSFET Gate Drive
Channel 1: Vdd ripple voltage Channel 2: Vtt ripple voltage
Figure 11. Steady-State Vdd and Vtt with IVdd = 0.1 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA http://onsemi.com
7
AND8079/D
Channel 1: VREF ripple voltage
Figure 12. Steady-State VREF with IVdd = 0.1 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA
Channel 1: Vdd ripple voltage Channel 2: Vtt ripple voltage
Figure 13. Steady-State Vdd and Vtt with IVdd = 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA
http://onsemi.com
8
AND8079/D
Channel 1: VREF ripple voltage
Figure 14. Steady-State VREF with IVdd = 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA
Channel 1: Vdd ripple voltage Channel 2: Transient current load IVdd = 0 to 8.0 A
Figure 15. Vdd with a Transient Load IVdd = 0 to 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA http://onsemi.com
9
AND8079/D
Channel 1: Vtt ripple voltage Channel 2: Transient current load IVdd = 0 to 8.0 A
Figure 16. Vtt with a Transient Load IVdd = 0 to 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA
Channel 1: VREF ripple voltage Channel 2: Transient current load IVdd = 0 to 8.0 A
Figure 17. VREF with a Transient Load IVdd = 0 to 8.0 A, IVtt = 1.25 A Sourcing and VREF = 2.45 mA http://onsemi.com
10
AND8079/D
Channel 1: Vdd ripple voltage Channel 2: Transient current load IVtt = 0 to 4.0 A sourcing (i.e. -2.0 A sinking to +2.0 A sourcing transient current load)
Figure 18. Vdd with a Transient Load IVtt = -2.0 to +2.0 A, IVdd = 8.0 A and VREF = 2.45 mA
Channel 1: Vtt ripple voltage Channel 2: Transient current load IVtt = 0 to 4.0 A sourcing (i.e. -2.0 A sinking to +2.0 A sourcing transient current load)
Figure 19. Vtt with a Transient Load IVtt = -2.0 to +2.0 A, IVdd = 8.0 A and VREF = 2.45 mA http://onsemi.com
11
AND8079/D
Channel 1: 5.0 V Input Voltage Channel 2: Transient current load of IVdd = 0 to 8.0 A
Figure 20. Switching Noise Reflected to the 5.0 V Input Power Supply with a Transient Load IVdd = 0 to 8.0 A, IVtt = 0 to 4.0 A Sourcing (i.e. -2.0 A Sinking to +2.0 A Sourcing Transient Current Load) and VREF = 2.45 mA
Table 1: Component temperature measured in still air at an ambient temperature of 23_C. The load conditions were: 1. Vdd Transient current load IVdd = 0 to 8.0 A 2. Vtt Transient current load IVtt = 0 to 4.0 A sourcing (i.e. -2.0 A sinking to +2.0 A sourcing transient current load) 3. Steady state VREF current load IREF = 2.5 mA
Table 1.
Circuit Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vtt Vtt Vtt Component FET Diode (Q1) Top FET (Q2) Bottom FET (Q3) Input Inductor (L1) Output Inductor (L2) Input Capacitor (C2) Output Capacitor (C10) NCP1571 (U1) LM358 (U2) Top FET (Q4) Bottom FET (Q5) Temperature (5C) 41.6 54.2 56.4 42.1 57.9 33.0 31.2 55.0 46.2 42.1 49.3
http://onsemi.com
12
AND8079/D
DEMONSTRATION DESIGN PCB
Figure 21. Component Layout
Figure 22. TopSide of PCB (layer 1)
http://onsemi.com
13
AND8079/D
Figure 23. Bottom Side of PCB (layer 2)
http://onsemi.com
14
AND8079/D
3.80
2.15
0 0.125 0 0.125
Figure 24. Drill Plot
Size 62 38 62 18 125 Qty. 5 22 2 41 5 Symbol
http://onsemi.com
15
AND8079/D
Table 2. Demonstration Board Bill of Materials
Item 1 2 Quantity 4 7 Reference C1, C2, C3, C5 C7, C8, C10, C11, C20, C21, C23 C4, C9, C12, C14, C16, C17, C22 C6 C18 C13 C15 C19 L1 L2 Q1, Q2, Q3 Q4 Q5 R1 R2 R3 R4 R5, R6 R7 R8 R9 U1 U2 U3 D1 Part 1800 mF, 10 V 1800 mF, 6.3 V Part No. MBZ Series MBZ Series Package see data sheet see data sheet Mfg. Rubycon Rubycon Comments C5 is provisional C7, C20 and C21 are provisional -
3
7
0.1 mF
-
SMT 1206
-
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NOTE:
1 1 1 1 1 1 1 3 1 1 1 1 1 1 2 1 1 1 1 1 1 1
100 pF 0.15 mF 0.01 mF 1.0 mF 2.0 mF 1.0 mH 2.2 mH N-Channel Mosfet N-Channel Mosfet P-Channel Mosfet 10 ohm 47 Kohm 20 Kohm 13 Kohm 10 Kohm 1.0 Kohm 200 ohm 100 ohm Sync. Buck Controller Op-Amp LDO Regulator Schottky Diode
DO3316P-102HC DO5022P-222HC MTB1306 NTD4302 MTD20P03HDL NCP1571 LM358DMR2 MC33375ST-2.5T3 MBRM110LT
SMT O805 SMT 1206 SMT O805 SMT O805 SMT O805 see data sheet see data sheet D2PAK DPAK Bent Lead DPAK Bent Lead SMT O805 SMT O805 SMT O805 SMT O805 SMT O805 SMT O805 SMT O805 SMT O805 SO-8 Micro-8 SOT-223 PowerMite
Coilcraft Coilcraft ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor
U3 is provisional D1 is provisional
The provisional components were not used in the verification of the reference design.
Acknowledgement
The author would like to acknowledge Tod Schiff's assistance in designing the linear Vdd circuit.
http://onsemi.com
16
AND8079/D
Notes
http://onsemi.com
17
AND8079/D
Notes
http://onsemi.com
18
AND8079/D
Notes
http://onsemi.com
19
AND8079/D
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
http://onsemi.com
20
AND8079/D

▲Up To Search▲

Price & Availability of AND8079

	To Download AND8079 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .