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CXP82220/82224
CMOS 8-bit Single Chip Microcomputer
Description The CXP82220/82224 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, fluorescent display tube controller/driver, remote control reception circuit, CTL duty detection circuit, 14-bit PWM output, high-speed output circuit and other servo systems besides the basic configurations of 8-bit CPU, PROM, RAM, and I/O port. The CXP82220/82224 also provides power-on reset function and sleep/stop function that enables lower power consumption. 100 pin QFP (Plastic)
Structure Silicon gate CMOS IC
Features * Wide-range instruction system (213 instructions) to cover various types of data -- 16-bit arithmetic/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 400ns at 10MHz operation 122s at 32kHz operation * Incorporated ROM capacity 20K bytes (CXP82220) 24K bytes (CXP82224) * Incorporated RAM capacity 704 bytes (including fluorescent display area) * Peripheral functions -- A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 32s/10MHz) -- Serial interface SIO with 8-bit, 8-stage FIFO incorporated for data use (Auto transfer for 1 to 8 bytes), 1 channel 8-bit standard SIO, 1 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer 16-bit capture timer/counter, 32kHz timer/counter -- Fluorescent display tube controller/driver Maximum of 384 segment display possible 1 to 16-digit dynamic display Dimmer function High voltage drive output (40V) Incorporated pull-down resistor (Mask option) Hardware key scan function Maximum of 16 x 8 key matrix compatible -- Remote control reception circuit Incorporated noise elimination circuit Incorporated 8-bit, 6-stage FIFO for measurement data -- PWM output circuit 14 bits, 1 channel -- CTL duty detection circuit -- High-speed output circuit Precision of 800ns at 10MHz, 4 outputs * Interruption 19 factors, 15 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 100-pin plastic QFP * Piggyback/evaluation chip CXP82200 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E92235A81-PS
Block Diagram
AVSS
AVREF
PA0/AN0 to PA7/AN7 SPC700 CPU CORE CLOCK GEN./ SYSTEM CONTROL
8
A/D CONVERTER
PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI
TEX TX EXTAL XTAL RST VDD VSS
8 7
PA0 to PA7 PB0 to PB6 PB7 8 PC0 to PC7
8 RAM 80 BYTES
8
T0 to T7 T8/S31 to T15/S24 PD0/S0 to PI7/S23 VFDP RAM 704 BYTES
24
FDP CONTROLLER/ DRIVER
PE6/PWM
14 BIT PWM GENERATOR
PE5/CTL PE7/DDO FIFO
CTL DUTY DET
INTERRUPT CONTROLLER
ROM 20K BYTES (CXP82220) 24K BYTES (CXP82224)
8 6 2 8
PD0 to PD7 PE0 to PE5 PE6 to PE7 PF0 to PF7
PE7/TO PB0/CINT PE1/INT1/EC1 2
4
PG0/RTO0 to PG3/RTO3
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
PRESCALER/ TIME BASE TIMER 32kHz TIMER/COUNTER
-2-
FIFO 222 2 2 REALTIME PULSE GENERATOR CH0 CH1
PE4/RMC
REMOCON
PB1/CS0 PB3/SI0 PB4/SO0 PB2/SCK0
SERIAL INTERFACE UNIT 0
PB6/SI1 PB7/SO1 PB5/SCK1
SERIAL INTERFACE UNIT 1
8
PG0 to PG7
PE0/INT0/EC0
8 BIT TIMER/COUNTER 0
8
PH0 to PH7
8 BIT TIMER 1
16 BIT CAPTURE TIMER/COUNTER 2
8
PI0 to PI7
CXP82220/82224
CXP82220/82224
Pin Assignment (Top View)
PE0/EC0/INT0
PG3/RTO3
PG2/RTO2
PG1/RTO1
PG0/RTO0
PG6
PG5
PG4
VSS
NC
VDD
VFDP
PG7
T1
T2
T3
T4
T5
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/CTL PE6/PWM PE7/TO/DDO/ADJ PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 T7 T8/S31 T9/S30 T10/S29 T11/S28 T12/S27 T13/S26 T14/S25 T15/S24 PI7/S23 PI6/S22 PI5/S21 PI4/S20 PI3/S19 PI2/S18 PI1/S17 PI0/S16 PF7/S15 PF6/S14 PF5/S13 PF4/S12 PF3/S11 PF2/S10 PF1/S9 PF0/S8 PD7/S7 PD6/S6 PD5/S5 PD4/S4 PD3/S3
PA0/AN0
PA6/AN6
RST
T0
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA7/AN7
PD0/S0
PD1/S1
PH7
TEX
TX
EXTAL
AVREF
XTAL
AVSS
VSS
Note) NC (Pin 90) must be connected to VDD. -3-
PD2/S2
T6
CXP82220/82224
Pin Description Symbol PA0/AN0 to PA7/AN7 PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 to PC7/KR7 PD0/S0 to PD7/S7 I/O I/O/ Analog input I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input Output/Output (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA synk current. (8 pins) (Port D) 8-bit output port. (8 pins) (Port B) 8-bit I/O port. I/O for lower 7 bits can be set in a unit of single bit. Uppermost bit (PB7) is for output only. (8 pins) (Port A) 8-bit I/O port. I/O can be set in a unit of single bit . (8 pins) Functions Analog inputs to A/D converter. (8 pins) External capture input to 16bittimer/counter. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).
I/O/Input
Serves as key return inputs when operating key scan with FDP segment signal.
Output/Output
FDP segment signal outputs. External event inputs for timer/counter. (2 pins)
PE0/INT0/EC0 Input/Input/Input PE1/INT1/EC1 Input/Input/Input PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/CTL PE6/PWM PE7/TO/DDO/ ADJ PF0/S8 to PF7/S15 Input/Input Input/Input/Input Input/Input Input/Input Output/Output Output/Output/ Output/Output (Port F) 8-bit output port. (8 pins) (Port G) 8-bit I/O port. I/O can be set in a unit of single bit. Data for the lower 4 bits are gated with the contents of RTO or OR-gate output. (8 pins) -4- (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) Inputs for external interruption request. (4 pins)
Non-maskable interruption request input.
Remote control reception circuit input. Input for CTL duty ditection circuit. 14-bit PWM output. Output for the 16-bit timer/counter rectangular waves, CTU duty detection, and 32kHz oscillation frequuency demultiplication. FDP segment signal outputs. Outputs for real-time pulse generator (RTG). Functions as high-precision, real-time pulse output port. (4 pins)
Output/Output
PG0/RTO0 to PG3/RTO3 PG4 to PG7
I/O/Output
I/O
CXP82220/82224
Symbol PH0 to PH7 PI0/S16 to PI7/S23 T8/S31 to T15/S24 T0 to T7 VFDP EXTAL XTAL TEX TX RST NC AVREF AVSS VDD VSS Input Input I/O
I/O
Functions (Port H) 8-bit I/O port. I/O can be set in a unit of single bit. (8 pins) (Port I) 8-bit output ports. (8 bits) FDP segment signal outputs.
Output/Output
Output/Output Output
Outputs for FDP timing (digit) signals/segment signals. FDP timing signal outputs. FDP voltage supply when incorporated resistor is set by mask option. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz crystal oscillator between TEX and TX. For usage as event input, attach clock source to TEX, and open TX. Low-level active, system reset. NC. Under normal operation, connect to VDD. Reference voltage input for A/D converter. A/D converter GND. Positive power supply. GND.
Output Input Output Input
-5-
CXP82220/82224
Input/Output Circuit Formats for Pins Pin Port A
Port A data
Circuit format
When reset
PA0/AN0 to PA7/AN7
Data bus
Port A direction "0" when reset
IP
Input protection circuit
Hi-Z
RD (Port A) Port A input selection "0" when reset Input multiplexer A/D converter
8 pins Port B
Port B data
PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1
Port B direction "0" when reset Data bus RD (Port B) CINT CS0 SI0 SI1 Schmitt input
IP
Hi-Z
4 pins
Port B
SCK out Output enable Port B output selection "0" when reset
PB2/SCK0 PB5/SCK1
Port B data Port B direction "0" when reset Data bus Schmitt input
IP
Hi-Z
RD (Port B)
2 pins
SCK in
-6-
CXP82220/82224
Pin Port B
SO Output enable Port B output selection "0" when reset
Circuit format
When reset
PB4/SO0
Port B data Port B direction "0" when reset Data bus
IP
Hi-Z
1 pin Port B
RD (Port B)
Internal reset signal SO Output enable
PB7/SO1
Port B output selection "1" when reset Port B data "1" when reset Data bus
High level
1 pin
Pull-up transistor approx. 10k RD (Port B)
Port C
Port C data
PC0/KR0 to PC7/KR7
Data bus
Port C direction "0" when reset
IP
Hi-Z
RD (Port C) Key input signal Large current drive of 12mA possible
8 pins Port E
Schmitt input IP
PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/CTL 6 pins
EC0/INT0 EC1/INT1 INT2 INT3/NMI RMC CTL Data bus RD (Port E)
Hi-Z
-7-
CXP82220/82224
Pin Port E
PWM Port E output selection
Circuit format
When reset
PE6/PWM
"0" when reset Port E data "1" when reset Data bus
High level
1 pin Port E
RD (Port E)
Output enable TO DDO ADJ16K ADJ2K
0 1 MPX 2 3
PE7/TO/ DDO/ADJ
Port E output selection Port E output selection "00" when reset Port E output selection "0" when reset Port E data "1" when reset Data bus ADJ signal is a frequency demultiplication output for 32kHz oscillation frequency adjustment. ADJ2K can be used for buzzer output.
High level
1 pin Port G
RD (Port E)
RTO data "0" when reset
PG0/RTO0 to PG3/RTO3
Port G data
Hi-Z
Port G direction "0" when reset Data bus IP
4 pins
RD (Port G)
-8-
CXP82220/82224
Pin Port G Port H
Circuit format
When reset
Port G or Port H data
PG4 to PG7 PH0 to PH7
Port G or Port H direction "0" when reset Data bus RD (Port G or Port H)
IP
Hi-Z
12 pins PD0/S0 to PD7/S7 PF0/S8 to PF7/S15 PI0/S16 to PI7/S23 24 pins Port D Port F Port I
Segment output data
Output selection control signal ("0" when reset) Port D, F, or I data "0" when reset Data bus RD (Port D, F, or I) Pull-down resistor
OP
Mask option
Hi-Z or Low level (when PD resistance is added)
VFDP High voltage drive transistor
Segment output data
T15/S24 to T8/S31 T0 to T7
Output selection control signal ("0" when reset)
OP Mask option Pull-down resistor VFDP
Hi-Z or Low level (when PD resistance is added)
16 pins
High voltage drive transistor
EXTAL XTAL
* Diagram shows circuit composition during oscillation. EXTAL IP IP * Feedback resistor is removed during stop. XTAL
Oscillation
2 pins
-9-
CXP82220/82224
Pin
Circuit format
* Diagram shows circuit composition during oscillation.
When reset
TEX TX
TEX
IP
IP
TX
2 pins
* When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX and TX become "Low" level and "High" level respectively.
Oscillation
Pull-up resistor
RST
Mask option OP IP
Low level
1 pin
Schmitt input
- 10 -
CXP82220/82224
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Display output voltage Symbol VDD AVSS VIN VOUT VOD IOH High level output current IODH1 IODH2 IOH IODH IOL IOLC IOL Topr Tstg PD Rating -0.3 to +7.0 -0.3 to +0.3 -0.3 to +7.01 -0.3 to +7.01 VDD - 40 to VDD + 0.3 -5 -15 -35 -40 -100 15 20 100 -20 to +75 -55 to +150 600 Unit V V V V
(Vss = 0V reference) Remarks
As P channel transistor is open drain, VDD is reference. All pins excluding display outputs2 mA (value per pin) V mA Display outputs S0 to S23 (value per pin) mA Display outputs T0 to T7, and T8/S31 to T15/S24 (value per pin)
High level total output current
mA Total for all pins excluding display outputs mA Total for all display outputs mA Port 1 mA Large current Port 1 3 mA Total for all output pins C C mW
Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation
1 VIN and VOUT must not exceed VDD + 0.3V. 2 Specifies output current of general-purpose l/O ports. 3 The large current drive transistor is the N-CH transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSl.
- 11 -
CXP82220/82224
Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.7 2.5 VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 VDD VDD V V V V V V C V Unit
(Vss = 0V reference) Remarks High-speed mode Guaranteed operation range Low-speed mode Guaranteed operation range Guaranteed operation range with TEX clock Guaranteed data hold range during stop 1 Hysteresis input2 EXTAL3 1 Hysteresis input2 EXTAL3
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD 0.4 +75
1 Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PG, PH). 2 Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC, CTL. 3 Specifies only during external clock input.
- 12 -
CXP82220/82224
Electrical Characteristics DC Characteristics Item High level output voltage Low level output voltage Symbol VOH PA, PB, PC,PE6, PE7, PG, PH VOL PC IIHE IILE Input current IIHT IILT IILR Display output current IOH RST1 S0 to S23 S24/T15 to S31/T8 T0 to T7 S0 to S23 S24/T15 to S31/T8 T0 to T7 S0 to S23 S24/T15 to S31/T8 T0 to T7 PA to PC, PE, PG, PH, RST1 TEX EXTAL Pins
(Ta = -20 to +75C, Vss = 0V reference) Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VOH = VDD - 2.5V VDD = 5.5V VOL = VDD - 35V VFDP = VDD - 35V VDD = 5V VFDP = VDD - 35V VDD = 5.5V VI = 0, 5.5V High-speed mode operation (1/2 frequency demultiplier clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD Sleep mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Stop mode VDD = 5.5V, termination of 10MHz and 32kHz crystal oscillation
Pins other than Clock 1MHz S0 to S31, T0 to T7, PB7, PE6,PE7,AVREF, 0V for all pins excluding AVSS, VFDP, VDD, VSS measured pins
Min. 4.0 3.5
Typ.
Max. Unit V V 0.4 0.6 1.5 V V V A A A A
0.5 -0.5 0.1 -0.1 -1.5 -8 -20
40 -40 10 -10
-400 A mA mA
Open drain output leakage current ILOL (P-CH Tr in off state) Pull-down resistance2 RL
-20
A
60
100
270 10
k
I/O leakage current IIZ
A
IDD1
20
40
mA
IDD2 Supply current3 IDDS1
35
100
A
1.2
8
mA
IDDS2
9
30
A
IDDS3
10
A
Input capacity
CIN
10
20
pF
1 RST specifies the input current when pull-up resistance has been selected; leakage current when no resisance has been selected. 2 When incorporated pull-down resistance has been selected through mask option. 3 When all pins are open. - 13 -
CXP82220/82224
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input clock input pulse width Event count input clock rise time,fall time 1 Symbol fC Pins
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. 1 37.5 200 Typ. Max. 10 Unit MHz ns ns ns 20 ms
XTAL Fig. 1, Fig. 2 EXTAL Fig. 1, Fig. 2 EXTAL External clock drive Fig. 1, Fig. 2 EXTAL External clock drive EC0 EC1 EC0 EC1 TEX TX TEX TEX Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
tsys + 501
32.768
kHz
tTL, tTH tTR, tTF
10 20
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR
Fig. 1. Clock timing
Crystal oscillation Ceramic oscillation
External clock
32kHz clock applied condition Crystal oscillation
EXTAL C1
XTAL C2
EXTAL
XTAL C1
TEX
TX C2
74HC04
Fig. 2. Clock applied conditions - 14 -
CXP82220/82224
TEX EC0 EC1 tEH tTH tEF tTF tEL tTL tER tTR
0.8VDD 0.2VDD
Fig. 3. Event count clock timing
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level width SI0 input setup time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss=0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SO0 SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH, tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 50 100 200
tsys + 200
100
tsys + 200
100
ns ns
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
- 15 -
CXP82220/82224
tWHCS
CS0 0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
Fig. 4. Serial transfer CH0 timing
- 16 -
CXP82220/82224
Serial transfer (CH1) Item SCK1 cycle time Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode SCK1 Input mode Output mode SI1 SCK1 input mode SCK1 output mode SI1 SCK1 input mode SCK1 output mode SO1 SCK1 input mode SCK1 output mode Min. 1000 16000/fc 400 8000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH, tKL tSIK tKSI tKSO
SCK1 High, Low level width SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
tKCY tKL tKH
SCK1 0.8VDD 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
Fig. 5. Serial transfer CH1 timing
- 17 -
CXP82220/82224
(3) A/D converter characteristics (Ta = -20 to +75C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT1 VFT2 Ta = 25C VDD = AVDD = 5.0V VDD = AVss = 0V -10 4930 160/fADC 3 12/fADC 3 AVREF AN0 to AN7 Operation mode AVREF Sleep mode Stop mode 32kHz operation mode VDD - 0.5 0 0.6 VDD AVREF 1.0 10 70 5050 Symbol Pin Condition Min. Typ. Max. 8 5 150 5120 Unit Bits LSB mV mV s s V V mA A
tCONV tSAMP
VIAN IREF
Reference input voltage VREF Analog input voltage
AVREF current
IREFS
FFH FEH
Digital conversion value
1 VZT : Value at which the digital conversion value changes from 00H to 01H and vice versa. 2 VFT : Value at which the digital conversion value changes from FEH to FFH and vice versa. 3 fADC indicates the below values due to ADC operation
Linearity error 01H 00H VZT Analog input VFT
clock selection (ADCS: Bit 6 of address 00F9H). During PS2 selection, fADC = fc/2 During PS1 selection, fADC = fc
Fig. 6. Definitions of A/D converter terms
- 18 -
CXP82220/82224
(4) Interruption, reset input Item External interruption High, Low level width Reset input Low level width
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins INT0 INT1 INT2 NMI/INT3 RST Condition Min. Max. Unit
tIH tIL tRSL
1
s
8/fc
s
tIH
tIL
0.8VDD INT0 INT1 INT2 NMI/INT3 (NMI specifies only for the falling edge) 0.2VDD tIL tIH
Fig. 7. Interruption input timing
tRSL
RST 0.2VDD
Fig. 8. RST input timing
(5) Others Item CLK input High, Low level width Symbol Pin CTL
(Ta = -20 to +75C, VDD = 4.5 to 5.0V, VSS = 0V reference) Condition Min. Max. Unit ns
tCTH, tCTL
tsys = 2000/fc
tCTH tCTL
tsys + 200
0.8VDD CTL 0.2VDD
Fig. 9. Other timing - 19 -
CXP82220/82224
Appendix
(i) Main clock (ii) Main clock (iii) Sub clock
EXTAL
XTAL
EXTAL
XTAL
TEX
TX Rd
C1
C2 C1 C2
C1
C2
Fig. 10. Recommended oscillation circuit
Manufacturer
Model CSA4.19MG CSA8.00MG
fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19
C1 (pF)
C2 (pF)
Circuit example
(i) 30 30 (ii)
MURATA MFG CO., LTD
CSA10.0MT CST4.19MGW CST8.00MTW CST10.00MTW
RIVER ELETEC HC-49/U03 CORPORATION
15
15 (i)
KINSEKI LTD.
HC-49/U (-S)
8.00 10.00
27
27
Those marked with an asterisk () signify types with built-in ground capacitance (C1, C2).
Mask option table Item Reset pin pull-up resistor High voltage drive output port pull-down Non-existent Non-existent Contents Existent Existent
- 20 -
CXP82220/82224
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 10
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
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