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| Buffer PI6C2502 Reference Clock Signal V 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2502A Phase-Locked Loop Clock Driver Product Features * High-Performance Phase-Locked-Loop Clock Distribution for Networking, * Synchronous DRAM modules for server/workstation/ PC applications * Allows Clock Input to have Spread Spectrum modulation for EMI reduction * Zero Input-to-Output delay * Low jitter: Cycle-to-Cycle jitter 75ps max. * On-chip series damping resistor at clock output drivers for low noise and EMI reduction * Operates at 3.3V VCC * Wide range of Clock Frequencies 80 to 134 MHz * Package: Plastic 8-pin SOIC Package (W) Product Description The PI6C2502A features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. Application If a system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-to-device skew introduced can significantly reduce the performance. Pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. As shown in Figure 1, this combination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. For example, when combined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer. Logic Block Diagram Product Pin Configuration CLK_IN PLL FB_IN AVCC CLK_OUT AGND FB_OUT CLK_OUT VCC 1 2 3 4 8-Pin W 8 7 6 5 CLK_IN AVCC GND FB_IN FB_OUT Feedback Zero Delay CLK_OUT 18 Output Non-Zero Delay Buffer 17 Figure 1. This Combination Provides Zero-Delay Between the Reference Clocks Signal and 17 Outputs. 1 PS8500 10/02/00 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2502A Phase-Locked Loop Clock Driver Pin Functions Pin Name CLK _IN FB_IN FB_O UT CLK _OUT AVC C AGND VC C GND Pin Numbe r 8 5 2 3 7 1 4 6 Type I I O O Power Ground Power Ground D e s cription Reference Clock input. CLK _IN allows spread spectrum clock input. Feedback input. FB_IN provides the feedback signal to the internal PLL. Feedback output FB_O UT is dedicated for external feedback. FB_OUT has an embedded series- damping resistor of the same value as the clock outputs CLK_OUT. Clock outputs. These outputs provide low- skew copies of CLK_IN. Each output has an embedded series- damping resistor. Analog power supply. AVC C can be also used to bypass the PLL for test purposes. When AVC C is strapped to ground, PLL is bypassed and CLK_IN is buffered directly to the device outputs. Analog ground. AGND provides the ground reference for the analog circuitry. Power supply. Ground. DC Specifications (Absolute maximum ratings over operating free-air temperature range) Symbol VI VO VI_DC IO_DC Power TSTG Parame te r Input voltage range Output voltage range DC input voltage DC output current Maximum power dissipation at TA = 55oC in still air Storage temperature 65 0.5 M in. M ax. VCC +0.5 3.8 100 1.0 150 mA W oC Units V Note: Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. Parame te r ICC CI CO VI = VCC or GND VO =VCC or GND Te s t Conditions VI = VCC or GND; IO = 0(1) Standby Current VCC 3.6V 3.3V M in. Typ. 4 6 M ax. 10 Units A pF Note: 1. Continuous Output Current 2 PS8500 10/02/00 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2502A Phase-Locked Loop Clock Driver Recommended Operating Conditions Symbol VCC VIH VIL VI TA Supply voltage High level input voltage Low level input voltage Input voltage Operating free- air temperature 0 0 Parame te r M in. 3.0 2.0 0.8 VCC 70 C M ax. 3.6 V Units Electrical Characteristics (Over Recommended Operating Free-Air Temperature Range Pull Up/Down Currents of PI6C2502A, VCC = 3.0V) Symbol IOH Parame te r Pull- up current Pull- up current Pull- down current Pull- down current Condition Vout = 2.4V Vout = 2.0V Vout = 0.8V Vout = 0.55V M in. M ax. 13.6 22 Units IOL 19 13 mA AC Specifications Symbol FCLK DCYI (Timing requirements over recommended ranges of supply voltage and operating free-air temperature) Parame te r Clock frequency PI6C2502A Input clock duty cycle Stabilization Time after power up M in. 80 40 M ax. 134 60 1 Units MHz % ms Switching Characteristics Parame te r tphase error without jitter Jitter, cycle- to- cycle Duty cycle tr, rise- time, 0.4V to 2.0V tf, fall- time, 2.0V to 0.4V (Over recommended ranges of supply voltage and operating free-air temperature, CL = 30pF) From (Input) CLK_IN at 100 & 66 MHz At 100 & 66 MHz To (Output) FB_IN VCC = 3.3V 0.3V, 0-70C M in. 150 75 45 1.0 1.1 Typ. M ax. +150 +75 55 Units ps % ns CLK_OUT Note: These switching parameters are guaranteed by design. 3 PS8500 10/02/00 Ordering Information Orde ring Code PI6C2502AW Package Name W8 Package Type 8- pin 150- mil SOIC Ope rating Range Commercial 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2502A Phase-Locked Loop Clock Driver Package Mechanical Information Plastic 8-pin SOIC Package 8 .149 .157 3.78 3.99 4.80 .189 5.00 .196 1 .016 REF .026 0.406 0.660 .053 .068 1.35 1.75 .0099 .0196 0.25 x 45 0.50 SEATING PLANE 0-8 .0075 .0098 0.40 .016 1.27 .050 .2284 .2440 5.80 6.20 0.19 0.25 .050 BSC 1.27 .013 .020 0.330 0.508 X.XX X.XX .0040 0.10 .0098 0.25 DENOTES DIMENSIONS IN MILLIMETERS Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 4 PS8500 10/02/00 |
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