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MWS5101, MWS5101A
March 1997
256-Word x 4-Bit LSI Static RAM
Description
The MWS5101 and MWS5101A are 256 word by 4-bit static random access memories designed for use in memory systems where high speed, very low operating current, and simplicity in use are desirable. They have separate data inputs and outputs and utilize a single power supply of 4V to 6.5V. The MWS5101 and MWS5101A differ in input voltage characteristics (MWS5101A is TTL compatible). Two Chip Select inputs are provided to simplify system expansion. An Output Disable control provides Wire-OR capability and is also useful in common Input/Output systems by forcing the output into a high impedance state during a write operation independent of the Chip Select input condition. The output assumes a high impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2. The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input. For applications requiring wider temperature and operating voltage ranges, the mechanically and functionally equivalent static RAM, CDP1822 may be used. The MWS5101 and MWS5101A types are supplied in 22 lead hermetic dual-in-line, sidebrazed ceramic packages (D suffix), in 22 lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
Features
* Industry Standard Pinout * Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA at VDD = 5V and Cycle Time = 1s * Two Chip Select Inputs Simple Memory Expansion * Memory Retention for Standby. . . . . . . . . . . . . 2V (Min) Battery Voltage * Output Disable for Common I/O Systems * Three-State Data Output for Bus Oriented Systems * Separate Data Inputs and Outputs * TTL Compatible (MWS5101A)
Pinout
MWS5101, MWS5101A (PDIP, SBDIP) TOP VIEW
A3 A2 A1 A0 A5 A6 A7 VSS DI1
1 2 3 4 5 6 7 8 9
22 21 20 19 18 17 16 15 14 13 12
VDD A4 R/W CSI O.D. CS2 DO4 DI4 DO3 DI3 DO2
DO1 10 DI2 11
Ordering Information
MWS5101 PACKAGE PDIP Burn-In SBDIP Burn-In TEMP. RANGE 0oC to +70oC 0oC to +70oC 250ns MWS5101EL2 350ns MWS5101ELS MWS5101A 250ns MWS5101AEL2 350ns MWS5101AEL3 PKG. NO. E22.4
MWS5101AEL3X E22.4 MWS5101DL3X MWS5101ADL3 D22.4A D22.4A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1106.2
6-56
MWS5101, MWS5101A
OPERATIONAL MODES INPUTS MODE Read Write Write Standby Standby Output Disable CHIP SELECT 1 (CS1) 0 0 0 1 X X CHIP SELECT 2 (CS2) 1 1 1 X 0 X OUTPUT DISABLE (OD) 0 0 1 X X 1 READ/WRITE (R/W) 1 0 0 X X X Read Data In High Impedance High Impedance High Impedance High Impedance OUTPUT
NOTE: Logic 1 = High, Logic 0 = Low, X = Don't Care.
Functional Block Diagram
4 3
(32) ROW 22 DECODERS
A0 A1
2 A2 1
A3 A4
21
(5) INPUT BUFFERS AND ALL ROWS DESELECT FUNCTION
VDD
9 DI1 11
DI2 DI3 DI4
(8 x 32) STORAGE ARRAY (4) GATES
(8 x 32) STORAGE ARRAY
(8 x 32) STORAGE ARRAY
(8 x 32) STORAGE ARRAY
(4) BITS (1-4) BUFFER DRIVERS 10
13 15
D01 12 D02 14 D03 16 D04
BIT (1)
BIT (2)
BIT (3)
BIT (4)
(8)
(8) COLUMN DECODERS
(8) COLUMN DECODERS
(8) COLUMN DECODERS
5 A5 6
A6 A7
7
(3) INPUT BUFFERS AND ALL COLUMNS DESELECT FUNCTION
COLUMN DECODERS
R/W
20
CONTROL B 8
CSI CS2 OD
19 17 18
VSS
CONTROL A
CONTROL C
VDD
VDD
VDD
VSS
VSS
VSS
INPUT PROTECTION
NETWORK
OUTPUT
PROTECTION CIRCUIT
OVER VOLTAGE
PROTECTION CIRCUIT
6-57
MWS5101, MWS5101A
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 80 21 Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS
PARAMETER DC Operating Voltage Range Input Voltage Range
MIN 4 VSS
MAX 6.5 VDD
UNITS V V
Static Electrical Specifications
At TA = 0oC to +70oC, VDD = 5V 5% CONDITIONS MWS5101 VO (V) VIN (V) 0, 5 0, 10 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 (NOTE 1) TYP 25 100 4 -2 0 5 4 5 10 LIMITS MWS5101A (NOTE 1) TYP 25 100 4 -2 0 5 4 5 10
PARAMETER Quiescent Device Current L2 Types L3 Types Output Low (Sink) Current Output High (Source) Current Output Voltage Low-Level Output Voltage High-Level Input Low Voltage Input High Voltage Input Leakage Current Operating Current (Note 2) Three-State Output Leakage Current Input Capacitance Output Capacitance NOTES: L2 Types L3 Types
SYMBOL IDD
MIN 2 -1 4.9 3.5 -
MAX 50 200 0.1 1.5 5 8 5 5 7.5 15
MIN 2 -1 4.9 2.2 -
MAX 50 200 0.1 0.65 5 8 5 5 7.5 15
UNITS A A mA mA V V V V A mA A A pF pF
IOL IOH VOL VOH VIL VIH IIN IDD1 IOUT
0.4 4.6 0, 5 0, 5
CIN COUT
-
1. Typical values are for TA = +25oC and nominal VDD. 2. Outputs open circuited; Cycle time = 1s.
6-58
MWS5101, MWS5101A
Dynamic Electrical Specifications
at TA = 0oC to +70oC, VDD = 5V 5% LIMITS (NOTE 1) L2 TYPES PARAMETER READ CYCLE TIMES (FIGURE 1) Read Cycle Access from Address Output Valid from Chip Select 1 Output Valid from Chip Select 2 Output Valid from Output Disable Output Hold from Chip Select 1 Output Hold from Chip Select 2 Output Hold from Output Disable WRITE CYCLE TIMES (FIGURE 2) Write Cycle Address Setup Write Recovery Write Width Input Data Setup Time Data in Hold Chip Select 1 Setup Chip Select 2 Setup Chip Select 1 Hold Chip Select 2 Hold Output Disable Setup NOTES: 1. MWS5101: tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD; CL = 100pF and MWS5101A: tR, tF = 20ns, VIH = 2.2V, VIL = 0.65V; CL = 50pF and 1 TTL Load. 2. Time required by a limit device to allow for the indicated function. 3. Typical values are for TA = 25oC and nominal VDD. tWC tAS tWR tWRW tDS tDH tCS1S tCS2S tCS1H tCS2H tODS 300 110 40 150 150 40 110 110 0 0 110 400 150 50 200 200 50 150 150 0 0 150 ns ns ns ns ns ns ns ns ns ns ns tRC tAA tDOA1 tDOA2 tDOA3 tDOH1 tDOH2 tDOH3 250 20 20 20 150 150 150 250 250 250 110 350 20 20 20 200 200 200 350 350 350 150 ns ns ns ns ns ns ns ns SYMBOL (NOTE 2) MIN (NOTE 3) TYP MAX (NOTE 2) MIN L3 TYPES (NOTE 3) TYP MAX UNITS
6-59
MWS5101, MWS5101A
tRC
A0 - A7
CHIP SELECT 1
tDOA1 tDOH1
CHIP SELECT 2
tDOA2
tDOH2
OUTPUT DISABLE
tDOA3
tDOH3
READ/WRITE tAA
DATA OUT HIGH IMPEDANCE
DATA OUT VALID
HIGH IMPEDANCE
FIGURE 1. READ CYCLE TIMING WAVEFORMS
tWC tWR A0-A7
tCS1S CHIP SELECT 1
tCS1H
CHIP SELECT 2 tCS2S OUTPUT DISABLE (NOTE) tODS DI1-DI4 tDS DATA IN STABLE tDH tCS2H
READ/WRITE tAS
tWRW
DON'T CARE
NOTE: tODS is required for common I/O operation only; for separate I/O operations, output disable is "don't care". FIGURE 2. WRITE CYCLE TIME WAVEFORMS
6-60
MWS5101, MWS5101A
Data Retention Specifications
at TA = 0oC to +70oC; See Figure 3 TEST CONDITIONS
LIMITS ALL TYPES
PARAMETER Minimum Data Retention Voltage Data Retention Quiescent Current L2 Types L3 Types Chip Deselect to Data Retention Time Recovery to Normal Operation Time VDD to VDR Rise and Fall Time NOTE:
SYMBOL VDR IDD
VDR (V) 2 2
VDD (V) 5 5 5
MIN 600 600 1
(NOTE 1) TYP 1.5 2 5 -
MAX 2 10 50 -
UNITS V A A ns ns s
tCDR tRC tR, tF
2
1. Typical Values are for TA = 25oC and nominal VDD .
VDD
DATA RETENTION MODE VDD VDR tCDR CS2 VIH VIL tF tR tRC VIH VIL WRITE ADDRESS DECODER DATA IN 0.95 VDD 0.95 VDD
VSS
VDD
FIGURE 3. LOW VDD DATA RETENTION TIMING WAVEFORMS
FIGURE 4. MEMORY CELL CONFIGURATION
6-61
DATA OUT
READ ADDRESS DECODER
MWS5101, MWS5101A
CONTROL A CS1 19 A CHIP-SELECT CONTROL
CS2 17
CONTROL B R/W 20 B CHIP-SELECT AND R/W CONTROL
CONTROL C C OUTPUT DISABLE CONTROL
OUTPUT 18 DISABLE
FIGURE 5. LOGIC DIAGRAM OF CONTROLS FOR MWS5101, MWS5101A
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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