View LC82151_135176.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CMOS LSI
No. *5601
LC82151
Single-Chip Facsimile Controller
Preliminary Overview
The LC82151 is a facsimile controller that integrates the main functions required by facsimile systems on a single chip. The LC82151 includes a FAX modem with ADPCM and HDLC functions, image processing functions that can create high-quality binary image data without external memory, a CODEC accelerator, a CPU and CPU peripheral circuits, general-purpose I/O ports, and other functions. A facsimile system with excellent costperformance characteristics can be created easily by providing ROM and RAM. * Modem - Group 3 FAX modem ITU-T V.29 (9600, 7200, and 4800 bps) ITU-T V.27ter (4800 and 2400 bps) ITU-T V.21ch2 (300 bps) - Simultaneous high/low-speed wait function - Short training function (ITU-T V.27ter only) - HDLC function (for all transmission speeds) - Synthesizer function - Caller ID function Bell 202 (1200 bps) ITU-T V.23 (1200 bps) - ADPCM function Encoding: 2, 3, or 4 bits Sampling frequencies: 9.6, 7.2, 4.8, and 3.6 kHz - RTC low-voltage backup - 5-V single-voltage power supply
Functions
* CPU and peripheral circuits - High-speed 16-bit CPU (65C816) operating at 7.4 MHz - 16-MB program address space - CODEC accelerator - Two-channel DMA controller - Four 16-bit timers - 16-bit watchdog timer - TPH interface - Serial I/O interface - Parallel I/O: 10 to 43 pins * Image processing - Processes 2048 pixels per line - Processing speed: 540 ns per pixel (maximum) - Built-in 8-bit A/D converter (Includes a sensor signal delay function.) - Sensor drive circuit (Supports CCDs and all major CIS devices.) - Distortion correction (White distortion: 8-pixel averaging correction, black correction: Allows the black correction subtraction data to be set.) - -correction (Supports user-defined correction curves.) - Simple binary conversion processing (fixed threshold and density-adaptive threshold) - Halftone processing error diffusion method (64 levels) - Image reduction (decimation, fine black line retention, and fine white line retention)
Package Dimension
unit: mm 3214-SQFP144
[LC82151]
SANYO: SQFP144
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
43097 (OT) No. 5601-1/8
LC82151 Block Diagram
AIN, ATAP, TEMP, SH, RS, ACLK1, ACLK2, ASAMP, DAREFH, DAREFL
O2, RES, R/W, IRQ, VP, RDY, BE, NMI, VPA, VDA, ABCNT
CPU 65C816
Image processing
PXD7 to PXD0 PDREQ, PDACK
RD, WR ROMCS, RAMCS, IOCS, MCS BREQ, BACK, EXRDY
CPU interface
Modem
TXA, RXA, PGCO, PGCI, VREF, RIN, VCOI, PHASEO, EYED, EYECLK, EYESYNC
PA7 to PA0 PB2 to PB0
PIO
CODEC accelerator
TO0 TO1
Timer
RTC
ROSC1 ROSC2
RTC, CTS, DSR, DTR, RI, DCD TD, RD
SIO
DMAC
WDT
Interrupt controller
INT2 INT8
PCK/SCLK, PDATA/TXD, EXCLK, LATCH/RXD, STB0 to STB3, HVON PROTECT
TPH interface
DRAM controller
RAS CAS
XTAL1, XTAL2, XOUT,CLKIN, RESET, BACKUP TEST2 to TEST0 TESTOUT
D7 to D0 A19 to A0
No. 5601-2/8
LC82151 Pin Assignment
Type I O Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin VSS VP RDY VPA VDA A19 A18 A17 A16 D7 D6 D5 D4 D3 D2 D1 D0 VDD VSS RD WR ROMCS RAMCS IOCS MCS RAS/PG1 CAS/PG2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VSS VDD RIN PHASEO VCOI INT8/PB7 INT2/PB6 BACK/PB5 BREQ/PB4 EXRDY/PB3 PB2 PB1 PB0 NMI TEST2 I/O P I O I I O O O O B B B B B B B B P P O O O O O O B B B B B B B B B B P P I O I B B B B B B B B I I Non-maskable interrupt request signal Test pin General-purpose port B Ground Power supply PLL bias input PLL phase detector output PLL voltage-controlled oscillator input External interrupt request signal/general-purpose port B CPU bus acknowledge signal/general-purpose port B CPU bus request signal/general-purpose port B External ready input/general-purpose port B General-purpose port A Power supply Ground Read signal from the CPU Write signal from the CPU Program ROM chip select signal Working RAM chip select signal External I/O chip select signal External I/O chip select signal DRAM row address strobe/general-purpose port G DRAM column address strobe/general-purpose port G Data bus Address bus Ground ICE vector address signal ICE ready signal ICE valid program address signal ICE valid data address signal Input pins Output pins B P Bidirectional pins Power pins Pin function NC No connection
Continued on next page.
No. 5601-3/8
LC82151
Continued from preceding page.
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Pin TEST1 TEST0 TESTOUT VDD VSS ROSC1 ROSC2 BACKUP RESET AVDD AVSS AIN TEMP ATAP DAREFH DAREFL TXA RXA PGCO PGCI VREF VSS VDD SH RS ACLK1 ACLK2 ASAMP PXD7/PC7 PXD6/PC6 PXD5/PC5 PXD4/PC4 PXD3/PC3 PXD2/PC2 PXD1/PC1 PXD0/PC0 PDREQ/PF7 PDACK/PF6 EYED/PF5 VDD VSS
EYECLK/PF4
EYESYNC/PF3
I/O I I I P P I O I I P P I I O I I O I O I I P P O O O O O B B B B B B B B B B B P P B B B B B B B B B B B B B B Thermal head strobe signal/general-purpose port E Image data DMA request signal/general-purpose port F Image data output/general-purpose port C Power supply Ground RTC crystal oscillator connections Low power mode input System reset signal Analog system power supply Analog system ground Sensor signal input Thermistor input A/D converter reference voltage output D/A converter high-level reference voltage input D/A converter low-level reference voltage input Modem analog transmit output Modem analog receive input Modem gain adjustment output Modem gain adjustment input Modem analog block reference input Ground Power supply Image sensor start pulse Image sensor reset pulse Image sensor data transfer clocks Built-in A/D converter sampling point monitor signal Test pins
Pin function
Image data DMA acknowledge signal/general-purpose port F Eye pattern data output/general-purpose port F Power supply Ground Eye pattern data clock/general-purpose port F Eye pattern data synchronizing signal/general-purpose port F Timer outputs/general-purpose port F Thermal head data transfer clock/serial I/O clock/general-purpose port E Thermal head serial output data/serial I/O send data/general-purpose port E Thermal head control external clock/general-purpose port E Thermal head data latch signal/serial I/O receive data/general-purpose port E
TO1/PF2 TO0/PF1
PCK/SCLK/PE7 PDATA/TXD/PE6
EXCLK/PE5
LATCH/RXD/PE4
STB3/PE3 STB2/PE2 STB1/PE1 STB0/PE0 HVON/PF0
PROTECT/PG0
Head power on/off control signal/general-purpose port F Head protection abnormality indication signal input/general-purpose port G
Continued on next page.
No. 5601-4/8
LC82151
Continued from preceding page.
Pin No. 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin XTAL1 XTAL2 VSS VDD XOUT CLKIN A15 A14 A13 A12 A11 A10 A9 A8 TD/PD7 RD/PD6 RTS/PD5 CTS/PD4 DSR/PD3 DTR/PD2 VDD VSS RI/PD1 DCD/PD0 A7 A6 A5 A4 A3 A2 A1 A0 ABCNT BE o2 RES RWB IRQ VDD I/O I O P P O I B B B B B B B B B B B B B B P P B B B B B B B B B B O O O O I O P ICE bus control signal ICE bus enable signal ICE system clock ICE reset signal ICE read/write signal ICE interrupt request signal Power supply Address bus Serial port transmit data output/general-purpose port D Serial port receive data input/general-purpose port D Request to send signal/general-purpose port D Clear to send signal/general-purpose port D Data set ready/general-purpose port D Data terminal ready/general-purpose port D Power supply Ground Ring indicator/general-purpose port D Data carrier detect/general-purpose port D Address bus Pin function System clock crystal oscillator element connection (29.4912 MHz) Ground Power supply Crystal oscillator clock output System clock input
No. 5601-5/8
LC82151 Sample Application
NCU
Document Fluorescent lamp
Public telephone network
Telephone
Stepping motor Lens
Image sensor
Facsimile controller RAM
Motor driver
Temperature sensor
LC82151
ROM
Cutter Thermal head To LCD
Stepping motor Paper To key matrix
No. 5601-6/8
LC82151
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature Symbol VDD max VI, VO Pd max Topr Tstg Manual soldering (3 seconds) Reflow soldering (10 seconds) Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD +0.3 550 -30 to +70 -55 to +125 350 235 Unit V V mW C C C C
Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V
Parameter Supply voltage Input voltage Symbol VDD VIN Conditions Ratings min 4.5 0 typ max 5.5 VDD Unit V V
Electrical Characteristics at Ta = -30 to +70C, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input leakage current Output high-level voltage Output low-level voltage Output leakage current Charge pump output current Vref input voltage Vref impedance Input voltage range Operating voltage range Output impedance Oscillator frequency Symbol VIH1 VIL1 IL VOH VOL IOZ IPOZ INOZ VREF VREF VIA VOA RO fCLK1 fCLK2 IDD1 IDD2 IOH = -4mA IOL = 4mA When outputs are high impedance PHASEO = 2 V PHASEO = 2 V VREF VREF RXA, PGCI TXA, PGCO TXA, PGCO XTAL1, XTAL2, CLKIN ROSC1, ROSC 2 Operating In backup mode, VDD = 2.5 V, BACKUP = 0 29.4912 32.768 100 5 1 VDD x 0.2 VDD x 0.2 VDD x 0.8 VDD x 0.8 7.0 -10 7 -8 15 -15 VDD/2 -10 2.4 0.4 +10 27 -28 Conditions Ratings min 2.2 0.8 +10 typ max Unit V V A V V A mA mA V M V V k MHz kHz mA A
Current drain
Power on Timing Applications must control the timing of the power on sequence carefully. Although AVSS and VSS are completely isolated internally in the LC82151, AVDD and VDD are connected through the substrate. This means that there must be no potential difference between AVDD and VDD. Also, the power supply voltage rise and fall times must be under 3 ms. Analog Characteristic D/A Converter
Parameter Resolution Reference resistors value DAREFL, DAREFH Symbol Conditions Ratings min typ 6 5.0 max Unit bit k
A/D Converter at an ATAP potential of 4.2 V A/D Converter
Parameter Resolution Linearity error Differential linearity error Symbol Conditions Ratings min typ 8 1 1 max Unit bit LSB LSB
No. 5601-7/8
LC82151
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 1997. Specifications and information herein are subject to change without notice. No. 5601-8/8

▲Up To Search▲

Price & Availability of LC82151

	To Download LC82151 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .