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| 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs November 1993 Revised January 1999 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs General Description The ABT16952 is a 16-bit registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to source 32 mA and to sink 64 mA. Features s Separate clock, clock enable and 3-STATE output enable provided for each register s A and B output sink capability of 64 mA source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Order Number 74ABT16952CSSC 74ABT16952CMTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the letter suffix "X" to the ordering code. Pin Descriptions Pin Names A0-A15 B0-B15 CPABn, CPBAn CEAn, CEBn OEABn, OEBAn Description Data Register A Inputs/ B-Register 3-STATE Outputs Data Register B Inputs/ A-Register 3-STATE Outputs Clock Pulse Inputs Clock Enable Output Enable Inputs Connection Diagram Pin Assignment for SSOP Output Control OE H L L Internal Q X L H Output Z L H Function Disable Outputs Enable Outputs Register Function Table (Applies to A or B Register) Inputs D X L H CP CE H L L Internal Q NC L H Function Hold Data Load Data X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance = LOW-to-HIGH Transition NC = No Change (c) 1999 Fairchild Semiconductor Corporation DS011647.prf www.fairchildsemi.com 74ABT16952 Block Diagram n for either byte 1 or byte 2 www.fairchildsemi.com 2 74ABT16952 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to +5.5V -0.5V to VCC -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA -65C to +150C -55C to +125C -55C to +150C DC Latchup Source Current Over Voltage Latchup (I/O) -500 mA 10V Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100 mV/ns -40C to +85C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL VID IIH IBVI IBVIT IIL IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Test Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Output Leakage Current -1 -1 10 -10 -100 -275 50 100 1.0 60 1.0 2.5 No Load 0.18 mA/MHz Max A A mA A A mA mA mA mA A Max VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) 0V-5.5V VOUT = 2.7V (An, Bn); OEA or OEB = 2.0V Output Leakage Current 0V-5.5V VOUT = 0.5V (An, Bn); OEA or OEB = 2.0V Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC (Note 4) Max Max 0.0V Max Max Max Max VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs 3-STATE; All Others GND VI = VCC - 2.1V; All Others at VCC or GND Outputs Open OEA or OEB = GND, Non-I/O = GND or VCC One Bit toggling, 50% duty cycle (Note 3) Note 3: For 8-bit toggling, ICCD <1.4 mA/MHz. Note 4: Guaranteed, but not tested. Min 2.0 Typ Max 0.8 -1.2 Units V V V VCC Conditions Recognized HIGH Signal Recognized LOW Signal Min IIN = -18 mA (Non I/O Pins) IOH = -3 mA (An, Bn) IOH = -32 mA (An, Bn) 2.5 2.0 0.55 4.75 1 1 7 100 A A Max Max V A 0.0 Max IOL = 64 mA (An, Bn) IID = 1.9 A (Non-I/O Pins) All Other Pins Grounded VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, B n) 3 www.fairchildsemi.com 74ABT16952 AC Electrical Characteristics (SSOP Package) TA = +25C Symbol Parameter Min fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Max Clock Frequency Propagation Delay CPABn or CPBAn to An or Bn Output Enable Time OEABn or OEBAn to An or Bn Output Disable Time OEABn or OEBAn to An or Bn 1.5 1.5 6.0 6.0 1.5 1.5 6.0 6.0 ns 1.5 1.5 5.5 5.5 1.5 1.5 5.5 5.5 ns 1.5 1.5 5.3 5.3 1.5 1.5 5.3 5.3 ns 200 VCC = +5.0V CL = 50 pF Max TA = -40C to +85C VCC = 4.5V to 5.5V CL = 50 pF Min 200 Max MHz Units AC Operating Requirements TA = +25C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) Setup Time, HIGH or LOW An or Bn to CPABn or CPBAn Hold Time, HIGH or LOW An or Bn to CPABn or CPBAn Setup Time, HIGH or LOW CEAn or CEBn to CPABn or CPBAn tH(H) tH(L) Hold Time, HIGH or LOW CEAn or CEBn to CPABn or CPBAn tW(H) tW(L) Pulse Width, HIGH or LOW to CPABn or CPBAn 3.0 3.0 3.0 3.0 ns 1.5 1.5 1.5 1.5 ns 2.5 2.5 2.5 2.5 ns 1.5 1.5 1.5 1.5 ns 2.5 2.5 VCC = +5.0V CL = 50 pF Max Min 2.5 2.5 TA = -40C to +85C VCC = 4.5V to 5.5V CL = 50 pF Max ns Units Capacitance Symbol CIN CI/O (Note 5) Parameter Input Capacitance Output Capacitance Typ 5 11 Units pF pF Conditions TA = 25C VCC = 0V (Non I/O Pins) VCC = 5.0V (An, Bn) Note 5: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74ABT16952 AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns FIGURE 2. Test Input Signal Levels tr 2.5 ns tf 2.5 ns FIGURE 3. Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT16952 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A www.fairchildsemi.com 6 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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