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INTEGRATED CIRCUITS
DATA SHEET
TDA9177 YUV transient improvement processor
Product specification Supersedes data of 1996 Jun 28 File under Integrated Circuits, IC02 1997 Dec 01
Philips Semiconductors
Product specification
YUV transient improvement processor
FEATURES * Can be used in 1fH and 2fH applications * Luminance step improvement * Line width control * Smart peaking for detail enhancement * Embedded feature reduction facility for smart noise control * Compensating chrominance delay * YUV interface * Two additional pins for access to 6-bit ADC and I2C-bus * Versatile I2C-bus and pin control for user adjustments. GENERAL DESCRIPTION The TDA9177 is an I2C-bus controlled sharpness improvement IC with additional inputs for 6-bit analog-to-digital conversion to facilitate additional parameter measurement (e.g. ambient light control). It should preferably be used in front of an RGB video signal processor with YUV interface. QUICK REFERENCE DATA SYMBOL VCC Vi(Y) Vi(UV) VFS(ADC) Vref PARAMETER supply voltage luminance input voltage UV input voltage full scale ADC input voltage reference voltage AMS = LOW AMS = HIGH CONDITIONS MIN. 7.2 - - - - 3.90 TYP. 8.0 0.315 1.0 - 4.05
TDA9177
In combination with the TDA9170, it builds a high performance and intelligent picture improvement solution. The sharpness processor provides 1D luminance step improvement and detail enhancement by smart peaking, suitable for both 1fH and 2fH applications. The TDA9177 can be used as a cost effective alternative to (but also in combination with) Scan Velocity Modulation (SVM). An on-board 6-bit Analog-to-Digital Converter (ADC) can be used for interfacing two analog, low frequency voltage signals to the I2C-bus. The supply voltage is 8 V. The TDA9177 is mounted in a 24-pin SDIP envelope.
MAX. 8.8 0.42 1.33 1.9 4.20
UNIT V V V V V V
0.5Vref -
ORDERING INFORMATION TYPE NUMBER TDA9177 PACKAGE NAME SDIP24 DESCRIPTION plastic shrink dual in-line package; 24 leads (400 mil) VERSION SOT234-1
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Philips Semiconductors
Product specification
YUV transient improvement processor
BLOCK DIAGRAM
TDA9177
handbook, full pagewidth
AMS 14
CFS 8
FHS 17
SDA SCL 13 12
ADR 6
ADEXT1 ADEXT2 3 10
22 STEEP LWC COR PEAK 4 2 11 PIN-TO-I2C-BUS INTERFACE I2C-BUS CONTROLLER 6-BIT ADC line width steepness coring peaking
TDA9177
SANDCASTLE input
1
SANDCASTLE DETECTOR
STEP IMPROVEMENT PROCESSOR SMART SHARPNESS CONTROLLER
20
YOUT
contour filter selection 5 YIN BLACK INSERTION CLAMP DELAY CLAMPS CONTOUR PROCESSOR
15 SNC amplitude selection DELAY DELAY IPTAT BANDGAP
23
Vref
7 UIN
18
9
16 VOUT
24 Rext
line frequency selection
21 VCC
19 GND
MBH229
VIN UOUT
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
YUV transient improvement processor
PINNING SYMBOL SANDCASTLE COR ADEXT1 LWC YIN ADR UIN CFS VIN ADEXT2 PEAK SCL SDA AMS SNC VOUT FHS UOUT GND YOUT VCC STEEP Vref Rext PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION sandcastle input coring level input ADC input 1 line width control input luminance input I2C-bus address input colour U input contour filter select input colour V input ADC input 2 peaking amplitude input serial clock input (I2C-bus) serial data input/output (I2C-bus) amplitude select input smart noise control input colour V output line frequency select input colour U output system ground luminance output supply voltage steepness control input reference voltage output resistor reference Fig.2 Pin configuration.
ADEXT2 10 PEAK 11 SCL 12
MBH228
TDA9177
handbook, halfpage
SANDCASTLE COR ADEXT1 LWC YIN ADR UIN CFS VIN
1 2 3 4 5 6
24 Rext 23 Vref 22 STEEP 21 VCC 20 YOUT 19 GND
TDA9177
7 8 9 18 UOUT 17 FHS 16 VOUT 15 SNC 14 AMS 13 SDA
1997 Dec 01
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Philips Semiconductors
Product specification
YUV transient improvement processor
FUNCTIONAL DESCRIPTION Y-input selection and amplification The dynamic range of the luminance input amplifier and output amplifier can be switched between 0.315 V and 1.0 V typically (excluding sync), either externally (pin AMS) or by I2C-bus (bit AMS of the control register). Amplitudes outside the corresponding maximum specified range will be clipped smoothly. The sync part is processed transparently to the output, independently of the feature settings. The input is clamped during the HIGH period of the CLP, defined by the sandcastle reference, and should be DC-decoupled with an external capacitor. During the clamp pulse, an artificial black level is inserted in the input signal to correctly preset the internal circuitry. The input amplifier drives a delay line of four delay sections, which form the core of the sharpness improvement processor. Sharpness improvement processor The sharpness improvement processor increases the slope of large luminance transients of vertical objects and enhances transients of details in natural scenes by contour correction. It comprises three main processing units, these being the step improvement processor, the contour processor and the smart sharpness controller. STEP IMPROVEMENT PROCESSOR The step improvement processor (see Fig.9) comprises two main functions: 1. the MINMAX generator 2. the MINMAX fader. The MINMAX generator utilizes 5 taps of an embedded luminance delay line to calculate the minimum and maximum envelope of all signals momentarily stored in the delay line. The MINMAX fader chooses between the minimum and maximum envelopes, depending on the polarity of a decision signal derived from the contour processor. Figures 4, 5 and 6 show some waveforms of the step improvement processor and illustrate that fast transients result with this algorithm. The MINMAX generator also outputs a signal that represents the momentary envelope of the luminance input signal. This envelope information is used by the smart sharpness controller. Limited line width control (also called aperture control) can be performed externally (pin 4, LWC) or by I2C-bus (LW-DAC). Line width control can be used to compensate
TDA9177
for horizontal geometry because of the gamma or blooming of the spot of the CRT. THE CONTOUR PROCESSOR The contour processor comprises two contour generators with different frequency characteristics. The contour generator generates a second-order derivative of the incoming luminance signal and is used both as a decision signal for the step improvement processor and as a luminance correction signal for the smart sharpness controller. In the smart sharpness controller, this correction signal is added to the proper delayed original luminance input signal, making up the peaking signal for detail enhancement. The peaking path is allowed to select either the narrow- or wide-peaked contour generators either externally (pin 8, CFS) or by I2C-bus (bit CFS in the control register). The step improvement circuitry always selects the wide-peaked contour filter. The contour generators utilize 3 taps (narrow band) or 5 taps (broad band) of the embedded luminance delay lines. Figures 11 and 12 illustrate the normalized frequency transfer of both the narrow and wide contour filters. SMART SHARPNESS CONTROLLER The smart sharpness controller (see Fig.10) is a fader circuit that fades between peaked luminance and step-improved luminance, defined by the output of a step discriminating device known as the step detector. It also contains a variable coring level stage. The step detector behaves like a band-pass filter, so both amplitude of the step and its slope add to the detection criterion. The smart sharpness controller has four user controls: 1. Steepness control 2. Peaking control 3. Coring level control 4. Smart Noise control. Control settings can be performed either by the I2C-bus or externally by pin, depending on the status of the I2C-bus bit STB. The steepness setting controls the amount of steepness in the edge-correction processing path. The peaking setting controls the amount of contour correction for proper detail enhancement.
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Philips Semiconductors
Product specification
YUV transient improvement processor
The envelope signal generated by the step improvement processor modulates the peaking setting in order to reduce the amount of peaking for large sine excursions see Figs 7 and 8. The coring setting controls the coring level in the peaking path for rejection of high-frequency noise. All three settings facilitate reduction of the impact of the sharpness features, e.g. for noisy luminance signals. An external noise detector and a user-preferred noise algorithm are needed to make a fully automatic I2C-bus controlled smart sharpness control. An on-board, hard-wired smart sharpness algorithm can be executed by driving pin SNC with the output of an external noise detector. This pin, however, is active both in I2C-bus and pin mode. Figures 13 and 14 illustrate the impact of the noise control voltage at pin SNC on the user settings. Figure 15 shows the relationship between the feature settings STEEP, COR, PEAK, LWC and their corresponding pin voltages. Chrominance compensation The chrominance delay lines compensate for the delay of the luminance signal in the step improvement processor, to ensure a correct colour fit. No delay compensation will be performed in the chrominance path for line-width corrections in the luminance path. Successive approximation ADC Pins ADEXT1 and ADEXT2 are connected to a 6-bit successive approximation ADC, via a multiplexer. The multiplexer toggles between the inputs with each field. For each field flyback, a conversion is started for either of the two inputs and the result is stored in the corresponding bus register, ADEXT1 or ADEXT2. In this way, any analog, slowly varying signal can be given access to the I2C-bus. If a register access conflict occurs, the data of that register is made invalid by setting the flag bit DV (Data Valid) to zero. Slave address A6 ADR A5 1 A4 ADR A3 0 A2 0 I2C-bus
TDA9177
At power up, the bit STB (standby) in the control register is reset, to leave control to the pins. However, the I2C-bus is at standby and responds if properly addressed. By setting STB to logic 1, the control of all features is instead left to the I2C-bus registers. The PDD bit (Power Down Detected) in the status register is set each time an interruption of the supply power occurs and is reset only by reading the status register. A 3-bit identification code can also be read from the status register, which can be used to automatically configure the application by software. The input control registers can be written sequentially by the I2C-bus by the embedded automatic subaddress increment feature or by addressing it directly. The output control functions cannot be addressed separately. Reading out the output control functions always starts at subaddress 00 and all subsequent words are read out by the automatic subaddress increment procedure. The I2C address is 40H if pin 6 (ADR) is connected to ground and E0H if pin 6 (ADR) is connected to pin 23 (Vref). I2C-bus specification
A1 0
A0 0
R/W X
Auto-increment mode available for subaddresses.
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Philips Semiconductors
Product specification
YUV transient improvement processor
Control functions DATA BYTE FUNCTIONS Inputs Control Peaking Steepness Coring Line width Outputs Status ADEXT1 (output) ADEXT2 (output) REG REG REG 00 01 02 0 0 0 0 DV DV 0 AD5 AD5 0 AD4 AD4 ID2 AD3 AD3 REG DAC DAC DAC DAC 00 01 02 03 04 X X X X X X X X X X X PK5 SP5 CR5 LW5 X PK4 SP4 CR4 LW4 CFS PK3 SP3 CR3 LW3 TYPE SUBADDRESS D7 D6 D5 D4 D3
TDA9177
D2
D1
D0
FHS PK2 SP2 CR2 LW2
AMS PK1 SP1 CR1 LW1
STB PK0 SP0 CR0 LW0
ID1 AD2 AD2
ID0 AD1 AD1
PDD AD0 AD0
INPUT SIGNALS Table 1 Address selection FUNCTION I2C address is 40H I2C address is E0H Standby FUNCTION pin mode I2C-bus mode
Table 6
Peaking amplitude FUNCTION 0% 100%
PK5 to PK0 000000 111111 Table 7
ADR 0 1 Table 2
Steepness correction FUNCTION 0% 100%
SP5 to SP0 000000 111111 Table 8
STB 0 1 Table 3
Coring level FUNCTION 0% 100%
Amplitude selection FUNCTION 0.315 V luminance 1.0 V luminance Line frequency selection FUNCTION 1fH 2fH Contour filter selection FUNCTION narrow contour filter wide contour filter
CR5 to CR0 000000 111111 Table 9
AMS 0 1 Table 4
Line width correction FUNCTION 0% 100%
LW5 to LW0 000000 111111
FHS 0 1 Table 5 CFS 0 1
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Philips Semiconductors
Product specification
YUV transient improvement processor
OUTPUT SIGNALS Table 10 Power Down Detection (PDD) PDD 0 1 FUNCTION no power down detected since last read action power down detected Table 12 Data valid of ADC registers DV 0 1
TDA9177
FUNCTION data not valid because of possible register access collision data valid
Table 13 Bits AD5 to AD0 AD5 to AD0 000000B 111111B 0V 0.5Vref FUNCTION
Table 11 Identification (version number or derivative type) ID2 to ID0 000 TDA9177/N1 FUNCTION
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC Vi Vo Tstg Tamb supply voltage input voltage on any input output voltage of any output storage temperature operating ambient temperature PARAMETER CONDITIONS MIN. -0.5 -0.5 -0.5 -55 -10 MAX. +8.8 V VCC + 0.5 V VCC + 0.5 V +150 +70 C C UNIT
QUALITY SPECIFICATION Quality level in accordance with "SNW-FQ-611 part E". All pins are protected against ESD by means of internal clamping diodes. The protection circuit meets the specification: Human body model (100 pF, 1500 ): All pins >3000 V. Machine model (200 pF, 0 ): All pins >300 V. Latch-up: At an ambient temperature of 70 C, all pins meet the specification: Itrigger > 100 mA or Vpin > 1.5VCC(max) Itrigger < -100 mA or Vpin < -0.5VCC(max) THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE <59 UNIT K/W
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Philips Semiconductors
Product specification
YUV transient improvement processor
CHARACTERISTICS VCC = 8 V; Rref = 10 k 2%; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies MAIN SUPPLY VCC (PIN 21) VCC ICC supply voltage supply current 1fH mode 2fH mode REFERENCE SUPPLY Vref (PIN 23) Vref IL(max) VRref Rref reference supply voltage maximum load current 3.90 1.0 - - 4.05 - 2 10 7.2 - - 8.0 40 45 PARAMETER CONDITIONS MIN. TYP.
TDA9177
MAX.
UNIT
8.8 - - 4.20 - - -
V mA mA
V mA
RESISTOR REFERENCE Rext (PIN 24) resistor supply voltage resistor value V k
Luminance input/output selection LUMINANCE INPUT YIN (PIN 5) Vi(Y) Vi(Yclamp) Iib(Y) VAMSL VAMSH luminance input voltage luminance input voltage level during clamping luminance input bias current no clamp AMS = LOW AMS = HIGH - - - - - 3.5 0.315 1.0 4.0 - - - 0.42 1.33 - 0.1 V V V A V V
LUMINANCE INPUT VOLTAGE RANGE SELECTION AMS (PIN 14); note 1 input voltage for low luminance range input voltage for high luminance range 0.5 5.5
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - 52 5 10 - - - 1.3
TYP.
MAX. - - - - - - - 1.0 5 150 -
UNIT
LUMINANCE OUTPUT YOUT (PIN 20) Vo(Y) (p-p) Vo(Yclamp) S/N(Y) BY luminance output voltage, peak-to-peak luminance output voltage during clamping luminance output signal-to-noise ratio luminance bandwidth 1fH mode (-1 dB); transparent; note 2 2fH mode (-1 dB); transparent; note 2 Ebl EG(n) Rout Iob black level error nominal gain error output resistance output bias current transparent; note 3 transparent AMS = LOW AMS = HIGH AMS = LOW AMS = HIGH 0.315 1.0 2.35 2 - - - 0 0 - - V V V V dB MHz MHz % % mA
Step improvement GENERAL tr(min) minimum rise time 10% to 90% 1fH mode; note 4 2fH mode; note 4 LINE WIDTH CONTROL (min) (max) tsd(max) minimum duty factor maximum duty factor maximum step displacement 2 MHz 2 MHz 1fH mode 2fH mode LINE-WIDTH CONTROL LWC (PIN 4); note 1 Vi(min) Vi(max) Ibias input voltage for minimum line width input voltage for maximum line width input bias current - 87.5 - - - 0.5 37.5 137.5 - %Vref %Vref A - - - - 33 67 140 70 - - - - % % ns ns - - 20 20 - - ns ns
Contour processing CONTOUR FILTER NARROW-PEAKED fpc peaking centre frequency 1fH 2fH CONTOUR FILTER WIDE-PEAKED fpc1 Qmax peaking centre frequency maximum contour amplitude at centre frequency 1fH 2fH note 5 - - - 4.14 8.28 12 - - - MHz MHz dB - - 3.57 7.14 - - MHz MHz
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
SYMBOL
PARAMETER
CONDITIONS
MIN. - 3.5
TYP. - -
MAX.
UNIT
CONTOUR FILTER SELECTION CFS (PIN 8); note 1 Vi(ncf) Vi(wcf) input voltage for narrow contour filter input voltage for wide contour filter 0.5 5.5 V V
Smart sharpness controller STEP DETECTOR fdc CORING QsmcL QsmcH Vi(min) Vi(max) Ibias Vi(min) Vi(max) Ibias Vi(min) Vi(max) Ibias Vnfr Vcfr Ibias td tde tde1 tde2 minimum coring level maximum coring level note 6 note 6 - - - 87.5 - - 87.5 - - 87.5 - - - - - - - - - - 0 22 - - - - - - - - - 0.0 Vref - - - 37.5 137.5 0.5 % % detection centre frequency 1fH 2fH - - 2.13 4.26 - - MHz MHz
CORING LEVEL CONTROL COR (PIN 2); note 1 input voltage for minimum coring input voltage for maximum coring input bias current %Vref %Vref A %Vref %Vref A %Vref %Vref A V V A
PEAKING LEVEL CONTROL PEAK (PIN 11); note 1 input voltage for minimum peaking input voltage for maximum peaking input bias current 37.5 137.5 0.5
STEEPNESS LEVEL CONTROL STEEP (PIN 22); note 1 input voltage for minimum steepness input voltage for maximum steepness input bias current 37.5 137.5 0.5 - - 1.0 - - 10 5 10 5
SMART NOISE CONTROL SNC (PIN 15) level for no feature reduction level for complete feature reduction input bias current
Overall group delay performance for luminance delay time from input to output delay error contour correction delay error step correction delay error step correction 1fH mode 2fH mode 1fH mode; note 7 2fH mode; note 7 1fH mode; note 7 2fH mode 175 108 0 0 0 0 ns ns ns ns ns ns
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
SYMBOL
PARAMETER
CONDITIONS
MIN. - 3.5
TYP. - -
MAX.
UNIT
DELAY TIME SELECTION FHS (PIN 17); note 1 Vi1fH Vi2fH input voltage for 1fH input voltage for 2fH 0.5 5.5 V V
Colour difference processing COLOUR DIFFERENCE INPUTS UIN AND VIN (PINS 7 AND 9) ViUIN(p-p) ViVIN(p-p) Ibias Vcl Vo(cl) G Eoff EG EG(UV) B td Rout Iob input voltage range UIN, peak-to-peak input voltage range VIN, peak-to-peak input bias current UIN, VIN voltage level during clamping no clamp 1.9 1.9 - - - - transparent transparent transparent 1fH 2fH delay time output resistance output bias current 1fH 2fH - - - 7 7 - - - 0.5 - - - 4.0 - - 0.1 - - - 1 5 1 - - - - 150 - % % % MHz MHz ns ns mA V V A V
COLOUR DIFFERENCE OUTPUTS UOUT AND, VOUT (PINS 18 AND 16) output voltage level during clamping gain offset error gain error UV gain tracking error bandwidth 3.2 1.0 0 0 0 - - 175 108 - - V
Successive Approximation ADC ADEXT1 AND ADEXT2 (PINS 3 AND 10) VFS Iib DLE ILE fcon Qadt full scale input voltage range input bias current data path differential linearity error integral linearity error conversion frequency conversion time (video lines) each channel each channel with respect to GND - - - - - - - 2.0 - 6 - - 0.5fV 8 - 1 - 1 1 - - V A bit LSB LSB Hz lines
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
SYMBOL Timing
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SANDCASTLE INPUT SANDCASTLE (PIN 1) Vscbn Vscbc tscnV tscV Vbkvar tdm(YUV) Notes 1. This selection is only valid when the standby bit STB is not set. 2. In transparent mode i.e. no step improvement and no peaking, the bandwidth of the luminance path for which the group delay is constant is 7 MHz in 1fH mode and 14 MHz in 2fH mode. However, as the circuit uses all-pass filters, ringing on the output signal may occur if the bandwidth of the input signal is larger than 7 MHz in 1fH mode or 14 MHz in 2fH mode. As the step improvement circuit adds harmonics to the luminance signal, the bandwidth of the output signal is much larger than 14 MHz. 3. The black level error that may occur will mainly be caused by inaccuracies in the internal clamping circuit. This internal clamping circuit is activated during 70% of the duration of the burst key pulse on the sandcastle signal. Integration of the `ramp shaped' black level error during the full duration of the burst key pulse will reduce the black level error to less than 1%. 4. Peaking set to minimum. Input signal is a sine wave with the nominal peak-to-peak amplitude corresponding to the selected input range. 5. The contour signal cannot be measured separately from the luminance input signal. The contour signal is also processed by the smart noise controller. The frequency transfer in the peaking mode of the luminance signal can be derived from the frequency transfer of the selected contour signal, taking into account the summation of the contour signal and the luminance input signal. The frequency transfer is most easily measured by sine excitation with a relatively small signal amplitude of 10% of the selected dynamic range of the luminance input, to avoid interaction with the step detector. 6. The coring level refers to the internally selected contour signal. It is dependent on the contour filter selected and is specified for the corresponding peaking centre frequency. The coring level can not be measured explicitly at the luminance output from a big step or sine excitation, because of its interaction with the step detector. 7. Contour correction and step improvement delays are internal delays and cannot be measured in a straightforward way. Contour correction delay mismatch results in asymmetrical `ears' with respect to the centre of the transient. Step improvement correction delay mismatch affects the symmetry of the line width control. detection level for blank detection level for blank input blanking width for no V-sync input blanking width for V-sync ripple on sandcastle burst key level no clamping with clamping and w.r.t. top level sandcastle pulse 1.25 - - 35 - - - 1.5 -0.6 - - - 1.75 - 15 - 0.4 V V s s V
Overall output group delay performance delay of matching YUV 1fH 2fH 0 0 10 5 ns ns
1997 Dec 01
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Philips Semiconductors
Product specification
YUV transient improvement processor
Figures 3 to 8 show the excitation and response of the TDA9177 sharpness improvement processor. The excitation shown in Fig.3 is a 2T-pulse, followed by a step function. Because the TDA9177 can handle both 1fH and 2fH signals, figures illustrating both situations could have been provided. However, as the difference between these two modes (with respect to the TDA9177) is that the time scale of a 2fH response diagram is half that of a 1fH response diagram under equal conditions, only the 1fH figures are shown. Figure 4 shows that the step improvement processor does not affect small amplitudes. Large transients, however, acquire steeper edges.
TDA9177
Figures 5 and 6 show that the width of the signal processed by the step improvement processor can be modified by the Line Width Control pin LWC (or DACLW). Figure 7 shows that the contour processor does not affect large transients, but works exclusively on small signals, e.g. details in a video signal. Figure 8 shows the combination of smart peaking and the step improvement processor; small signals will be affected by the contour processor, while large transients will be modified by the step improvement processor.
1997 Dec 01
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, halfpage
1000 input signal (mV) 800
MBH230
handbook, halfpage
(1)
1000 Vo (mV) 800
MBH231
(1)
600
600
400
400
200
(2)
200
(2)
0 0 0.5 1.0 1.5 t (s) 2.0
0 0 0.5 1.0 1.5 t (s) 2.0
(1) 90% of nominal amplitude. (2) 30% of nominal amplitude.
(1) 90% of nominal amplitude. (2) 30% of nominal amplitude.
Fig.4 Fig.3 Excitation signals: 90% and 30% of nominal amplitude 2T-pulse and step function.
Response signals for maximum step improvement, no peaking and nominal line width.
handbook, halfpage
(1)
1000 Vo (mV) 800
MBH232
handbook, halfpage
(1)
1000 Vo (mV) 800
MBH233
600
600
400
400
200
(2)
200
(2)
0 0 0.5 1.0 1.5 t (s) 2.0
0 0 0.5 1.0 1.5 t (s) 2.0
(1) 90% of nominal amplitude. (2) 30% of nominal amplitude.
(1) 90% of nominal amplitude. (2) 30% of nominal amplitude.
Fig.5
Response signals for maximum step improvement, no peaking and minimum line width.
Fig.6
Response signals for maximum step improvement, no peaking and maximum line width.
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, halfpage
1400
MBH234
handbook, halfpage
1400
MBH235
Vo (mV) 1000
Vo (mV) 1000
(1)
(1)
600
600
200
(2)
200
(2)
-200
-200 0 0.5 1.0 1.5 t (s) 2.0
0
0.5
1.0
1.5 t (s)
2.0
(1) 90% of nominal amplitude. (2) 30% of nominal amplitude.
(1) 90% of nominal amplitude. (2) 30% of nominal amplitude.
Fig.8 Fig.7 Response signals for no step improvement, maximum peaking and 0% coring.
Response signals for maximum step improvement, nominal line width, maximum peaking and 0% coring.
handbook, full pagewidth
line width control
MINMAX SELECTOR
FADER
YSTEP
YIN
DELAY
CLAMPS
MINMAX Yenvelope
MBH236
Fig.9 Block diagram of the step improvement processor.
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, full pagewidth
delay cells coring control
STEP DETECTOR Yenvelope
Ycontour
CORING
Yc
FADER
YSTEP
YSTEP
peaking steepness control control smart noise
MBH237
Fig.10 Block diagram of the smart sharpness controller.
MBH238
handbook, full pagewidth
100
contour (%) 80
60
40
(1) (2)
20
0 104 (1) 1fH mode. (2) 2fH mode.
105
106
107
f (Hz)
108
Fig.11 Frequency transfers narrow contour filter.
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
MBH239
handbook, full pagewidth
100
contour (%) 80
60
40
(1) (2)
20
0 104
105
106
107
f (Hz)
108
(1) 1fH mode. (2) 2fH mode.
Fig.12 Frequency transfers wide contour filter.
handbook, halfpage
100
MBH240
(%)
75
50
25
0 0 25 50 75 Vref (%) 100
Fig.13 Relative decrease of steepness level as a function of voltage at pin SNC starting from four different steepness level presets.
1997 Dec 01
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, halfpage
100
MBH241
(%) 80
60
40
20
0 0 25 50 75 Vref (%) 100
Fig.14 Relative increase of coring level as a function of voltage at pin SNC starting from four different coring level presets.
handbook, halfpage
100
MBH242
transfer (%)
50
0 37.5
50.0
62.5
75
Vref (%)
87.5
Fig.15 Feature setting control as a function of the pin voltage for peaking, coring, steepness and line width.
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Philips Semiconductors
Product specification
YUV transient improvement processor
INTERNAL CIRCUITRY
TDA9177
handbook, halfpage
handbook, halfpage
275 1 SANDCASTLE
COR 2
275
MBH245
MBH244
Fig.16 Simplified circuit diagram pin 1.
Fig.17 Simplified circuit diagram pin 2.
handbook, halfpage
handbook, halfpage
275 275 ADEXT1 3 100 k LWC 4
MBH247 MBH246
Fig.18 Simplified circuit diagram pin 3.
Fig.19 Simplified circuit diagram pin 4.
handbook, halfpage
handbook, halfpage
275 YIN 5
275 ADR 6
MBH248
MBH249
Fig.20 Simplified circuit diagram pin 5.
Fig.21 Simplified circuit diagram pin 6.
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Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, halfpage
handbook, halfpage
275 UIN 7 275 CFS 8
275
900
1 M
MBH250
MBH251
Fig.22 Simplified circuit diagram pin 7.
Fig.23 Simplified circuit diagram pin 8.
handbook, halfpage
handbook, halfpage
275 VIN 9 275 275 ADEXT2 10 900 100 k
MBH252
MBH253
Fig.24 Simplified circuit diagram pin 9.
Fig.25 Simplified circuit diagram pin 10.
ndbook, halfpage
handbook, halfpage
275 PEAK 11
SCL 12
275
MBH254
MBH255
Fig.26 Simplified circuit diagram pin 11.
Fig.27 Simplified circuit diagram pin 12.
1997 Dec 01
21
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, halfpage handbook, halfpage
275 SDA 13
275 AMS 14
900
1 M
MBH257 MBH256
Fig.28 Simplified circuit diagram pin 13.
Fig.29 Simplified circuit diagram pin 14.
handbook, halfpage
handbook, halfpage
275 SNC 15 0.5 mA
MBH258
100 16 VOUT
MBH259
Fig.30 Simplified circuit diagram pin 15.
Fig.31 Simplified circuit diagram pin 16.
handbook, halfpage
handbook, halfpage
275 FHS 17
900
100 18 UOUT 1 M 0.5 mA
MBH260 MBH261
Fig.32 Simplified circuit diagram pin 17.
Fig.33 Simplified circuit diagram pin 18.
1997 Dec 01
22
Philips Semiconductors
Product specification
YUV transient improvement processor
TDA9177
handbook, halfpage
handbook, halfpage
GND
19
MBH262
100 20 YOUT 0.5 mA
MBH263
Fig.34 Simplified circuit diagram pin 19.
Fig.35 Simplified circuit diagram pin 20.
handbook, halfpage handbook, halfpage
275 STEEP VCC 21 22
MBH264 MBH265
Fig.36 Simplified circuit diagram pin 21.
Fig.37 Simplified circuit diagram pin 22.
handbook, halfpage
handbook, halfpage
100 100 23 Vref 100
24 Rext
21 k
MBH266 MBH267
Fig.38 Simplified circuit diagram pin 23.
Fig.39 Simplified circuit diagram pin 24.
1997 Dec 01
23
Philips Semiconductors
Product specification
YUV transient improvement processor
APPLICATION INFORMATION To benefit optimally from its picture-sharpening capabilities, the TDA9177 should be positioned as the last part of the YUV-chain. Feature reduction as a function of the noise contents of the picture can easily be realized in hardware by using a Noise Detector. Smart Noise Control (SNC) can be tailor-made for each application, by means of controlling the peaking and the steepness values by software (I2C-bus control).
TDA9177
Whenever I2C-bus control is not feasible, the embedded smart sharpness algorithm can be executed by driving pin SNC with the output of a noise detector. In this concept, additional post-processing of the noise detector output can easily be realized with external components. Figure 40 shows an application example in which the TDA9177 is bus controlled, with the I2C-bus address at 40H. Furthermore, the Smart Noise Control pin (SNC; pin 15) is not used in the example shown.
handbook, full pagewidth
YOUT 8V 100 nF 0V 10 k 24 23 22 21 20 19 100 F
UOUT
VOUT
18
17
16
15
14
13
TDA9177
1 2 3 4 5 6 7 8 9 10 11 12
100 nF
10 nF
10 nF
100
100
sandcastle
YIN
UIN
VIN
SCL
SDA
MBH243
Fig.40 Application diagram.
1997 Dec 01
24
Philips Semiconductors
Product specification
YUV transient improvement processor
PACKAGE OUTLINE SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
TDA9177
SOT234-1
D seating plane
ME
A2
A
L
A1 c Z e b 24 13 b1 wM (e 1) MH
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT234-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 22.3 21.4 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
ISSUE DATE 92-11-17 95-02-04
1997 Dec 01
25
Philips Semiconductors
Product specification
YUV transient improvement processor
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.
TDA9177
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
1997 Dec 01
26
Philips Semiconductors
Product specification
YUV transient improvement processor
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9177
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Dec 01
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/02/pp28
Date of release: 1997 Dec 01
Document order number:
9397 750 03053

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