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SERCON410B
DATASHEET
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.
SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein : 1. Life support devices or systems are those which (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided with the product, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
SERCON410B DATASHEET INDEX
Page Number
SERCON410B
....................................
1 5
6 9 9 9 9 11 11 11 12 12 13 14 15 16 17 17 23 23 25 26 26 29 29 29 29
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 RECOMMENDED OPERATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Clock Input MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Clock Input SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Read Access of Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 Read Access of Dual Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Write Access to Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 Write Access to Dual Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 4 CONTROL REGISTERS AND RAM DATA STRUCTURES . . . . . . . . . . . . . . . . . . . . 4.1 CONTROL REGISTER ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 DATA STRUCTURES WITHIN THE RAM . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Telegram Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Data Containers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 End Marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Service Containers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ADDITIONAL SUPPORT AND TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 SERCOS INTERFACE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 SOFTWARE AND BOARDS FOR THE SERCON410B . . . . . . . . . . . . . . . . . .
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SERCON410B
NOTES:
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SERCON410B
SERCOS INTERFACE CONTROLLER
PRELIMINARY DATA
Single-chip controller for SERCOS interface Real time communication for industrial control systems 8/16-bit bus interface, Intel and Motorola control signals Dual port RAM with 1024 words * 16-bit Data communications via optical fiber rings, RS 485 rings and RS 485 busses Maximum transmission rate of 4 Mbaud with internal clock recovery Maximum transmission rate of 10 Mbaud with external clock recovery Internal repeater for ring connections Full duplex operation Modulation of power of optical transmitter diode Automatic transmission of synchronous and data telegrams in the communication cycle Flexible RAM configuration, communication data stored in RAM (single or double buffer) or transfer via DMA Synchronization by external signal Timing control signals Automatic service channel transmission 100-pin plastic flat-pack casing
PQFP100 (Ordering Number: SERGBQA)
May 1994
This is Preliminary Data from SGS-THOMSON. Details are subject to change without notice.
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Figure 1. SERCON410B Block Diagram
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SERCON410B
Figure 2. SERCON410B Pin Configuration
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SERCON410B
Figure 3. SERCOS Interface with Ring Connection
Figure 4. SERCON410B with RS-485 bus Connection
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SERCON410B
1 GENERAL DESCRIPTION The SERCOS interface controller SERCON410B is an integrated circuit for SERCOS interface communication systems. The SERCOS interface is a digital interface for communication between systems which have to exchange information cyclically at short, fixed intervals (65 s to 65 ms). It is appropriate for the synchronous operation of distributed control or test equipment (e.g. connection between drives and numeric control). A SERCOS interface communication system consists of one master and several slaves (Fig. 3). These units are connected by a fiber optical ring. This ring starts and ends at the master. The slaves regenerate and repeat their received data or send their own telegrams. By this method the telegrams sent by the master are received by all slaves while the master receives data telegrams from the slaves. The optical fiber assures a reliable highspeed data transmission with excellent noise immunity. The SERCOS interface controller contains all the hardware-related functions of the SERCOS interface and considerably reduces the hardware costs and the computing time requirements of the microprocessor. It is the direct link between the electro-optical receiver and transmitter and the microprocessor that executes the control algorithms. The SERCON410B can be used both for SERCOS interface masters and slaves.
The circuit contains the following functions (Fig. 1): Interface to microprocessor with a data - bus width of 8the 16 bits and with control lines or according to Intel or Motorola standards. a - A serial interface for makinganddirect connection with the optical receiver transmitter of the fiber optic ring or with drivers to an electric ring or bus. Data and clock regeneration, the repeater for ring topologies and the serial transmitter and receiver are integrated. The signals are monitored and test signals generated. The serial interface operates up to 4Mbaud without external circuitry and up to 10 Mbaud with external clock regeneration. (1024 * 16 bit) for control - A dual port RAMdata. The organization of and communication the memory is flexible. processing - Telegram monitoring offor automatic transmission and synchronous and data telegrams. Only transmission data which is intended for the particular interface user is processed. The transmitted data is either stored in the internal RAM (single or double buffer) or transferred via direct memory access (DMA). The transmission of service channel information over several communication cycles is executed automatically. In addition to the SERCOS interface the SERCON410B can also be used for other real-time communications tasks. As an alternative to the fiberoptical ring also bus topologies with RS-485 signals are supported (Fig. 4). The SERCON410B is therefore suitable for a wide range of applications.
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2 PIN DESCRIPTION Table 1. SERCON410B I/O Port Function Summary
Signal (s) Pin (s) 77-80, 82-85, 87-90, 92-95 56-59, 61-64, 66-69, 71-74 IO Function Data bus: for 8-bit-wide bus interfaces, data is written to and read via D7-0, for 16-bit-wide bus interfaces via D15-0. When ADMUX is 1, the address which is stored in the address latch with ALEL and ALEH is input via D15-0. Address bus: when ADMUX is 0 the pins are inputs, when ADMUX is 1, they are outputs for the address stored with ALEL (A7-0) and ALEH (A15-8). In the 8-bit bus mode, A0 distinguishes which byte is transmitted via D7-0 (depends on BYTEDIR). In the 16-bit bus mode, data is tansferred via D7-0 only when A0 is 0. A10-1 selects the words of the internal RAM; A61the control registers. Address latch enable, low and high, active high: they are only used when ADMUX is 1. When ALEL/ALEH is 1, the signals go from the data bus to the address bus, when ALEL/ALEH = 0, they store the address. When ADMUX is 0, ALEL/ALEH have to be connected to VDD . Read: for the Intel bus interface, data is read when RDN is 0. For the Motorola bus interface, data is read or written to when RDN is 0 (BUSMODE1 = 0) or RDN is 1 (BUSMODE1 = 1). Write: for the Intel bus interface, data is written to when WRN is 0. For the Motorola bus interface, WRN selects read (WRN = 1) and write (WRN = 0) operations of the data bus. Byte high enable, active low: in the 16-bit bus mode, data is transferred via D15-8 when BHEN is 0. Memory chip select, active low: to access the internal RAM MCSN0 and MCSN1 must be 0. Periphery chip select, active low (PCSN0) and active high (PCSN1): to access the control registers PCSN0 must equal 0 and PCS1 must equal 1. RAM busy, active low: becomes active if an access to an address of the dual port RAM is performed simultaneously to an access to the same memory location by the internal telegram processing. DMA request receive, active high: becomes active if data from the receive FIFO can be read. At the beginning of the read operation of the last word of the receive FIFO, DMAREQR becomes inactive. DMA acknowledge receive, active low: when DMAACKRN is 0, the receive FIFO is read, independent of the levels on A6-1 and the chip select signals. DMA request transmit, active high: becomes active when data can be written to the transmit FIFO. DMAREQT becomes inactive again at the beginning of the last write access to the transmit FIFO. DMA acknowledge transmit, active low: when DMAACKTN is 0, the transmit FIFO is written to when there is a bus write access independent of the levels on A6-1 and the chip select signals. Address data bus: when ADMUX is 0 A15-0 are the address inputs, when ADMUX is 1 A15-0 are the outputs of the address latch. Bus mode: BUSMODE0 = 0 turns on the Intel bus interface (RDN = read, WRN = write), BUSMODE0 = 1 selects the Motorola interface (RDN = data strobe, WRN = read/write). BUSMODE1 selects the 0-active data strobe (BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1). Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1).
D15-0
I/O
A15-0
I/O
ALEL, ALEH
54, 53
I
RDN
51
I
WRN
52
I
BHEN MCSN0, MCSN1 PCSN0, PCS1 BUSYN
75 46,47 48,49
I I I
45
O
DMAREQR
38
O
DMAACKRN
40
I
DMAREQT
39
O
DMAREQTN
41
I
ADMUX
96
I
BUSMODE0, BUSMODE1 BUSWIDTH
97,98
I
99
I
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PIN DESCRIPTION (Continued) Table 1. SERCON410B I/O Port Function Summary (Continued)
Signal (s) BYTEDIR Pin (s) 100 IO I Function Byte address sequence: when BYTEDIR is 0, A0 = 0 addresses the lower 8 bits of a word (low byte first), when BYTEDIR is 1, the upper 8 bits of a word are addressed (high byte first). Interrupts, active low or active high. Interrupt sources and signal polarity are programmable. Internal regeneration. When SREGEN is 0, clock and data regeneration are turned off. RxC and TxC are clock inputs. When SREGEN is 1, clock and data regeneration are turned on. RxC and TxC output the internally generated clocks. Baud rate. When regeneration is turned on, SBAUD selects the baud rate (fSCLK/16 when SBAUD is 0, fSCLK/32 when SBAUD is 1). Can be overwritten by the microprocessor. Receive data for the serial interface. Receive clock for the serial interface. When regeneration is turned off (SREGEN = 0), clock input for the serial receiver and transmitter (only when repeater is turned on); when regeneration is turned on (SREGEN = 1) output of the internally generated receive clock. The maximum frequency is 10 MHz. Receive active, active low. Indicates that the serial receiver is receiving a telegram. Transmit data. The pin can be switched to a high impedance state. Transmit data or output port. The pins either output the serial data or can be used as parallel output ports. When they output transmit data, each pin can be switched to a high impedance state individually. NRZ-coded transmit data. Transmit clock for the serial interface. When regeneration is turned off (SREGEN = 0) and the repeater is turned off, it is the clock input for the serial transmitter; when regeneration is turned on (SREGEN = 1) it is the output for the internally generated transmit clock. The maximum frequency is 10 MHz. Transmitter active, active low. When transmitting own data IDLE is 0. Turn on test generator: TM0 = 0 switches TxD1-6 to continuous signal light, TM1 = 0 switch-over to zero bit stream. The processor can overwrite the level of TM1-0. Line error, active low: goes low when signal distortion is too high or when the receive signal is missing. The operating mode is programmed by the processor. SERCOS interface cycle clock: CYC_CLK synchronizes the communication cycles. The polarity is programmable. Control clock: becomes active within a communication cycle. Time, polarity and width are programmable. Divided control clock: becomes active several times within a ommunication cycle. Number of pulses, start time, repetition rate and polarity are programmable, the pulse width is 1s. Serial clock for clock regeneration: the frequency is 16 or 32 times the baud rate, the maximum frequency is 64 MHz. 7/30
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INT0, INT1
44,43
O
SREGEN
28
I
SBAUD RxD
29
I I
14 12
RxC
I/O
RECACTN TxD1 TxD6-2 TxDNRZ
26 16 22,21,2 0, 18,17 24 13
O O O O
TxC
I/O
IDLE TM0, TM1
25 30,31
O I
L_ERRN
32
O
CYC_CLK CON_CLK
34 35
36
I O
DIV_CLK
O
SCLK
2
I
SERCON410B
PIN DESCRIPTION (Continued) Table 1. SERCON410B I/O Port Function Summary (Continued)
Signal (s) SCLKO2 SCLKO4 MCLK RSTN TEST OUTZ Pin (s) 6 5 4 10 7 11 IO O O I I I I Function Clock output: outputs the SCLK clock divided by 2. Clock output: outputs the SCLK clock divided by 4. Master clock for telegram processing and timing control, frequency 12 to 20 MHz. Reset, active low. Must be zero for at least 50 ns after power on. Test, active high. Has to be tied to VSS. Puts outputs into high impedance state, active high: OUTZ is 1 puts all pins into a high impedance state. The clocks are turned off and the circuit is reset. For the in-circuit test and for turning on the powerdown mode. NAND tree output. For the test at the semiconductor manufacturers and for the connection test after board production. NDTRO is not set to a high impedance state.
NDTRO
9 3,15,23, 33,42, 50,60, 70,81, 91 1,8,19, 27,37, 55,65, 76,86
O
VSS
Ground pins.
VDD
Power supply +5 V 5%.
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3 ELECTRICAL CHARACTERISTICS 3.1 ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VO TSTG Supply Voltage Input Voltage Output Voltage Storage Temperature Parameter Value -0.3 to 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 -55 to +150 Unit V V V C
3.2 RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD fSCLK fMCLK fTxC, fRxC Parameter Min. Operating Temperature Operating Supply Voltage Clock Frequency SCLK Clock Frequency MCLK Clock Frequency TxC, RxC -40 4.75 Value Max. 85 5.25 64 20 10 C V MHz MHz MHz Unit
3.3 DC ELECTRICAL CHARACTERISTICS (VDD = 5V 5% TA = -40C to +85C, unless otherwise specified)
Value Symbol Parameter Test Conditions Min. VIL Input Low Level Voltage Input High Level Voltage Typ. Max. 0.8 V Unit
VIH
2.4 All pins except D15-0, A15-0, ALEL, ALEH, RDN, WRN, BHEN, MCSN0-1, PCSN0, PCS1, DMAACKTN, DMAACKRN 0.6 2.0 2.4
V V
Schmitt trig. +ve threshold
VT+
VT-
Schmitt trig. +ve threshold
0.8
V
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DC ELECTRICAL CHARACTERISTICS (Continued)
Value Symbol Parameter Test Conditions Min. IIL Low Level Input Current (Pull-up resistor) High Level Input Current VI = VSS -450 Typ. -50 Max. -30 A A Unit
IIH VOL
VI = VDD
-10
<1
10
Low level Output Voltage, all O- and I/O-pins except TXD6-1 High level output voltage, all O- and I/O-pins except TXD6-1 High level output voltage, all O- and I/O-pins except TXD6-1 High level output voltage, pins TXD6-1 Tri-state output leakage I/O latch-up current Electrostatic protection Pin capacitance
IOI = -4 mA
0.4
V
VOH
IOH = +4 mA
2.4
V
VOL
IOI = -8 mA
0.4
V
VOH IOZ IKLU VESD C PIN
IOH = +8 mA VO = 0 V or VDD VVDD C=100 pF, R = 1.5 k
VDD - 0.5 -10 200mA 2000 10 <1 +10 A mA V pF
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3.4 AC ELECTRICAL CHARACTERISTICS Figure 5. Timing of Clock MCLK and Related Outputs (Cload = 50 pF, VDD = 5 V 5% TA = -40 C to +85 C)
3.4.1 Clock Input MCLK
Symbol fMCLK tMCLK0 tMCLK1 tMCLD Parameter Min. Clock Frequency MCLK MCLK Low MCLK High Output Delay Rising Edge MCLK to DMAREQR/T, CON_CLK, DIV_CLK 12 20 20 30 Value Type Max. 20 MHz ns ns ns Unit
Figure 6. Timing of Clock SCLK
3.4.2 Clock Input SCLK
Symbol fSCLK tSCLK0 tSCLK1 Parameter Min. Clock Frequency SCLK SCLK Low SCLK High 6.5 6.5 Value Type Max. 64 MHz ns ns Unit
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AC ELECTRICAL CHARACTERISTICS (Continued) Figure 7. Timing of Serial Clock Inputs RxC and TxC and Related Signals
3.4.3 Serial Clock (SREGEN = 0, external clock regeneration, RxC and TxC are inputs)
Symbol fRTXC tRTXC0 tRTXX1 tRTOUT tRXDSU Parameter Min. Clock Frequency RxC, TxC RxC, TxC Low RxC, TxC High Output Delay RxC, TxC to TxD6-1, TxDNRZ, IDLE, RECACTN Setup RxD to Falling Edge of RxC 15 40 40 45 Value Type Max. 10 MHz ns ns ns ns Unit
Figure 8. Timing of Serial Clock Inputs RxC and TxC and Related Signals
3.4.4 Address Latch
Symbol tALEW tALESU tALEHD tDA 12/30
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Parameter Min. Pulse Width ALEL, ALEH Setup Time D15-0 To Falling Edge ALEH, ALEL Hold Time Falling Edge ALEH, ALEL to D15-0 Delay from D15-0 to A15-0 25 10 5
Value Type Max.
Unit ns ns ns 20 ns
SERCON410B
AC ELECTRICAL CHARACTERISTICS (Continued) Figure 9. Read Access of Control Registers
3.4.5 Read Access of Control Registers
Symbol Parameter Min. Setup time A6-0, BHEN, PCSN0, PCS1, DMAACKNR, WRN (only Motorola mode) to falling edge RDN (Intel or Motorola mode with low active strobe) or rising edge RDN (Motorola mode with high active strobe) Hold time A10-0, BHEN, MCSN0-1, WRN (only Motorola mode) to rising edge RDN (Intel Motorola mode with low active strobe) or falling edge RDN (Motorola mode with high active strobe) Access time A6-0, BHEN, PCSN0, PCS1, DMAACKNR, WRN (only Motorola mode) to D15-0 valid Access time RDN to D15-0 valid Delay RDN to D15-0 high-Z Delay RDN to DMAREQR low Value Type Max. Unit
tASU
0
ns
tAHD
0
ns
tPAD tPRDD tRDZ tPRQ
50 40 15 30
ns ns ns ns
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AC ELECTRICAL CHARACTERISTICS (Continued) Figure 10. Read Access of Dual Port RAM
3.4.6 Read Access of Dual Port RAM
Symbol Parameter Min. Setup time A10-0, BHEN, MCSN0-1, WRN (only Motorola mode) to falling edge RDN (Intel or Motorola mode with low active strobe) or rising edge RDN (Motorola mode with high active strobe) Hold time A10-0, BHEN, MCSN0-1, WRN (only Motorola mode) to rising edge RDN (Intel Motorola mode with low active strobe) or falling edge RDN (Motorola mode with high active strobe) Access time RDN to D15-0 valid Delay RDN to BUSYN low Delay BUSYN high to D15-0 valid Delay RDN to D15-0 high-Z RDN and WRN high after end of read access 30 Value Type Max. Unit
tASU
0
ns
tAHD
0
ns
tMRDD tMBSY tMBHD tRDZ tRD1
60 35 30 15
ns ns ns ns ns
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AC ELECTRICAL CHARACTERISTICS (Continued) Figure 11. Write Access to Control Registers
3.4.7 Write Access to Control Registers
Symbol Parameter Min. Setup time A6-0, BHEN, PCSN0, PCS1, DMAACKNT, WRN (only Motorola mode) to falling edge WRN (Intel mode) or RDN (Motorola mode, strobe active low) or rising edge RDN (Motorola mode, strobe active high) Hold time A6-0, BHEN, PCSN0, PCS1, DMAACKNT, WRN (only Motorola mode) to rising edge WRN (Intel mode) or RDN (Motorola mode, strobeactive low) or falling edge RDN (Motorola mode, strobe active high) Pulse width WRN (Intel mode) or RDN (Motorola mode) Setup time D15-0 to end of write access Hold time D15-0 to end of write access Delay WRN or RDN to DMAREQT low Value Type Max. Unit
tASU
0
ns
tAHD
0
ns
tPWRW tDSU tDHD tPRQ
30 10 10 30
ns ns ns ns
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AC ELECTRICAL CHARACTERISTICS (Continued) Figure 12. Write Access to DUAL Port RAM
3.4.8 Write Access to Dual Port RAM
Symbol Parameter Min. Setup time A10-0, BHEN, MCSN0-1, WRN (only Motorola mode) to falling edge of WRN (Intel mode) or RDN (Motorola mode with low active strobe) or rising edge RDN (Motorola mode with high active strobe) Hold time A10-0, BHEN, MCSN0-1, WRN (only Motorola mode) to rising edge of WRN (Intel mode) or RDN (Motorola mode with low active strobe) or rising edge RDN (Motorola mode with high active strobe) Pulse width WRN or RDN Setup time D15-0 to end of write access Hold time D15-0 after end of write access Delay WRN or RDN (begin of write access) to BUSYN low Setup time BUSYN high to end of write access WRN and RDN high after end of write access 30 40 Value Type Max. Unit
tASU
0
ns
tAHD
0
ns
tMWRW tDSU tDHD tMBSY tMBHWH tWR1
30 10 10 35
ns ns ns ns ns ns
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4 CONTROL REGISTERS AND RAM DATA STRUCTURES 4.1 CONTROL REGISTER ADDRESSES The following table is an overview of the control registers. The address is the word address which is input by A6-1. To calculate the byte address, the value has to be multiplied by two. The reset values of the control registers are shown in bold. All control registers can be written to and read (R/W), with the exception of the control bits that initiate an action (W). The status registers can only be read (R). When control registers which contain bits that are not used or can only be read, are written to, these bits can be set to 0 or 1; they are not evaluated internally. If control registers are read with bits that are not used, these bits are set to 0.
A6-1 0H
Bit 0-15 0 1 2 3 4 5
Name VERSION RSTFL SWRST
R/W R R/W W
Value 2 0 1 0 1
Function Circuit code (0002H) Reset has not taken place Reset has taken place Do not reset Reset by software (Not used)
REPON SREGEN REGMODE
R/W R R/W
0 1
Repeater turned off Repeater turned on Level at SREGEN pin
0 1 0 1 0 1 0 1 0 1 0 1
Sampling at the middle of bit Sampling according to SERCOS interface specification Baud rate = fSCLK / 16 Baud rate = fSCLK / 32 "Light on" when RxD = 0 "Light on" when RxD = 1 No pre-frame sync word Pre-frame sync word "Light on" when TxD = 0 "Light on" when TxD = 1 Baud rate selected by SWSBAUD pin Baud rate selected by SWSBAUD control bit Level at pin SBAUD
6 1H 7 8 9 10 11 12 13 14 15 POLRXD PRESYNC POLTXD ENTSBAUD SBAUD RXDNRZ WRSYNC DMAMODE
R/W R/W R/W R/W R/W R R/W R/W R/W
0 1
Receive data is NRZI-coded Receive data is NRZI-coded Direct RAM write access RAM write access internally synchronized
0 1
DMAREQR/DMAREQT are static signals DMAREQR/DMAREQT are pulses (Not used)
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CONTROL REGISTER ADDRESSES (Continued)
A6-1 Bit 0-5 6 Name ENTXD1-6 TXDMODE R/W R/W R/W Value 0 1 0 1 0-3 4,6 5 7 0 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Pin TxDn has a high impedance Pin TxDn is outputting transmit data TXDMODE TxD2-6 is outputting ENTXD2-6 Test functions are controlled via TM0-1 pins Continuous signal light Zero bit stream Normal operation Level at TM0-1 Receive data normal Receive data over distortion limit Filler signal or data is received No edges on receive data L_ERRN L_ERRN L_ERRN L_ERRN active by FIBBR and RDIST active by RDIST active by FIBBR is inactive
7-9 2H
TMODE0-2
R/W
10-11 12 13
TM0-1 RDIST FIBBR
R R R
14-15
LMODE0-1
R/W
0 1 2 3 4 5 6 7 8 9 10 11
INTFL0 ENINT0 POLINT0 INTFL1 ENINT1 POLINT1 COMACT COMBLK ENTMT FLTMT FLRWAIT FLREC
R R/W R/W R R/W R/W R R R/W R R R
Interrupt INT0 not active Interrupt INT0 active Interrupt INT0 disabled Interrupt INT0 disabled Interrupt INT0 1-active Interrupt INT0 0-active Interrupt INT1 not active Interrupt INT1 active Interrupt INT1 disabled Interrupt INT1 enabled Interrupt INT1 1-active Interrupt INT1 0-active No transmission block is processed Transmission block is processed Transmission block 0 is processed Transmission block 1 is processed Do not send data telegrams Send data telegrams Data telegram is not sent Data telegram is sent Data telegram is not expected Data telegram is expected Data telegram is not received Data telegram is received
3H
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SERCON410B
CONTROL REGISTER ADDRESSES (Continued)
A6-1 Bit 12 3H 13 14 15 Name DMAREQT DMAREQR IDLE RECACTN INT_n CLR_INT_n 0 1 2 3 4 4H 5 6 7 8 9 10 11 12 13 14 15 0-7 8 5H 9-12 13 14 15 INT_RDIST INT_FIBBR INT_COMBLK0 INT_COMBLK1 INT_COMEND INT_PHAS0 INT_PHASERR INT_MSTEARLY INT_MSTLATE INT_MSTMISS INT_TSTART INT_TEND INT_RWAIT INT_RSTART INT_REND INT_RERR INT_SC_0-7 INT_RMISS INT_TIME0-3 INT_DIVCLK INT_PROGERR INT_NEWADR R/W R R R R R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 Value 0 1 0 1 Function DMA request of transmit FIFO inactive DMA request of transmit FIFO active DMA request of receive FIFO inactive DMA request of receive FIFO active Level at IDLE pin Level at RECACTN pin Interrupt event has not occurred Interrupt flag active, interrupt event has occurred Do not modify interrupt flag Clear interrupt flag Interrupt receive data distorted Interrupt no receive data Interrupt start transmission block 0 Interrupt start transmission block 1 Interrupt end of transmission block Interrupt phase MST = 0. Interrupt phase MST errored Interrupt communication cycle start too early Interrupt communication cycle start too late Interrupt MST missing twice Interrupt start of transmit telegram Interrupt end of transmit telegram Interrupt start waiting for receive telegram Interrupt start of receive telegram Interrupt end of receive telegram Interrupt error of receive telegram Interrupt service container Interrupt receive telegram missing twice Interrupt time TINT0-3 Interrupt DIVCLK signal Interrupt programming error Interrupt address change
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CONTROL REGISTER ADDRESSES (Continued)
A6-1 6H Bit 0-15 Name EN0_INT_n R/W R/W Value 0 1 0 1 0 1 0 1 Function Interrupt flag does not activate INT0 Interrupt flag activates INT0 Bit assignment same as for address 4H Interrupt flag does not activate INT0 Interrupt flag activates INT0 Bit assignment same as for address 5H Interrupt flag does not activate INT1 Interrupt flag activates INT1 Bit assignment same as for address 4H Interrupt flag does not activate INT1 Interrupt flag activates INT1 Bit assignment same as for address 5H Phase for MST transmit (master) or MST receive (slave) (reset value = 0FFH) Phase for MST receive (slave) (reset value = 0FFH) Phase information of received MST Address of receive telegram 0 1 0 1 0 2 COMBLK0 R/W 1 0 0CH 3 COMBLK1 R/W 1 MST is not transmitted or received MST is transmitted or received (SERCOS interface mode) Receive MST (SERCOS interface slave) Transmit and receive MST (SERCOS interface master) When phase = PHAS0 transmission block 0 is processed When phase = PHAS0 transmission block 1 is processed When phase = PHAS1 transmission block 0 is processed When phase = PHAS1 transmission block 1 is processed Level at CON_CLK pin 0 1 0 1 CON_CLK pin doesn't become active CON_CLK pin becomes active from TINT0 to TINT1 Signal at CON_CLK is 1-active Signal at CON_CLK is 0-active Level at CYC_CLK pin 0 1 CYC_CLK pin does not trigger timing control CYC_CLK pin triggers timing control after TCYCSTART
7H
0-15
EN0_INT_n
R/W
8H
0-15
EN1_INT_n
R/W
9H
0-15
EN1_INT_n
R/W
0-7 OAH 8-15 0-7 8-15 0
PHAS0 PHAS1 PHASREC RECADR MSTEN
R/W R/W R R R/W
OBH
1
MSTMASTER
R/W
4 5
CON_CLK ENCONCLK
R R/W
6 7 8
POLCONCLK CYC_CLK ENCYCCLK
R/W R R/W
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CONTROL REGISTER ADDRESSES (Continued)
A6-1 Bit Name R/W Value 0 9 POLCYCCLK R/W 1 0 1 0 1 Function Timing control triggered by rising edge of CYC_CLK Timing control triggered by falling edge of CYC_CLK No function Trigger timing control after TCYCSTART (master) Do not read TCNT Load TCNT to TCNTRD Number of communcation cycles triggered by CYC_CLK or CYCSTART Handshake timeout for service channel BUSY timeout for service channel Predivider value: fMCLK/1 MHz - 1 (reset value = 19) (Not used) MCLKST R/W Initial value for predivider (Not used) TSCYC0 TSCYC1 TCYCDEL TCNTLT TCNTST TCYCSTART JTSCYC1 JTSCYC2 PROGERR_FL CLR_PROGERR_FL 18H 19H 1AH 1BH 0-15 0-15 0-15 0-15 JTRDEL1 JTRDEL2 TINT0 TINT1 R/W R/W R R R/W R/W R/W R/W R W R/W R/W R/W R/W SERCOS interface cycle time in *s for transmission block 0 SERCOS interface cycle time in *s fur transmission block 1 Time at which MST is received, ring delay (master) Stored value of TCNT time counter Initial value for TCNT time counter Delay in triggering timing control Receive time window for MST 1 Receive time window for MST 2 Error flags Clear error flags Receive time window for data telegram 1 Receive time window for data telegram 2 Time at which time interrupt 0 and first edge of CON_CLK occur Time at which time interrupt 1 and second edge of CON_CLK occur
OCH
10
CYCSTART
W
11 12-15 0-7 8-15 0-4 0EH 5-7 8-12 13-15 0FH 10H 11H 12H 13H 14H 15H 16H 17H 0-15 0-15 0-15 0-15 0-15 0-15 0-15 0-15 0-15
RDTCNT NCYC HS_TIMEOUT BUSY_TIMEOUT MCLKDIV
W R/W R/W R/W R/W
0DH
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CONTROL REGISTER ADDRESSES (Continued)
A6-1 1CH 1DH 1EH 1FH Bit 0-15 0-15 0-15 0-15 0-7 20H 8 9-15 0-9 10-15 22H 0-15 0-9 23H 10-15 24H 0-15 0-9 10 THW THRPT MSTTCHK R R R/W 0 1 0 1 0 12 FLMDTADR R/W 1 THT THWPT R R THTPT R TINT2 TINT3 TDIVCLK DTDIVCLK NDIVCLK POLDIVCLK Name R/W R/W R/W R/W R/W R/W R/W 0 1 Value Function Time at which time interrupt 2 occurs Time at which time interrupt 3 occurs Time at which the first pulse of DIV_CLK occurs DIV_CLK pulse distance Number of DIV_CLK pulses within one communication cycle (reset value =0) Pulses from DIV_CLK are 1-active Pulses from DIV_CLK are 0-active (Not used) Internal RAM address of telegram header of transmitted telegram (Not used) Control word 0 of telegram header of transmitted telegram Internal RAM address of telegram header of a telegram which is expected (Not used) Control word 0 of telegram header of telegram which is expected Internal RAM address of telegram header of received telegram MST receive time is not checked MST receive time is checked Normal operation Operating mode for SERCOS interface phase 1 and 2 Address of receive telegram different from expected value Address of receive telegram equal to expected value (Not used) THR RFIFO TFIFO R R W Control word 0 of telegram header of received telegram Receive FIFO Transmit FIFO
21H
25H
11
PHAS12
R/W
13-15 26H 0-15 0-15 0-15
27H
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4.2 DATA STRUCTURES WITHIN THE RAM In this RAM the first eleven words have a fixed meaning.
A10-1 0-1 2-9 10 Contents COMPT0-1: Start of transmission blocks 0-1 SCPT0-7: Address service containers 0-7 NMSTERR: Error counter MST
The rest of the RAM can be divided into data structures as required.
4.2.1 Telegram Headers A telegram header for receive telegram contains thefollowing five control words:
INDEX Bit 0-7 8 9 Name ADR DMA DBUF Telegram address Data storage in the internal RAM (DMA = 0) or DMA transfer (DMA = 1) Data in the RAM: single buffer (DBUF = 0) or double buffer (DBUF = 1) For single buffering (DMA = 0, DBUF = 0) or DMA transfer (DMA = 1): telegram data is invalid (VAL = 0) or valid (VAL = 1); for double buffering (DMA = 0, DBUF = 1): data in buffer 0 (VAL = 0) or buffer 1 (VAL = 1) is valid. Modified by controller at beginning and end of receive telegrams. Telegrams are received if the address is valid (ACHK = 1) or independent on the received address (ACHK = 0). The received address is stored at ADR. The time of receiving is checked (TCHK = 1) or not checked (TCHK = 0). The last telegram was free of error (RERR = 0) or errored or not received (RERR = 1). Marker bit for telegram header of receive telegram. Marker bit for telegram header. Time for the start of telegram in s after end of MST. Length of telegram in data words (not including address). Word address within the RAM of the next telegram header or the end marker. (Not used) NERR Error counter Function
10 0
VAL
11
ACHK
12 13 14 15 1 2 0-15 0-15 0-9 10-15 4 0-15
TCHK RERR 0 0 TRT TLEN PT
3
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DATA STRUCTURES WITHIN THE RAM (Continued) A telegram header for transmit telegram comprises four control words:
Index
Bit 0-7 8 9 10
Name ADR DMA DBUF VAL Telegram address
Function
Data storage in the RAM (DMA = 0) or DMA transfer (DMA = 1). Data in RAM: single buffer (DBUF = 0) or double buffer (DBUF = 1). For double buffering (DMA = 0, DBUF = 1): data in buffer 0 (VAL = 0) or buffer 1 (VAL = 1) are valid. Set by processor. Data telegram is not to be transmitted (EN = 0), transmitted once (EN = 1), continuously (EN = 2) or transmitted only if the previously received telegram contains the expected address (EN = 3) (PHAS12 =1 and FLMDTADR = 1). If EN is 1 the circuit sets EN to 0 after the transmit telegram has been started. (Not used)
0 11-12 EN
13 14 15 1 2 3 0-15 0-15 0-9 10-15 1 0 TRT TLEN PT
Marker bit for telegram header of transmit telegram. Marker bit for telegram header. Time for the start of telegram in *s after the end of MST. Length of the telegram in data words (not including address). Word address of the next telegram header or the end marker. (Not used)
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DATA STRUCTURES WITHIN THE RAM (Continued) 4.2.2 Data Containers A data container comprises one or two 16-bit control words as well as a variable number of data words. If the data is stored in the internal RAM (DMA = 0) and a single buffer is used (DBUF = 0), the data container has one buffer. Using RAM
Index Bit 0-9 10 0 11-13 14 15 Name LEN SVFL NSV SCMASTER LASTDC
storage and double buffering (DBUF = 1), two data buffers are needed. In case of DMA transfer (DMA = 1) the data container only comprises the control words (Fig. 13). The structure of the two control words depends on whether a telegram is transmitted or received:
Function
Number of 16-bit data words of the data block. Flag, whether data block uses service container (SVFL = 1). Number of service container, which is used (0 - 7). Processing of service container in slave mode (SCMASTER = 0) or master mode (SCMASTER = 1). Last data container of the telegram (1) or further data containers follow (0). Position of the data block within the telegram in number of words. The first data record of a telegram has POS = 0 (only in case of receive telegrams).
1
0-15
POS
Figure 13. Structure of Data Containers
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DATA STRUCTURES WITHIN THE RAM (Continued) 4.2.3 End Marker The end marker comprises two 16-bit words:
Index Bit 0-13 0 14 15 1 0-15 1 1 TEND Name (Not used) Marker bit for the end marker. Marker bit for the end marker. Time after end of MST at which the last telegram has ended (in s). Function
4.2.4 Service Containers A service container contains 5 control words and a buffer (BUFLEN words, max. length 255) (Fig. 14) Figure 14. Structure of Service Container
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DATA STRUCTURES WITHIN THE RAM (Continued) For master mode (SCMASTER = 1) the control words are coded as follows:
Index Bit 0 1 2 3-5 6 0 7 8-9 10-11 12 13 14 15 0 1 2 1 3 4-6 7 8-9 10-15 2 0-7 8-15 3 0-7 8-15 0-7 8 9 4 10 11 12 13-15 WRDATPT WRDATLAST RDDATPT RDDATLAST ERR_CNT BUSY_CNT INT_SC_ERR INT_HS_TIMEOUT INT_BUSY_TIMEOUT INT_CMD RECERR NINFO_READ HS_AT BUSY_AT ERR_AT CMD_AT INT_ERR INT_END_WRBUF INT_END_RDBUF Name HS_MDT L/S_MDT END_MDT ELEM_MDT SETEND M_BUSY NINFO_WRITE Handshake-bit in MDT Read/write in MDT End in MDT Data element type in MDT END_MDT is to be set Service container waits for interaction of microprocessor (M_BUSY = 1) Number of info words in write buffer (1 to 4) (Not used) Slave reports error End of write buffer is reached End of read buffer is reached (Not used) Handshake bit in AT Busy bit in AT Error bit in AT Command modification bit in AT (Not used) Last transmission was correct (0) or errorneous (1) Number of info words in read buffer (1 to 4) (Not used) Pointer to present position in write buffer Pointer to last position in write buffer Pointer to present position in read buffer Pointer to last position in read buffer Error counter Error counts differences of handshake (0) or BUSY cycles (1) Interrupt due to protocol error Interrupt due to handshake timeout Interrupt BUSY timeout Slave has set command modification bit (Not used) 27/30
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SERCON410B
DATA STRUCTURES WITHIN THE RAM (Continued) The coding of the five control words depends on the mode of the service channel. Using the slave mode (SCMASTER = 0) they have the following structure:
Index Bit 0 1 2 3 4-6 0 7 8-9 10-11 12 13 14 15 0 1 2 1 3-5 6 7 8-9 10-15 2 0-7 8-15 3 0-7 8-15 0-8 4 9 10-15 INT_SC_ERR WRDATPT WRDATLAST RDDATPT RDDATLAST RECERR NINFO_READ INT_ELEM_CHANGE INT_END_WRBUF INT_END_RDBUF INT_END_MDT HS_MDT L/S_MDT END_MDT ELEM_MDT Name HS_AT BUSY_AT ERR_AT Error bit in AT ELEM L/S NINFO_WRITE Handshake bit in AT Busy bit in AT, also waiting for microprocessor interaction Error bit in AT Command modification bit in AT Data element of present transmission Read (0)/write (1) of present transmission Number of info words in write buffer (1 to 4) (Not used) Master has modified data element or read/write End of write buffer is reached End of read buffer is reached Master reports end via END_MDT-bit Handshake bit in MDT Read/write in MDT End bit in MDT Data element in MDT (Not used) Last transmission was correct (0) or errorneous (1) Number of info words in read buffer (1 to 4) (Not used) Pointer to present position in write buffer Pointer to last position in write buffer Pointer to present position in read buffer Pointer to last position in read buffer (Not used) Interrupt due to protocol error (Not used) Function
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5 PACKAGE MECHANICAL DATA Figure 15. SERCON410B 100 Pin Plastic Quad Flat Pack Package
Dim. Min A A2 D D1 D3 E E1 E3 e ND NE N
mm Typ Max 3.40 2.55 2.80 Min
inches Typ Max 0.134
3.05 0.100 0.110 0.120
23.65 23.90 24.15 0.931 0.941 0.951 19.90 20.00 20.10 0.783 0.787 0.791 18.85 0.742 17.65 17.90 18.15 0.695 0.705 0.715 13.90 14.00 14.10 0.547 0.551 0.555 12.35 0.65 Number of Pins 30 20 100 0.486 0.026
6 ADDITIONAL SUPPORT AND TOOLS 6.1 SERCOS INTERFACE SPECIFICATION The SERCOS interface specification is available at: Fordergemeinschaft SERCOS interface e.V. Herseler Str. 31 D-50389 Wesseling Tel. xx49-2236-1517 Fax. xx49-2236-1542 6.2 SOFTWARE AND BOARDS FOR THE SERCON410B Driver software SERCDRV Master and slave routines for the SERCON410B Written in ANSI-C Independent from operating system and processor Contains: - initialization - start-up of SERCOS interface (phases 0 - 4) - service channel transmission Easy portable to many microprocessors and hardware platforms
PC-AT board SERCEB 16-bit ISA bus Receiver and transmitter for fibre optics (SERCOS interface standard) SERCON410B and additional timerchip 82C54 Additional RS-485-signals for serial connection and synchronization Wire wrap area for extension Add-on board SERCINT Multiplexed 16-bit address/data-bus Receiver and transmitter for fibre optics (SERCOS interface standard) SERCON410B Additional RS-485-signals for serial connection These software and boards are available at: IAM GmbH Vertrieb Systemtechnik Richard-Wagner-Str. 1 D-38106 Braunschweig Tel. xx49-531-3802-0 Fax. xx49-531-3802-110
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NOTES:
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All rights reserved. Purchase of I 2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I 2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I 2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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