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| CXP87240A/87248A CMOS 8-bit Single Chip Microcomputer Description The CXP87240A/87248A is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, PWM generator, PWM for tuner, VISS/VASS circuit, 32kHz timer/event counter, remote control receiving circuit, general purpose prescaler, HSYNC counter, VCR vertical sync separation circuit and the measuring circuit which measure signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP87240A/87248A provides sleep/stop function which enables to lower power consumption and ultra-low speed instruction mode in 32kHz operation. 100 pin QFP (PIastic) 100 pin LQFP (PIastic) Structure Silicon gate CMOS IC Features * A wide instruction set (213 instructions) which cover various types of data -- 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction * Minimum instruction cycle During operation 333ns/12MHz (3.0 to 5.5V) During operation 250ns/16MHz (4.5 to 5.5V) During operation 122s/32kHz * Incorporated ROM capacity 40Kbytes (CXP87240A), 48Kbytes (CXP87248A) * Incorporated RAM capacity 1376bytes * Peripheral functions -- A/D converter 8-bit, 12-channel, successive approximation system (Conversion time 20.0s/16MHz) -- Serial interface Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel Incorporated 8-bit and 8-stage FIFO (1 to 8 bytes auto transfer) 1-channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter -- High precision timing pattern generator PPG 19-pin 32-stage programmable RTG 5-pin 2-channel -- PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz) DA gate pulse output 13-bit, 4-channel -- Servo input control Capstan FG, Drum FG/PG, CTL input -- VSYNC separator -- FRC capture unit Incorporated 26-bit and 8-stage FIFO -- PWM output 14-bit, 1-channel -- VISS/VASS circuit Pulse duty auto detection circuit -- Remote control receiving circuit 8-bit pulse measuring counter, 6-stage FIFO -- General purpose prescaler 7-bit (SYNC1 input frequency divided, FRC capture possible) -- HSYNC counter 12-bit event counter (counts the SYNC1 input.) * Interruption 22 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 100-pin plastic QFP/LQFP * Piggyback/evaluation chip CXP87200A 100-pin ceramic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E94833-ST Block Diagram AVREF AVss PI4/INT1/NMI PE1/INT2 AVDD TEX TX EXTAL XTAL RST MP VDD Vss SPC700 CPU CORE PORT B CLOCK GENERATOR/ SYSTEM CONTROL 8 PORT A AN0 to AN3 PF0/AN4 to PF7/AN11 2 8 PA0 to PA7 NMI 12 A/D CONVERTER PE0/INT0 CS0 SI0 SO0 SCK0 RAM PORT C SERIAL INTERFACE UNIT (CH0) PB0 to PB7 PI3/TO/DDO 8 BIT TIMER 1 PORT D PE1/EC 8 BIT TIMER/COUNTER 0 INTERRUPT CONTROLLER PI7/SI1 PI6/SO1 PI5/SCK1 FIFO 2 ROM 40K/48K BYTES RAM 1376 BYTES SERIAL INTERFACE UNIT (CH1) 8 PC0 to PC7 8 PD0 to PD7 PE0/CKOUT 2 6 4 4 PE0 to PE1 PORT E PG4/SYNC0 PG5/SYNC1 2 2 2 VSYNC SEPARATOR PE2 to PE7 PF0 to PF3 PORT F PG6/EXI0 PG7/EXI1 PI1/RMC REMOCON INPUT FIFO 32kHz TIMER/COUNTER PI2/PWM 14 BIT PWM GENERATOR 2 PORT H VISS/VASS PORT G 12 BIT PWM GENERATOR CH0 2 PROGRAMMABLE PATTERN GENERATOR RAM REALTIME PULSE GENERATOR CH0 CH 1 12 BIT PWM GENERATOR CH1 4 PORT I PE2/PWM0 PE4/DAA0 PE6/DAB0 PE3/PWM1 PE5/DAA1 PE7/DAB1 PROGRAMMABLE PRESCALER PE1/HCOUT HSYNC COUNTER 19 5 PI3/ADJ PC3/RTO3 to PC7/RTO7 PORT J PA0/PPO0 to PC2/PPO18 -2- SERVO INPUT CONTROL 3 FIFO FRC CAPTURE UNIT CAPSTAN PRESCALER/ TIME BASE TIMER PF4 to PF7 DRUM PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL CTL 8 PG0 to PG7 8 PH0 to PH7 7 PI1 to PI7 8 PJ0 to PJ7 CXP87240A/87248A CXP87240A/87248A Pin Configuration 1 (Top View) 100-pin QFP package PI3/TO/DDO/ADJ PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 PI4/INT1/NMI VSS NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO1 PI7/SI1 PE0/INT0/CKOUT PE1/EC/INT2/HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8 TX TEX VDD PI1/RMC PI2/PWM Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. -3- PF7/AN11 PF6/AN10 PF5/AN9 EXTAL SCK0 XTAL RST SO0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CS0 VSS MP SI0 PI5/SCK1 CXP87240A/87248A Pin Configuration 2 (Top View) 100-pin LQFP package PI3/TO/DDO/ADJ PB4/PPO12 PB5/PPO13 PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 PI4/INT1/NMI PI1/RMC PI2/PWM PI5/SCK1 PI6/SO1 VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE1/EC/INT2/HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF TX TEX NC VDD PF5/AN9 PF4/AN8 PI7/SI1 Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. -4- PF7/AN11 PF6/AN10 EXTAL SCK0 XTAL AVSS SO0 RST PD2 PD1 PD0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CS0 VSS SI0 MP PE0/INT0/CKOUT CXP87240A/87248A Pin Description Symbol PA0/PPO0 to PA7/PPO7 I/O Output/ Real time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port, enables to specify I/O by bit unit. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Description PB0/PPO8 to PB7/PPO15 PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 Output/ Real time output I/O/ Real time output I/O/ Real time output Programmable pattern generator (PPG) output. Functions as high precision real time pulse output port. (19 pins) PB0 and PB2 can be 3-state controlled with PPG. Real time pulse generator (RTG) output. Functions as high precision real time pulse output port. (5 pins) PD0 to PD7 I/O (Port D) 8-bit I/O port. Enable to specify I/O by 4-bit unit. Enables to drive 12mA sink current. (8 pins) Input pin to request external interruption. Active when falling edge. PC3 can be 3-state controlled with RTG. System clock frequency division output. External event Input pin to request Coincidence signal external interruption. input pin for output pin for timer/counter. Active when falling edge. HSYNC counter. PWM output pins. (2 pins) PE0/INT0/ CKOUT Input/Input/Output (Port E) 8-bit port. Lower 2 bits are input pins and upper 6 bits are output pins. (8 pins) PE1/EC/INT2/ HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 SCK0 SO0 SI0 CS0 Input/Input/Input/ Output Output/Output Output/Output Output/Output Output/Output Output/Output Output/Output Input Input/Input DA gate pulse output pins. (4 pins) Analog input pins to A/D converter. (12 pins) (Port F) Lower 4 bits are input port and upper 4 bits are output port. Lower 4 bits also serve as standby release input pin. (8 pins) Output/Input I/O Ouput Input Input Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin. Serial chip select (CH0) input pin. -5- CXP87240A/87248A Symbol PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 I/O Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input (Port G) 8-bit input port. (8 pins) Description Capstan FG input pin. Drum FG input pin. Drum PG input pin. Playback CTL pulse input pin. External event input pin of timer/counter. Composite sync signal input pin. External input pin to FRC capture unit. (Port H) 8-bit output port ; Medium withstand voltage (12V) and high current (12mA), N-ch open drain output. (8 pins) Remote control receiving circuit input pin. 14-bit PWM output pin. (Port I) 7-bit I/O port. I/O port can be specified by bit unit. (7 pins) Timer/counter, CTL duty detection, 32kHz oscillation adjustment output pin. Input pin to request external interruption and non-maskable interruption. Active when falling edge. Serial clock (CH1) I/O pin. Serial data (CH1) output pin. Serial data (CH1) input pin. (Port J) 8-bit I/O port. Function as standby release input can be specified by bit unit. I/O can be specified by bit unit. Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (Feedback resistor is not removed.) System reset pin of active "L" level. Microprocessor mode input pin. Always connect to GND. Positive power supply pin of A/D converter. PH0 to PH7 Output PI1/RMC PI2/PWM PI3/TO/ DDO/ADJ PI4/INT1/ NMI PI5/SCK1 PI6/SO1 PI7/SI1 PJ0 to PJ7 EXTAL XTAL TEX TX RST MP AVDD AVREF AVss VDD Vss I/O/Input I/O/Output I/O/Output/ Output/Output I/O/Input/Input I/O/I/O I/O/Output I/O/Input I/O Input Output Input Output Input Input Input Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. GND pin. Connect both Vss pins to GND. -6- CXP87240A/87248A Input/Output Circuit Formats for Pins Pin Port A Port B PA0 /PPO0 to PA7/PPO7 PB4/PPO12 to PB7/PPO15 PPO data Circuit format When reset Hi-Z Port A or Port B Data bus RD Output becomes active from Hi-Z by data writing to port register. 12 pins PB0 /PPO8 PB2/PPO10 PPO8 or PPO10 Hi-Z PB0 or PB2 data RD Data bus 2 pins Output becomes active from Hi-Z by data writing to port register. PPO9 or PPO11 PPG control status register bit 0 3-state control selection PPO9 or PPO11 PB1/PPO9 PB3/PPO11 PB1 or PB3 data Hi-Z Data bus RD Output becomes active from Hi-Z by data writing to port register. 2 pins -7- CXP87240A/87248A Pin Port C Circuit format When reset PC0/PPO16 to PC2/PPO18 PC5/RTO5 to PC7/RTO7 PPO, RTO data Port C data Input protection circuit IP (Every bit) Data bus RD (Port C) Data bus Port C direction Hi-Z 6 pins RD (Port C direction) RTO3 PC3 data PC3 direction PC3/RTO3 Data bus RD Data bus RD RTO4 Hi-Z 1 pins RTG interruption control register bit7 3-state control selection RTO4 PC4 data PC4/RTO4 Data bus PC4 direction Hi-Z RD Data bus RD RTO data is OR-gate data of ch0 and ch1. 1 pins -8- CXP87240A/87248A Pin Port D Circuit format When reset PD0 to PD7 Port D data IP (Every 4 bits) PD0 to 3 PD4 to 7 RD (Port D) High current 12mA Hi-Z Port D direction Data bus 8 pins Port E Port E/PWM selection register bit 0, 1 PE0/INT0/ CKOUT PS1 PS2 PS3 MPX Hi-Z IP Input protection circuit Data bus RD Interruption circuit 1 pin Port E Hi-z control HCOUT Input protection circuit From HSYNC counter PE1/EC/INT2/ HCOUT IP Hi-Z Data bus RD (Port E) To interruption circuit/ event counter 1 pin -9- CXP87240A/87248A Pin Port E DA gate output or PWM output Hi-Z control Circuit format When reset MPX PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 Port E data Hi-Z Port/DA output select Data bus 4 pins Port E RD (Port E) DA gate output Hi-Z control MPX PE6/DAB0 PE7/DAB1 Port E data H level Port/DA output select Data bus 2 pins AN0 to AN3 4 pins Port F PF0/AN4 to PF3/AN7 RD (Port E) Input multiplexer IP A/D converter Hi-Z Input multiplexer IP A/D converter Hi-Z Data bus 4 pins RD (Port F) - 10 - CXP87240A/87248A Pin Port F PF4/AN8 to PF7/AN11 Circuit format When reset Port F data Data bus RD (Port F) Port/AD select IP A/D converter Hi-Z 4 pins Port G PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 8 pins Port H PH0 to PH7 Schmitt input IP Input multiplexer Servo input Data bus RD (Port G) Hi-Z Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt input can be selected with the mask option. Medium withstand voltage 12V Port H data Hi-Z High current 12mA Data bus 8 pins Port I RD (Port H) Port I function select PI2: From 14-bit PWM PI3: From timer/counter, CTL duty detection circuit, 32kHz timer Port I data Port I direction Data bus PI2/PWM PI3/TO/ DDO/ADJ MPX Hi-Z IP 2 pins RD (Port I) - 11 - CXP87240A/87248A Pin Port I Port I data Circuit format When reset PI1/RMC PI4/INT1/NMI PI7/SI1 Data bus Port I direction IP RD (Port I) PI1: To remote control circuit PI4: To interruption circuit PI7: To serial CH1 Schmitt input Hi-Z 3 pins Port I Port I function select From serial CH1 Port I data Port I direction MPX Note) PI5 is schmitt input PI6 is inverter input RD (Port I) To serial CH1 PI5/SCK1 PI6/SO1 MPX Hi-Z IP Data bus 2 pins Port J Port J data PJ0 to PJ7 Port J direction IP RD (Port J) Standby release Data bus Data bus Edge detection Hi-Z 8 pins RD CS0 SI0 2 pins Schmitt input IP To SIO Hi-Z SO0 SO0 from SIO Hi-Z 1 pin SO0 output enable - 12 - CXP87240A/87248A Pin Circuit format When reset SCK0 Internal serial clock from SIO SCK0 output enable External serial clock to SIO IP Hi-Z 1 pin Schmitt input EXTAL XTAL EXTAL IP * Shows the circuit composition during oscillation. * Feedback resistor is removed during stop. Oscillation 2 pins XTAL TEX TX 32kHz timer counter TEX IP * Shows the circuit composition during oscillation. * Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs "L" level and TX pin outputs "H" level. Oscillation 2 pins TX RST Mask option Pull-up resistor Schmitt input OP IP L level 1 pin MP IP CPU mode Hi-Z 1 pin - 13 - CXP87240A/87248A Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVSS Input voltage Output voltage Medium withstand output voltage High level output current High level total output current Low level output current VIN VOUT VOUTP IOH IOH IOL IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD Rating -0.3 to +7.0 AVss to +7.01 -0.3 to +0.3 -0.3 to +7.02 -0.3 to +7.02 -0.3 to +15.0 -5 -50 15 20 130 -20 to +75 -55 to +150 600 380 mW Unit V V V V V V mA mA mA mA mA C C QFP package type LQFP package type Total of output pins PH pin Remarks (Vss=0V) Other than high current output pins: per pin High current port pin3: per pin Total of output pins 1 AVDD and VDD should be set to a same voltage. 2 VIN and VOUT should not exceed VDD + 0.3V. 3 The high current operation transistors are the N-CH transistors of the PD and PH ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. - 14 - CXP87240A/87248A Recommended Operating Conditions Item Symbol Min. 3.0 2.7 Supply voltage VDD 2.7 2.5 Analog power supply AVDD VIH VIHS High level input voltage VIHTS VIHEX 3.0 0.7VDD 0.8VDD 2.2 5.5 5.5 5.5 VDD VDD 5.5 5.5 V V V V V V V V V V V V V C Max. 5.5 5.5 V Unit Remarks (Vss = 0V) Guaranteed range during high speed mode (1/2 dividing clock) operation Guaranteed range during low speed mode. (1/16 dividing clock) operation Guaranteed operation range by TEX clock Guaranteed data hold operation range during STOP 1 2 CMOS schmitt input3 and PE0/INT0 pin CMOS schmitt input7 TTL schmitt input4 EXTAL pin5, 8 TEX pin6, 8 EXTAL pin5, 9 TEX pin6, 9 2, 8 2, 9 CMOS schmitt input3 and PE0/INT0 pin TTL schmitt input4 EXTAL pin5, 8 TEX pin6, 8 EXTAL pin5, 9 TEX pin6, 9 VDD - 0.4 VDD + 0.3 VDD - 0.2 VDD + 0.2 0.3VDD VIL Low level input voltage VILS VILTS VILEX Operating temperature 1 2 3 4 5 6 7 8 9 Topr 0 0 0 -0.3 -0.3 -20 0.2VDD 0.2VDD 0.8 0.4 0.2 +75 AVDD and VDD should be set to a same voltage. Normal input port (each pin of PC, PD, PF0 to PF3, PG, PI and PJ), MP pin. Each pin of SCK0, RST, PE1/EC/INT2, PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1. Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option) It specifies only when the external clock is input. It specifies only when the external event count clock is input. Each pin of CS0, SI0, and PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option.) When the range of supply voltage (VDD) is within 4.5 to 5.5V. When the range of supply voltage (VDD) is within 3.0 to 3.6V. - 15 - CXP87240A/87248A Electrical Characteristics DC Characteristics Supply Voltage (VDD) 4.5 to 5.5V Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE IILE Input current IIHT IILT IILR TEX RST1 PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST1 EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -20 to +75C, Vss = 0V) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 Typ. Max. Unit V V V V V A A A A A VOL I/O leakage current IIZ VDD=5.5V, VI=0, 5.5V 10 A Open drain output leakage current (N-CH Tr OFF in state) ILOH PH VDD = 5.5V VOH = 12V 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 5V 0.5V3 SLEEP mode VDD = 5V 0.5V 1.7 28 50 A IDD1 45 mA IDDS1 8 mA Supply current2 IDD2 32kHz crystal oscillation (C1 = C2 = 47pF) VDD VDD = 3V 0.3V SLEEP mode VDD = 3V 0.3V 10 30 A 40 100 A IDDS2 IDDS3 STOP mode (EXTAL and TEX pins oscillation stop) VDD = 5V 0.5V 10 A Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss 10 20 pF 1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. 2 When entire output pins are open. 3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). - 16 - CXP87240A/87248A Supply Voltage (VDD) 3.0 to 3.6V Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE IILE Input current IIHT IILT IILR TEX RST1 PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST1 PH VDD = 3.6V, VIL = 0.3V EXTAL Conditions VDD = 3.0V, IOH = -0.15mA VDD = 3.0V, IOH = -0.5mA VDD = 3.0V, IOL = 1.2mA VDD = 3.0V, IOL = 1.6mA VDD = 3.0V, IOL = 5mA VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIH = 3.6V (Ta = -20 to +75C, Vss = 0V) Min. 2.7 2.3 0.3 0.5 1.0 0.3 -0.3 0.1 -0.1 -0.9 20 -20 10 -10 -200 Typ. Max. Unit V V V V V A A A A A VOL I/O leakage current IIZ VDD = 3.6V, VI = 0, 3.6V 10 A Open drain output leakage ILOH current IDD1 VDD = 3.6V, VOH = 12V 12MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V 0.3V3 SLEEP mode 13 50 A 25 mA Supply current2 IDDS1 VDD VDD = 3.3V 0.3V STOP mode (EXTAL and TEX pins oscillation stop) VDD = 3.3V 0.3V 0.8 2.5 mA IDDS3 10 A Input capacity CIN Clock 1MHz Other than VDD, Vss, AVDD, and AVss 0V other than the measured pins 10 20 pF 1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. 2 When entire output pins are open. 3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). - 17 - CXP87240A/87248A AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times System clock frequency Event count clock input pulse width Event count clock input rise and fall times Symbol fC Pins XTAL EXTAL Fig. 1, Fig. 2 (Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V) Conditions VDD = 4.5 to 5.5V Min. 1 1 28 37.5 200 ns ns 20 32.768 10 20 ms kHz s ms Max. 16 12 ns Unit MHz tXL, tXH tCR, tCF tEH, tEL tER, tEF fC VDD = 4.5 to 5.5V Fig. 1, XTAL EXTAL Fig. 2 (External clock drive) XTAL Fig. 1, Fig. 2 EXTAL (external clock drive) EC EC TEX TX TEX TEX Fig. 3 Fig. 3 Fig. 2 VDD = 2.7 to 5.5V (32kHz clock spplied condition) Fig. 3 Fig. 3 tsys x 4 tTL, tTH tTR, tTF tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied condition Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition crystal oscillation EXTAL C1 XTAL C2 EXTAL XTAL C1 TEX TX C2 74HC04 Fig. 3. Event count clock timing 0.8VDD TEX EC 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR - 18 - CXP87240A/87248A (2) Serial transfer (CH0) Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (against SCK ) SI input hold time (against SCK ) SCK SO delay time Note 1) Symbol Pins SCK0 (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns tDCSK tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys+200 2tsys + 200 8000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc - 100 -tsys + 100 200 2tsys + 100 100 tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO means each pin of CS CS0, SCK SCK0, SI SI0, and SO SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL. - 19 - CXP87240A/87248A (2) Serial transfer (CH0) Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (against SCK ) SI input hold time (against SCK ) SCK SO delay time Note 1) Symbol Pins SCK0 (Ta = -20 to +75C, VDD = 3.0 to 3.6V, Vss = 0V) Conditions Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 250 125 ns ns tDCSK tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 200 2tsys + 200 8000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc - 150 -tsys + 100 200 2tsys + 100 100 tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO means each pin of CS CS0, SCK SCK0, SI SI0, and SO SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF. - 20 - CXP87240A/87248A Fig. 4. Serial transfer timing (CH0) tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD - 21 - CXP87240A/87248A Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (against SCK1 ) SI1 input hold time (against SCK1 ) SCK1 SO1 delay time Note 1) Symbol Pins SCK1 (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO tsys+100 8000/fc - 50 100 200 tsys + 200 100 tsys + 200 100 ns ns tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (against SCK1 ) SI1 input hold time (against SCK1 ) SCK1 SO1 delay time Note 1) Symbol Pins SCK1 (Ta = -20 to +75C, VDD = 3.0 to 3.6V, Vss = 0V) Conditions Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc - 150 100 200 tsys + 200 100 tsys + 250 125 ns ns tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF. - 22 - CXP87240A/87248A Fig. 5. Serial transfer CH1 timing (SIO mode) tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data - 23 - CXP87240A/87248A Serial transfer (CH1) (Special mode) Item SO1 cycle time SI1 data setup time SI1 data hold time Note 1) Symbol Pins SO1 SI1 SI1 SI1 (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Note 1) 2 2 Min. Typ. 104 Max. Unit s s s tLCY tLSU tLHD tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock selection) has been set at 104s. Note 2) The load of SO1 pin is 50pF + 1TTL. Serial transfer (CH1) (Special mode) Item SO1 cycle time SI1 data setup time SI1 data hold time Note 1) Symbol Pins SO1 SI1 SI1 SI1 (Ta = -20 to +75C, VDD = 3.0 to 3.6V, Vss = 0V) Conditions Note 1) 2 2 Min. Typ. 104 Max. Unit s s s tLCY tLSU tLHD tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock selection) has been set at 104s. Note 2) The load of SO1 pin is 50pF. Fig. 6. Serial transfer CH1 timing (Special mode) tLCY tLCY SO1 Start bit Output data bit 0.5VDD tLCY/2 tLSU tLHD 0.8VDD 0.2VDD SI1 input data bit - 24 - CXP87240A/87248A (3) General purpose prescaler Item External clock input frequency External clock input pulse width External clock input rise and fall times Symbol fPCK Pins SYNC1 SYNC1 SYNC1 (Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V) Conditions Min. Typ. Max. 12 33 200 Unit MHz ns ns tWH, tWL tR, tF Fig. 7. General purpose prescaler timing 1/fPCK tWH SYNC1 tF 0.8VDD 0.5VDD 0.2VDD tWL tR - 25 - CXP87240A/87248A (4) HSYNC counter Item External clock input frequency External clock input pulse width Symbol fHCK Pins SYNC1 SYNC1 SYNC1 (Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V) Conditions Min. Typ. Max. 12 33 200 unit MHz ns ns tWH, tWL tR External clock input rise/fall time tF tHLH HCOUT output delay time (against SYNC1 ) tHHL tTLH HCOUT output rise/fall time tTHL Note 1) upper 2 bits (CPU clock selection). External clock input HCOUT SYNC1 tR = tF = 6ns External clock input HCOUT SYNC1 tR = tF = 6ns tsys + 130 tsys + 220 ns tsys + 90 tsys + 150 ns 100 30 280 70 ns ns tsys indicates three values according to the contents of the clock control register (address; 00FEH) tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of HCOUT pin is 50pF. Fig. 8. HSYNC counter timing 1/fHCK tWH SYNC1 tF 0.8VDD 0.5VDD 0.2VDD tWL tHLH 0.8VDD HCOUT 0.5VDD 0.2VDD tR tHHL tTLH tTHL - 26 - CXP87240A/87248A (5) A/D converter characteristics Item Resolution Linearity error Absolute error Conversion time Sampling time Symbol (Ta = -20 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Pins Conditions Ta = 25C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Min. Typ. Max. 8 1 2 160/fADC 12/fADC AVREF AN0 to AN11 Operating mode AVREF SLEEP mode STOP mode 32kHz operating mode VDD = AVDD = 4.5 to 5.5V AVDD - 0.5 0 0.6 1.0 10 AVDD Unit Bits LSB LSB s s V V mA A tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current IREFS (Ta = -20 to +75C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V) Item Resolution Linearity error Absolute error Conversion time Sampling time Ta = 25C VDD 5.0V= AVDD = AVREF = Symbol Pins Conditions Min. Typ. Max. 8 1 2 160/fADC 12/fADC AVREF AN0 to AN11 Operating mode AVREF IREFS SLEEP mode STOP mode 32kHz operating mode VDD = AVDD = 3.0 to 3.6V AVDD - 0.3 0 0.4 0.7 10 AVDD Unit Bits LSB LSB s s V V mA A tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current Fig. 9. Definitions of A/D converter terms FFH FEH Digital conversion value The value of fADC is as follows by selecting ADC operation clock (MSC: Address 01FFH bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc VFT Analog input Linearity error 01H 00H VZT - 27 - CXP87240A/87248A (6) Interruption, reset input Item Symbol (Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V) Pins INT0 INT1 INT2 NMI PJ0 to PJ7 RST Conditions Min. Max. Unit External interruption high and low level widths tIH tIL tRSL 1 s Reset input low level width 32/fc s Fig. 10. Interruption input timing INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge) tIH tIL 0.8VDD 0.2VDD Fig. 11. Reset input timing tRSL RST 0.2VDD (7) Others Item CFG input high and low level widths Symbol Pins CFG DFG DPG DPG PBCTL EXI0 EXI1 (Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V) Conditions Min. Max. Unit ns ns ns ns ns ns tCFH tCFL tDFH DFG input tDFL high and low level widths DPG minimum pulse width tDPW DPG minimum removal time PBCTL input high and low level widths EXI input high and low level widths Note) tFRC x 24 + 200 tFRC x 16 + 200 tFRC x 8 + 200 tFRC x 16 + 200 tsys = 2000/fc tsys = 2000/fc tFRC x 8+200 + tsys tFRC x 8+200 + tsys trem tCTH tCTL tEIH tEIL tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") tFRC = 1000/fc [ns] - 28 - CXP87240A/87248A Fig. 12. Other timings tCFH tCFL 0.8VDD CFG 0.2VDD tDFH tDFL DFG 0.8VDD 0.2VDD tDPW trem trem 0.8VDD DPG tCTH tCTL 0.8VDD PBCTL 0.2VDD tEIH tEIL EXI0 EXI1 0.8VDD 0.2VDD - 29 - CXP87240A/87248A Supplement Fig. 13. Recommended oscillation circuit (i) (ii) EXTAL XTAL Rd TEX TX Rd C2 C1 C2 C1 Manufacturer Model fc (MHz) 8.00 C1 (pF) 10 C2 (pF) 10 Rd () Circuit example RIVER ELETEC CO., LTD. HC-49/U03 10.00 12.00 16.00 8.00 5 16 (12) 16 (12) 12 12 30 5 16 (12) 16 (12) 12 12 18 0 (i) HC-49/U (-S) KINSEKI LTD. 10.00 12.00 16.00 0 (i) P3 32.768kHz 470K (ii) Mask option table Item Reset pin pull-up resistor Input circuit format Non-existent Content Existent C-MOS schmitt TTL schmitt In PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin. However, TTL shmitt can not be selected when the supply voltage (VDD) ranges 3.0V to 5.5V. - 30 - CXP87240A/87248A Characteristics Curve IDD vs. VDD (fc = 16MHz, Ta = 25C, Typical) IDD vs. VDD (fc = 12MHz, Ta = 25C, Typical) 1/2 dividing mode 1/4 dividing mode 10.0 1/16 dividing mode 5.0 5.0 1/16 dividing mode 10.0 1/2 dividing mode 1/4 dividing mode IDD - Supply current [mA] IDD - Supply current [mA] SLEEP mode 1.0 0.5 32kHz mode (instruction) SLEEP mode 1.0 0.5 0.1 (100A) 0.05 (50A) 32kHz SLEEP mode 0.1 (100A) 0.05 (50A) 0.01 (10A) 0.01 (10A) 3 4 5 6 3 4 5 6 VDD - Supply voltage [V] VDD - Supply voltage [V] IDD vs. fc (VDD = 5.0V, Ta = 25C, Typical) IDD vs. fc (VDD = 3.3V, Ta = 25C, Typical) 30 30 IDD - Supply current [mA] 20 IDD - Supply current [mA] 1/2 dividing mode 20 1/2 dividing mode 1/4 dividing mode 10 1/16 dividing mode 10 1/4 dividing mode 1/16 dividing mode 0 1 5 10 15 fc - System clock [MHz] SLEEP mode 16 0 1 5 10 15 SLEEP mode 16 fc - System clock [MHz] - 31 - CXP87240A/87248A Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.1 0.15 - 0.05 23.9 0.4 + 0.4 20.0 - 0.1 + 0.4 14.0 - 0.01 17.9 0.4 15.8 0.4 A 0.65 0.12 M + 0.35 2.75 - 0.15 0.15 0 to 15 DETAIL A 0.8 0.2 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g 100PIN LQFP (PLASTIC) 16.0 0.2 75 76 14.0 0.1 51 50 100 1 0.5 0.08 + 0.08 0.18 - 0.03 25 26 (0.22) + 0.2 1.5 - 0.1 + 0.05 0.127 - 0.02 0.1 0.1 0.1 0 to 10 DETAIL A 0.5 0.2 NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 QFP100-P-1414-A - 32 - 0.5 0.2 A (15.0) |
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