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| SED1180 SED1180 CMOS LCD 64-SEGMENT DRIVER s DESCRIPTION The SED1180 is a dot matrix LCD segment (column) driver for driving high-capacity LCD panel at duty cycles higher than 1/64. The LSI contains 64-bit shift register for display data. The display data is supplied through 4-bit bus, and serially transferred through 16 x 4 bit shift register. The display data is held in a 64-bit latch circuit. The LSI converts the level of the latched data to an LCD drive waveform. The SED1180 is used in conjunction with the SED1190 (64-bit row driver) to drive a large-capacity dot matrix LCD panel. s FEATURES * Low-power CMOS technology * 64-bit segment (column) driver * High-speed 4-bit data * Duty cycle ..................................... 1/64 to 1/128 * Daisy chain enable support s SYSTEM BLOCK DIAGRAM * Wide range of LCD voltage .......... -14V to -25V * Supply voltage .................................. 5.0V 10% QFP1-80 pin (F0A) * Package ................................ QFP5-80 pin (F5A) DIE: Al pad chip (D0A) D0 ~ D3 XSCL LP, FR YSCL YD LCD CONTR SED1180 64 SED1180 64 SED1180 64 SED1180 64 SED1190 64 256 SEG x 64 COM DUTY: 1/64 425 SED1180 s BLOCK DIAGRAM 0 D0 D1 D2 D3 LP XSCL 4 1 SEG 31 LCD Driver Level Shifter Latch Shift Register 32 bits 32 bits 32 bits 32 bits 4 Voltage Control EI ECL Enable Control Shift Register Latch FR VSS VDD V2 V3 VSSH 5 Level Shifter LCD Driver 32 bits 32 bits 32 bits 32 bits EO TEST 32 33 SEG 63 s PIN CONFIGURATION 64 41 65 40 SED1180 80 25 1 24 426 SED1180 Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG 9 SEG 8 Number 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 EO D3 D2 D1 D0 XSCL LP FR SEG32 SEG33 SEG34 SEG35 Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 Number 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 VSSH V2 V3 VSS VDD TEST EI ECL SEG31 SEG30 SEG29 SEG28 s PIN DESCRIPTION Pin Name SEG0 to SEG63 XSCL LP FR EI EO ECL D0 to D3 TEST VDD, VSS V2, V3, VSSH LP falling edge. Data shift clock input: display data is shifted in on the falling edge of this signal. Latch pulse for displayed data, falling edge trigger: display data is latched on the falling edge of this signal. LCD AC-drive signal Active high daisy chain enable input Active high daisy chain enable output Daisy chain enable clock: the daisy chain enable is propagated on the falling edge of this clock. 4-bit display data input Test output Logic power inputs LCD drive power inputs VSSH: -14V to -23V VDD V2 V3 VSSH Function Outputs to segment pins of LCD. Output level changes at each latch pulse 427 SED1180 s ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage (1) Supply voltage (2) Input voltage Operating temperature Storage temperature Soldering temperature time Notes: 1. All voltage measurements are based on VDD = 0V. 2. V2 and V3 must always satisfy the condition VDD V2, V3 VSSH. 3. Exceeding the absolute maximum ratings can result in permanent damage to the device. Functional operation under these conditions is not implied. 4. Moisture resistance of flat packages can be reduced by the soldering process. Care should be taken to avoid thermally stressing the package during board assembly. Symbol VSS VSSH V2, V3 VI Topr Tstg Tsol Ratings -7.0 to +0.3 -28.0 to +0.3 VSS - 0.3 to +0.3 -20 to +75 -55 to +125 260C, 10 sec (at lead) Unit V V V C C -- 428 SED1180 s ELECTRICAL CHARACTERISTICS DC Electrical Characteristics * (VDD = 0V, VSS = -5.0 V 10%, Ta = -20 to 75C) Condition Rating Min -5.5 VSSH VSSH Recommended VSSH Operable VSSH (see note) -25.0 -25.0 0.2VSS VSS-0.3 IOH = -0.6 ma IOL = 0.6 ma 0 V VI VSS 0 V VO VSS -0.4 -- -- -- -- -- Ta = 25C VSSH = -20.0 V -- -- -- -- -- -- Typ -5.0 -- -- -- -- -- -- -- -- 0.05 0.05 -- 1/60 5.0 1.9 2.4 3.6 11.5 0.05 Max -4.5 VDD VDD -14.0 -5.0 VDD-0.3 0.8VSS -- VSS+0.4 2.0 5.0 6.0 -- 8.0 2.9 3.9 7.0 500.0 30 A k Unit V V V V V V V V V A A MHz S pF Parameters Supply voltage (1) Symbol VSS V2 V3 VSSH Supply voltage (2) HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Input leakage current Output leakage current Shift clock Frame signal Input capacitance Segment output on resistance VIH VIL VOH VOL ILI ILO XSCL FR CI RSEG VOH = VDD = -0.5 V VOL = VSSH = +0.5 V VSSH = -14.0 V SEG bit VSSH = -9.0 V VSSH = -5.0 V VSSH = -25 V, VSSH = -5.5 V, VI = VDD VSS = -5.0 V, VIH = VDD, VIL = VSS, LP cycle=130 S, Quiescent current IQ Operating current for the logic ISSO FR cycle = 16.7 ms ECL cycle = 13 S XSCL=1.5 MHz, (duty 50%) All data input reversed bit by bit. All output pins are open. VSS = -4.5 V, V2 = -4.0 V, V1 = -16.0 V, VSSH = -20.0 V, VIH = VDD, VIL = VSS, XSCL=1.5 MHz, (duty 50%), all data input reversed bit by bit. All output pins are open. -- 90 200 A Operating current for the LCD ISSHO FR cycle = 16.7 ms ECL cycle = 13 S -- 40 80 A (continued) 429 SED1180 * DC Electrical Characteristics (continued) Rating Min 166 63 63 50 30 See note 4 See note 4 See note 4 See note 4 See note 4 See note 4 See note 2 100 100 50 20 -10 70 110 220 100 0 See notes 3 & 4 See notes 3 & 4 140 50 -500 -- -- See note 4 20 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 500 See note 4 See note 4 Parameters Shift clock cycle Shift clock "H" width Shift clock "L" width Data setup time Data hold time Enable clock "H" width Enable clock "L" width Enable data setup time Enable data hold time Enable clock delay time Enable clock setup time Latch pulse "H" width Latch pulse "L" width Latch timing Latch hold time Latch pulse data setup time Latch pulse data hold time Permissible frame signal delay Input signal rise time Input signal fall time Enable output delay Notes: Symbol Condition Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- -- ns tCLC tWCLH tWCLL tDS tDH tWECH tWECL tEDS tEDH tEDR tECS tWLPH tWLPL tLT tLH tLDS tLDH tDFR tr tf tPD 150 1. While the drive is guaranteed to operate without error within this voltage range, the output resistance of the segment drivers will be higher than that in the recommended operating range. It is suggested that the drive capability of the driver under these conditions is tested using the target panel. 2. tWLPH = 160 ns (min) when LP is used as EI data. 3. tWLPH = 250 ns (min) when EO is reset by LP. 4. Applies to the SED1180F only. 5. tr, tf < (tCLC - tWCLH - tWCLL) / 2 and tr, tf 50 ns. 430 SED1180 s AC ELECTRICAL CHARACTERISTICS Data I/O Timing * 1 line period FR 1 LP Enlarged FR LP EI ECL XSCL 1 D0 to D3 EO 16 1 2 3 15 16 1 2 2 15 n 16 1 Valid Valid Valid 2 3 4 61 62 63 64 1 2 FR tWLPH LP tLDS tLT EI tEDS tr ECL tEDR tECS XSCL tWCLH tDS D0 to D3 Valid tDC EO VIH VIL tWECH Valid tEDH tr tWECL tLDH tWLPL tLH tFR VIH = 0.2 x VSS VIL = 0.8 x VSS tCLC tWCLL tDH Valid 431 SED1180 * Segment Drive Timing LP VIL FR VIH VIL tLPSD tFRSU Vn -0.5V Vn +0.5V VDO ,V2 V2, V3, VSSH SEG out VIH = 0.2VSS; VIL = 0.8VSS (VDD = 0V, VSS = -5.0 V 10%, Ta = -20 to 75C) Parameters LP-SEG output delay time FR-SEG output delay time Symbol Condition VSSH=-14.0 to -25.0 V, CL= 100 pF Rating Min -- -- Typ -- -- Max 4.5 4.5 Unit s s tLPSD tFRSD 432 SED1180 s TYPICAL SYSTEM CONNECTION (64 x 640 pixels, 1/64 duty ratio) *2 LP YSCL YD YDIS VSS VDD, V1, V4, VSS YSCL LAT DIN INH SED1190 0 COM LCD PANEL 64 x 640 Full Dot Graphic Display 63 64 127 128 SEG 0 191 SEG 0 576 639 SEG 0 VSSH FR 63 0 VDD + + R 63 SEG 0 63 63 63 V1 R V2 C+ + C SED1180 SED1180 SED1180 SED1180 1 4 EI EO FR LP VDD, VSS V2, V3 4 *1 EI 2 EO FR LP EI 3 EO FR LP EI 10 EO FR LP 5R V3 + C V4 R 100 4 4 + C VSSH FR LP ECL, XSCL D0 to D3 R *1 100 2 4 2 4 2 4 2 4 Notes: 1. Current limiting resistors 2. Bypass VSS and VSSH with capacitors of at least 0.01 F 433 SED1180 THIS PAGE INTENTIONALLY BLANK 434 |
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