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19-1356; Rev 0; 4/98
Active-Matrix Liquid Crystal Display (AMLCD) Supply
________________General Description
The MAX1664 integrates power-supply and backplane drive circuitry for active-matrix thin-film-transistor (TFT) liquid crystal displays. Included are a single-output, pulsewidth-modulation boost converter (0.25 switch), a dual-output (positive and negative) gate-driver supply using one inductor, an LCD backplane driver, and a simple phase-locked loop to synchronize all three outputs. High switching frequency (1MHz nominal) and phaselocked operation allow the use of small, minimumheight external components while maintaining low output noise. A +2.8V to +5.5V input voltage range allows operation with any logic supply. Output voltages are adjustable to +5.5V (DC-DC 1) and to +28V and -10V (DC-DC 2). The negative output voltage can be adjusted to -20V with additional components. Also included are a logic-level shutdown and a "Ready" output (RDY) that signals when all three outputs are in regulation. The boost-converter operating frequency can be set at 16, 24, or 32 times the backplane clock. This flexibility allows a high DC-DC converter frequency to be used with LCD backplane clock rates ranging from 20kHz to 72kHz. The MAX1664 is supplied in a 1.1mm-high TSSOP package.
____________________________Features
o Integrates All Active Circuitry for Three DC-DC Converters o Ultra-Small External Components (ceramic capacitors, 2H to 5H inductors) o DC-DC Converters Phase-Locked to Backplane Frequency for Lowest Noise o Low Operating Voltage (down to +2.8V) o Adjustable Output Voltage from VIN to +5.5V o Load Currents Up to 500mA o Adjustable TFT Gate Driver Output: Positive, VIN to +28V Negative, 0 to -10V (-20V with added components) o Includes 0.35 Backplane Driver o 1A Shutdown Current o Power-Ready Output Signal
MAX1664
_______________Ordering Information
PART MAX1664CUP TEMP. RANGE 0C to +70C PIN-PACKAGE 20 TSSOP
________________________Applications
LCD Modules LCD Panels
Typical Operating Circuit
VSUPPLY 2.8V TO 5.5V REF
___________________Pin Configuration
TOP VIEW
SHDN 1 RDY 2 FB1 3 REF 4 GND 5 IN 6 FB2- 7 FB2+ 8 PLLC 9 BPVSS 10 20 FPLL 19 LX1 18 PGND1 17 PGND2 28V -10V
IN FB2LX2P
INP LX1 FB1 PGND1 5.5V
MAX1664
LX2N FB2+
MAX1664
16 LX2N 15 LX2P 14 INP 13 BPCLK 12 BPVDD 11 BPDRV PLLC GND FPLL RDY BPCLK PGND2
BPVDD BPDRV BPVSS SHDN REF ON BACKPLANE DRIVER
OFF
TSSOP ________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.
Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
ABSOLUTE MAXIMUM RATINGS
RDY, IN, BPVDD to GND...........................................-0.3V to +6V FB2-, PGND1, PGND2 to GND ..........................................0.3V LX1 to PGND1 ..........................................................-0.3V to +6V BPVSS to GND .......................................................-3.3V to +0.3V BPVDD to BPVSS ......................................................-0.3V to +6V BPDRV to BPVSS ..................................-0.3V to (VBPVDD + 0.3V) LX2P to INP ............................................................-15V to +0.3V LX2N to PGND2......................................................-0.3V to +30V SHDN, INP, FB1, FB2+, REF, PLLC, BPCLK, FPLL to GND ................................-0.3V to (VIN +0.3V) RDY Sink Current ................................................................20mA LX2P, LX2N Peak Switch Currents .................................750mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 7mW/C above+70C) ..............559mW Operating Temperature Range...............................0C to +70C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VINP = 3.3V, SHDN = IN, VBPVDD = 4V, VBPVSS = -1V, PGND1 = PGND2 = FPLL = GND, fBPCLK = 30kHz, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Input Supply Range Undervoltage Lockout Threshold Quiescent Current Shutdown Current DC-DC 1 (PWM MAIN OUTPUT) Output Voltage Range Operating Frequency FB1 Regulation Voltage FB1 Input Bias Current LX1 On Resistance LX1 Leakage Current LX1 Peak Current Limit Power-Ready Trip Level DC-DC 2 (PFM) Positive Output Voltage Range Negative Output Voltage Range Maximum Operating Frequency VOUT2+ VOUT2FPLL = GND fOP2(MAX) FPLL = REF FPLL = IN VIN -10 16 x fBPCLK 12 x fBPCLK 8 x fBPCLK Hz 28 0 V V VOUT1 FPLL = GND fOP1 VFB1 IFB1 RON(LX1) ILKG(LX1) ILIM(LX1) VTH_RDY Rising edge, 2% hysteresis VLX1 = 6V 1.2 1.091 FPLL = REF FPLL = IN 0 < ILX1 < 1.2A VFB1 = 1.3V 0.25 0.1 1.5 1.125 1.2125 VIN 32 x fBPCLK 24 x fBPCLK 16 x fBPCLK 1.2500 1.275 100 0.5 10 1.8 1.159 V nA A A V Hz 5.5 V SYMBOL VIN VUVLO IQ ISD VFB1+ = VFB2+ = 1.3V, VFB2- = -0.1V; IIN + IINP SHDN = GND, VIN = 5.5V; IIN + IINP CONDITIONS MIN 2.8 2.5 0.5 0.01 TYP MAX 5.5 2.8 2 10 UNITS V V mA A
2
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Active-Matrix Liquid Crystal Display (AMLCD) Supply
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VINP = 3.3V, SHDN = IN, VBPVDD = 4V, VBPVSS = -1V, PGND1 = PGND2 = FPLL = GND, fBPCLK = 30kHz, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER FB2+ Regulation Voltage FB2- Regulation Voltage FB2+, FB2- Input Bias Current LX2N, LX2P On-Resistance LX2N, LX2P Leakage Current FB2- Power-Ready Trip Level FB2+ Power-Ready Trip Level BACKPLANE DRIVER BPVDD Supply Range BPVSS Supply Range BPVDD to BPVSS Voltage Range BPVDD Shutdown Current BPDRV On-Resistance BPDRV Leakage Current BPVDD Supply Current BPCLK Input Low Voltage BPCLK Input High Voltage BPCLK Input Current PLL VCO Center Frequency (Note 1) BPCLK Input Frequency Range Reference Voltage Undervoltage Lockout LOGIC SIGNALS SHDN Input Low Voltage SHDN Input High Voltage SHDN Input Current FPLL Input Current RDY Output Low Voltage RDY Output High Leakage VIL(SHDN) VIH(SHDN) IIN(SHDN) IIN(FPLL) VOL(RDY) FPLL = GND or IN ISINK = 2mA (0.10 x VIN) typical hysteresis 0.7 x VIN 0.01 0.01 0.05 0.01 1 1 0.4 1 0.3 x VIN V V A A V A fC PLLC = REF, BPCLK = GND CPLLC = 22nF RPLLC = 100k CSHUNT = 2.2nF -2A < IREF < 50A FPLL = GND FPLL = REF FPLL = IN 1.63 20 27 40 1.225 0.90 1.250 1.05 1.92 2.20 36 48 72 1.275 1.20 V V kHz MHz VBPVDD VBPVSS VVDD to VSS ISHDN(BP) RON(BPDRV) IIN(BPVDD) VIL(BPCLK) VIH(BPCLK) IIN(BPCLK) 0.7 x VIN 0.01 1 SHDN = GND Source and sink -10 80 VBPCLK = 0 or 3.3V 2.5 -3 2.5 0.1 0.35 5.5 0 5.5 10 0.7 10 200 0.3 x VIN V V V A A A V V A SYMBOL VFB2+ VFB2IFB2+, IFB2RON(LX2N), RON(LX2P) ILKG(LX2N), ILKG(LX2P) VTH(RDY) VTH(RDY) VLX2N = 28V, VLX2P = -10V Falling edge, 40mV hysteresis Rising edge, 40mV hysteresis 85 1.091 VFB2+ = 1.3V, VFB2- = -0.1V CONDITIONS MIN 1.225 -15 -100 0.9 0.05 120 1.125 TYP 1.25 0 MAX 1.275 15 100 1.7 10 165 1.159 UNITS V mV nA A mV V
MAX1664
ILKG(BPDRV) SHDN = GND
fBPCLK VREF VREF(UVLO)
ILKG(RDYOH) VRDY = 5.5V
Note 1: DC-DC 1 operates at one-half of the VCO frequency (fC / 2).
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Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
__________________________________________Typical Operating Characteristics
(fBPCLK = 22.5kHz, FPLL = GND, L1 = 3.3H, L2 = 4.7H, TA = +25C, unless otherwise noted.)
DC-DC 1 EFFICIENCY vs. LOAD CURRENT (VOUT1 = +5V)
MAX1664 TOC01
DC-DC 2 EFFICIENCY vs. LOAD CURRENT (VOUT2- = -5V)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VIN = 5V VIN = 3.3V VOUT2+ UNLOADED
MAX1664 TOC02
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 10 100 VIN = 4.5V VIN = 3V
100
1000
1
10 LOAD CURRENT (mA)
100
LOAD CURRENT (mA)
DC-DC 2 EFFICIENCY vs. LOAD CURRENT (VOUT2+ = +15V)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 10 LOAD CURRENT (mA) VOUT2- UNLOADED 100 VIN = 3.3V VIN = 5V
MAX1664 TOC03
VOUT1 RIPPLE
MAX1664 TOC04
100
10mV/div
500ns/div IOUT1 = 250mA, L = 3.3H
VOUT2+ RIPPLE
MAX1664 TOC05
VOUT2- RIPPLE
MAX1664 TOC06
VOUT2
100mV/ div
VOUT2-
50mV/ div
2s/div VOUT2+ = 15V, VIN = 3.3V, ILOAD = 9mA, COUT2 = 0.22F, AC COUPLED
5s/div VOUT2- = -5V, VIN = 3.3V, ILOAD = 5mA, COUT2- = 0.47F, AC COUPLED
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Active-Matrix Liquid Crystal Display (AMLCD) Supply
Typical Operating Characteristics (continued)
(fBPCLK = 22.5kHz, FPLL = GND, L1 = 3.3H, L2 = 4.7H, TA = +25C, unless otherwise noted.)
VOUT1 LINE-TRANSIENT RESPONSE
MAX1664 TOC07
MAX1664
VOUT2+ LINE-TRANSIENT RESPONSE
MAX1664 TOC08
A
50mV/ div
A
200mV/ div
B
500mV/ div
B
500mV/ div
2ms/div VOUT1 = 5V, ILOAD = 250mA, COUT1 = 20F A: VOUT1, 50mV/div, AC COUPLED B: VIN, 3V to 4V
2ms/div VOUT2+ = 15V, ILOAD = 5mA, COUT2+ = 0.22F A: VOUT2+, 200mV/div, AC COUPLED B: VIN, 3V to 4V
VOUT2- LINE-TRANSIENT RESPONSE
MAX1664 TOC09
VOUT1 LOAD-TRANSIENT RESPONSE
MAX1664 TOC10
A
200mV/ div
A
50mV/ div
B
500mV/ div
B
100mA/ div
2ms/div VOUT2- = -5V, ILOAD = 5mA, COUT2- = 0.47F A: VOUT2-, 200mV/div, AC COUPLED B: VIN, 3V to 4V
2ms/div VOUT1 = 5V, VIN = 3.3V, COUT1 = 20F A: VOUT1, 50mV/div, AC COUPLED B: IOUT1, 25mA TO 225mA, 100mA/div
INTERNAL FET ON-RESISTANCE vs. TEMPERATURE
INTERNAL FET ON-RESISTANCE (m)
MAX1664 TOC 11
BPDRV RISE AND FALL TIME vs. LOAD CAPACITANCE
MAX1664 TOC12
1400 1200 1000 800 600 400 200 LX1 0 0 10 20 30 40 50 60 70 80 BPDRV P-CHANNEL LX2P LX2N
300 250 RISE/FALL TIME (ns) 200 RISE TIME 150 100 50 0 0.001 CLOAD FROM BPDRV TO GND 0.01 0.1 1 FALL TIME
BPDRV N-CHANNEL
90
TEMPERATURE (C)
LOAD CAPACITANCE (F)
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Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
Typical Operating Characteristics (continued)
(fBPCLK = 22.5kHz, FPLL = GND, L1 = 3.3H, L2 = 4.7H, TA = +25C, unless otherwise noted.)
BPCLK TO BPDRV FALLING DELAY
MAX1664 TOC14
BPCLK TO BPDRV RISING DELAY
MAX1664 TOC14(a))
2V/div
BPDRV 5V/div BPCLK 2V/div BPDRV BPCLK 5V/div
100ns/div CLOAD = 10,000pF CLOAD = 10,000pF
100ns/div
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX1664 TOC15
OUT-OF-SHUTDOWN SEQUENCE
MAX1664 TOC16(a)
1.8 NO-LOAD SUPPLY CURRENT (mA) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 INPUT VOLTAGE (V) INCLUDES ALL EXTERNAL COMPONENT CURRENTS
5V/div SHDN VREF VOUT1 VOUT25V/div 2V/div 5V/div
10V/div VOUT2+ RDY 500s/div
5V/div
DC-DC 1 SWITCHING WAVEFORMS
MAX1664 TOC17(a)
DC-DC 2 SWITCHING WAVEFORMS DISCONTINUOUS CONDUCTION
VLX1
5V/div VLX2N
5V/div 5V/div
VLX2P ILI 500mA/div IL2 500mA/ div 1s/div VIN = 3.3V; VOUT2+ = 15V/8mA, VOUT2- = -5V/10mA NOTE: LX2N, LX2P PULSES ARE SYNCHED TO DC-DC 1
500ns/div IOUT1 = 300mA, L1 = 3.3H
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Active-Matrix Liquid Crystal Display (AMLCD) Supply
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME SHDN RDY FB1 REF GND IN FB2FB2+ PLLC BPVSS BPDRV BPVDD BPCLK INP LX2P LX2N PGND2 PGND1 LX1 FPLL FUNCTION Shutdown Input. Drive low to enter shutdown mode. Drive high or connect to IN for normal operation. All IC sections are off when SHDN is low. Ready Indicator Output, DC-DC 1 and DC-DC 2. Open-drain N-channel output becomes high impedance when all three outputs are within 10% of regulation. Regulator Feedback Input, DC-DC 1. Regulates to 1.25V nominal. Internal Reference Output. Connect a 0.22F capacitor from this pin to GND. REF can source up to 50A. Analog Ground. Connect to PGND1 and PGND2. See Supply Connections and Layout section. Supply Input to the IC. The input voltage range is +2.8V to +5.5V. Regulator Feedback Input for Negative Output, DC-DC 2. Regulates to 0V nominal. Regulator Feedback Input for Positive Output, DC-DC 2. Regulates to 1.25V nominal. PLL Compensation. Connect compensation network as in Figure 4. Backplane Driver Negative Supply. Typically connected to PGND1. May be connected to a separate supply. Backplane Driver Output Backplane Driver Positive Supply. Typically connected to VOUT1 of DC-DC 1. May be connected to a separate supply. Backplane Driver Clock Input. See Table 1 for input frequency ranges. DC-DC 2 Power Input. Source of Internal LX2P P-channel MOSFET. Drain of Internal LX2P P-Channel MOSFET Drain of Internal LX2N N-Channel MOSFET Power Ground 2. Connect to PGND1. Source of internal LX2N N-channel MOSFET. Power Ground 1. Connect to PGND2. Source of internal LX1 N-channel MOSFET. Drain of Internal LX1 N-Channel MOSFET Sets the BPCLK input frequency range for PLL synchronization. Connect to GND, REF, or IN. See Table 1.
MAX1664
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Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
REF INP FB2IN VSUPPLY 2.8V TO 5.5V
MAX1664
VOUT2-10V LX2P DC-DC 2 VOUT2+ 28V DC-DC 1
LX1
VOUT1 5.5V
FB1
LX2N PGND1 FB2+ BPVDD PGND2
/4
PLLC
/2
BPDRV
BACKPLANE DRIVER
BPVSS BPCLK PHASE DET FPLL VCO 1.25V REF SHDN
/N
RDY IN REF GND
GND
REF
Figure 1. Functional Diagram
_______________Detailed Description
The MAX1664 combines power supply and backplane drive circuitry for active matrix thin-film-transistor (TFT) liquid crystal displays (LCD) into one IC. Included are a pulse-width-modulation (PWM) boost converter, a dualoutput (positive and negative) converter using one inductor, an LCD backplane driver, and a phaselocked loop (PLL) to synchronize all three outputs to the backplane clock. A high switching frequency (1MHz nominal) and phaselocked operation allow the use of small, minimumheight external components while maintaining low output noise. Output voltages are adjustable to +5.5V (DC-DC 1) and to +28V and -10V (DC-DC 2). The negative output voltage can be set to as low as -20V with additional components. The frequency ratio between the DC-DC 1 converter and the backplane clock can be set to 16, 24, or 32. This flexibility allows high DC-DC converter frequencies
to be used with LCD backplane clock rates ranging from 20kHz to 72kHz.
Start-Up
At start-up, both converters remain disabled until VREF reaches 90% of its nominal value. VOUT1 is activated first. Once V OUT1 is regulated, V OUT2- is enabled. VOUT2+ is held at 0 until VOUT2- is within 90% of its regulation target. All three outputs power up in a similar order when power is applied or when coming out of shutdown. See the Out-of-Shutdown Sequence photo in the Typical Operating Characteristics section.
DC-DC 1 Boost Converter
DC-DC 1 uses a current-mode boost PWM architecture to produce a positive regulated voltage, adjustable from 3V to 5.5V (but not less than VIN). This converter uses an internal N-channel MOSFET with a maximum on-resistance of 0.5. Cycle-by-cycle peak current limiting protects the switch under fault conditions. Upon start-up, DC-DC 1 is the first converter to be enabled.
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Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
Table 1. Switching Frequency Options
FPLL IN REF GND *See Figure 2 fBPCLK (kHz) 40 to 72 27 to 48 20 to 36 fDC-DC 1 (kHz) 640 to 1152 640 to 1152 640 to 1152 fDC-DC 2 MAX (kHz) 320 to 576 320 to 576 320 to 576 fDC-DC 1: fBPCLK 16:1 24:1 32:1 fDC-DC 2 MAX: fBPCLK 8:1 12:1 16:1 N* 32 48 64
Fixed-frequency, current-mode operation ensures that the switching noise exists only at the operating frequency and its harmonics. The switching frequency is phase locked to the backplane clock input. Table 1 illustrates the possible switching-frequency options.
loads, the controller may skip one or more cycles of either polarity, thereby keeping the outputs in regulation. See Table 1 for the relationship between the maximum DC-DC 2 pulse frequency and the backplane clock frequency.
DC-DC 2 Dual Outputs
DC-DC 2 uses a synchronized, fixed on-time PFM architecture to provide the positive and negative output voltages that allow the driver ICs to turn the TFT gates on and off. When pulses occur, they are synchronized to DC-DC 1, thereby minimizing converter interactions and subharmonic interference. The DC-DC 2 inductor current is always discontinuous, enabling the dual outputs to be regulated independently. This allows one output to be at 100% load while the other is at no load.
Outputs with Low Step-Up or Inversion Ratios For DC-DC 2 output voltage setpoints, which require minimum step-up or inversion ratios (for example, VOUT+ < 6V or VOUT- > -3V, when VINP = 5V), more than one half-cycle may be required to transfer the inductor energy to the appropriate output filter capacitor. In such cases, subsequent conversion cycles are delayed, as necessary, by one or more PFM clock cycles to preserve discontinuous mode operation.
Backplane Driver
The MAX1664 provides a low-impedance backplane driver, as shown in Figure 1, that level-translates the BPCLK signal from a logic level to BPVDD/BPVSS levels. The backplane driver consists of an N-channel/P-channel complementary pair of high-current MOSFETs. These devices drive BPDRV to either BPVDD or BPVSS when BPCLK goes either high or low, respectively. The switches have a maximum on-resistance of 0.7 with a typical propagation delay of 50ns. Power for the backplane driver can be taken from the output of DC-DC 1, VOUT1, as shown in the Typical Operating Circuit.
DC-DC 2 Operation In normal operation, DC-DC 2 alternates between charging the negative and positive outputs (Figure 1). During the first half-cycle of the PFM clock period, both the N-channel and P-channel MOSFETs turn on, applying the input supply across inductor L2. This causes the inductor current to ramp up at a rate proportional to V INP . During the second half-cycle, the P-channel MOSFET turns off and the inductor transfers its energy into the negative output filter capacitor. Assuming that the energy transfer is completed during this second half-cycle and the inductor current ramps down to zero, the process is repeated for the positive output during the next clock cycle. During the first half of the second clock cycle, both the N-channel and Pchannel MOSFETs turn on again. The current in the inductor again rises at the same rate. During the second half of the second clock cycle, the N-channel MOSFET is turned off and this time the inductor energy transfers to the positive output filter capacitor. During conditions of heavy loads, DC-DC 2 will continue to operate in this manner, alternately delivering pulses to the negative and positive outputs. For lighter
Phase-Locked Loop
The MAX1664 contains an on-board PLL to synchronize the PWM and PFM converter clocks to the backplane clock (Figure 2). This will minimize noise and interference. The PLL is a frequency-multiplying type, generating a nominal 1MHz clock signal for DC-DC 1 and a nominal 500kHz clock for DC-DC 2. Three input frequency ranges, spanning 20kHz to 72kHz, permit synchronization over a broad range of backplane clock input frequencies while maintaining optimal conversion frequencies (Table 1).
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9
Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
PHASE DETECTOR CSHUNT PLLC VCO RPLLC CPLLC /N* /4 DC-DC 2 /2
REF R5
DC-DC 1
VOUT1
MAX1664
VOUT2+ R6 R7 VOUT2FB2+ BPDRV CC FB2FB1 CFB1
R1 BPVDD R2 R3 DC BIAS R4 BPVSS
BPCLK
R8
*SEE TABLE 1 FOR SELECTED VALUES OF N. IN REF GND
Figure 2. Internal PLL Operation within the MAX1664 Figure 3. Output Voltage Selection
The heart of the PLL is the VCO, which is trimmed to a nominal frequency of 1.92MHz for a control voltage (at the PLLC pin) of 1.250V. This high-frequency internal clock is divided digitally with a division ratio selected by pin-strapping FPLL to GND, REF, or IN. This divided clock is compared to the backplane clock by an internal phase comparator (rising-edge triggered). The phase detector in turn adjusts the VCO control voltage until the two frequencies (and phases) match. This feedback loop is compensated at the PLLC pin. In some applications, the backplane clock may be halted for several cycles between screen scans or may not be immediately applied on power-up. The PLL contains a proprietary phase-detector architecture that minimizes frequency error during clock dropouts of more than two cycles and re-establishes lock immediately when the clock resumes.
DC-DC 1 Output For VOUT1 = 5V, typical values are R2 = 100k and R1 = 301k. To set VOUT1 to another voltage, choose R2 = 100k and CFB1 = 50pF, and calculate R1 as follows:
V R1 = R2 OUT1 - 1 VFB1
DC-DC 2 Positive Output For VOUT2+ = 15V, typical values are R8 = 49.9k and R7 = 549k. To set VOUT2+ to another voltage, choose R8 = 49.9k and calculate R7 as follows:
V R7 = R8 OUT2 + - 1 VFB2 +
Ready Indicator (RDY)
The RDY pin has an open-drain output and indicates when all three outputs are in regulation. The open-drain output becomes high impedance when all three converter outputs are within 10% of their regulation setpoints.
DC-DC 2 Negative Output For the negative output voltage, the FB2- threshold voltage is 0. For VOUT2- = -5V, typical values are R5 = 49.9k and R6 = 200k. To set VOUT2+ to another voltage, choose R5 = 49.9k and calculate R6 as follows:
R6 = R5 VOUT2VREF
Design Procedure and ______________Component Selection
Output Voltage Selection
The three output voltages as well as the DC bias for the backplane clock are adjustable on the MAX1664, as shown in Figure 3. Set each output using two standard 1% resistors to form a voltage divider between the selected output and its respective feedback pin. Use the following equations to calculate the resistances.
DC Bias for the Backplane Driver For VDCBIAS = VBPVDD/2, typical values are R3 = R4 = 100k. To set the DC bias to a different value, choose R4 and calculate R3 as follows:
V - VBPVSS R3 = R4 BPVDD VDCBIAS - VBPVSS - 1
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Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
REF R5 49.9k R6 200k LX2P 0.47F 0.22F VOUT2+ 15V R7 D3 549k FB2+ R8 49.9k PGND2 BPDRV 2 x 10F PLLC 2.2nF 100k 22nF BPCLK RDY GND FPLL SHDN REF 0.22F ON OFF BPVSS R4 100k BPVDD 10F R3 100k D2 L2 4.7H FB1 50pF R2 100k 0.47F IN FB2VOUT2-5V 33 VSUPPLY 2.8V TO 5.5V 2.2F INP LX1 3 x 10F R1 301k VOUT1 5.5V 10F 3.3H 2.2F
MAX1664
PGND1 LX2N
BACKPLANE DRIVER
Figure 4. Detailed Typical Operating Circuit
Inductor Selection
The optimum inductor value for L1 is 3.3H, as shown in Figure 4. Inductors with less than 300m DC series resistance are recommended to achieve the highest efficiency. Using a larger value for L1 (e.g., 4.7H) increases the output current capability of DC-DC 1 (by reducing the peak ripple current) at the expense of size and the additional output filter capacitance needed for loop stability. For DC-DC 2, at large input voltages (i.e., 5V) and low switching frequencies (i.e., 400kHz), the value of L2 should be increased (e.g., 6.8H or 10H) to limit the peak current. In some cases it may be necessary to reduce the value of L2 to increase the output current capability of DC-DC 2 (Table 2). The relationship between input voltage, output voltage, switching frequency, inductor value, and maximum load current for DC-DC 2 is complex and nonlinear. This relationship is summarized in Table 2. The L2 equation is as follows: L2 >
VINP - RON(LX2P) + RON(LX2N) + RL2 IPEAK x 2 fDC-DC 1
[
(
)
] (I 2
PEAK )
where: Internal MOSFET on-resistance: RON(LX2P) = RON(LX2N) = 0.9 typical External inductor DC resistance: RL2 = 0.3 typical Inductor peak current: IPEAK = 700mA (750mA absolute maximum) Due to the MAX1664's high switching frequency, inductors with a high-frequency core material such as ferrite are recommended. Powdered iron compounds are not recommended due to their higher core losses. Typical small-size, low-profile inductors include the ILS-3825 (Dale Electronics-Vishay) and the CLQ61B (Sumida). These inductors are primarily used for DC-DC converters with low height requirements. See Table 3 for more information on manufacturers who provide low-profile inductors.
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Active Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
Table 2. Typical DC-DC 2 Operation
VOUT2+ (V) +15 +15 +15 +15 +15 +15 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 VOUT2(V) -5 -5 -5 -5 -5 -5 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 VIN (V) 3.0 3.0 3.3 3.3 4.5 5.0 3.0 3.0 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 3.3 3.3 4.5 4.5 4.5 4.5 5.0 5.0 5.0 fBPCLK (kHz) 22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 25.0 25.0 30.0 30.0 22.5 22.5 25.0 25.0 30.0 30.0 22.5 25.0 30.0 30.0 22.5 25.0 30.0 L2 (H) 4.7 2.7 4.7 2.7 4.7 4.7 4.7 2.7 4.7 2.7 4.7 2.7 4.7 2.7 4.7 2.7 4.7 4.7 4.7 4.7 4.7 2.7 4.7 4.7 4.7 IOUT2+(MAX) (mA) 6 8 7 10 15 20 3 5 2 4 3 3 4 6 4 6 4 4 9 8 8 10 11 10 10 IOUT2-(MAX) (mA) 15 23 19 27 35 43 6 10 5 8 4 6 8 12 7 10 5 8 16 14 12 17 20 18 15 fDC-DC 2(MAX) (kHz) 360 360 360 360 360 360 360 360 400 400 480 480 360 360 400 400 480 480 360 400 480 480 360 400 480 INDUCTOR PEAK CURRENT* (mA) 375 585 425 643 550 600 385 585 340 530 300 451 425 643 370 583 340 496 580 500 450 679 640 550 500
*Note: Absolute maximum peak current at LX2P and LX2N is 750mA.
Diode Selection
The MAX1664's high switching frequency requires fast diodes. Schottky diodes such as the MBR0520L and MBR0540L (Motorola) are recommended because they have the necessary power ratings in a low-height SOD123 package. Also recommended is the MBRM5817 which is 1.1mm high. Use a Schottky diode with a forward current rating greater than: I V IF > OUT OUT 0.9VIN For the positive output of DC-DC 2, use a Schottky diode with a voltage rating that exceeds VOUT2+. For the negative output, use a Schottky diode with a rating
that exceeds VIN + V OUT2-. See Table 3 for more information on Schottky diode manufacturers.
Filter Capacitor Selection
An output filter capacitor's ESR and size can greatly influence a switching converter's output ripple, as shown in the following equation. t VRIPPLE(PK - PK) IPEAK x RESR + IOUT ON C OUT DC - DC 1 tON = VOUT1 + VF - VIN fDC -DC 1 VOUT1 + VF 1 DC - DC 2 tON = 2 fDC -DC 1 1
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Active-Matrix Liquid Crystal Display (AMLCD) Supply
Ceramic capacitors are recommended because they have low ESR and the lowest profile. Typical ceramic capacitors are the C3225X5R series from TDK and JMK325 series from Taiyo Yuden. See Table 3 for more information on the manufacturers who provide surfacemount ceramic capacitors.
MAX1664
33 0.47F 3.3H IN INP D1 LX1 D2 V1 C1 3.3F (x2)
VSUPPLY 2.8V TO 3.6V
PLL Compensation
In most applications, the recommended compensation component values shown in Figure 4 will give optimal system performance. If no backplane clock is used, connect PLLC to REF.
C2 3.3F (x2) 10V 150mA C4 3.3F (x2) FB1 D3 R1 91k C3 3.3F (x6)
Table 3. Component Manufacturers
MANUFACTURER INDUCTORS Dale Inductors Sumida USA DIODES Central Semiconductor International Rectifier Motorola CERAMIC CAPACITORS Marcon/United Chemicon TDK Taiyo Yuden Vishay/Vitramon (847) 696-2000 (847) 390-4373 (408) 573-4150 (203) 268-6261 (847) 696-9278 (847) 390-4428 (408) 573-4159 (203) 452-5670 (516) 435-1110 (310) 322-3331 (602) 303-5454 (516) 435-1824 (310) 322-3232 (602) 994-6430 (605) 668-4131 (847) 956-0666 (605) 665-1627 (847) 956-0702 PHONE FAX
MAX1664
50pF PGND1
R2 13k
D1, D2, D3-- MBRM5817 C1, C2, C3--ALL CERAMIC TYPES
Figure 5. Charge Pump Configuration to Increase VOUT1 Above 5.5V.
COUT are 0.47F to 1F and 4.7F to 10F, respectively. As a general rule, COUT should be ten times greater than CF. This circuit operates as follows: 1) During the first PFM cycle, the voltage at V1 is charged by inductor L2 to some fraction of its final steady-state voltage, in the normal manner described in the Detailed Description. 2) During the first half of subsequent PFM cycles, pin LX2P is pulled to VINP, and capacitor CF is charged to (VINP +V1 - VD), where VD is a diode forward voltage. 3) During subsequent second half-cycles when LX2P flies negatively below V1, capacitor C F transfers some of its energy to output capacitor COUT, which then is charged to a negative voltage of approximately (VINP + 2 x V1 - 2x VD). 4) This process continues until V OUT reaches the desired voltage, as determined by the ratio of the FB2- feedback resistors. 5) During steady-state (in-regulation) operation, the magnitude of the voltage at LX2P is equal to (VOUT / 2 - VINP / 2 + VD), which must be limited to less than 10V.
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_____________Applications Information
Increasing VOUT Above 5.5V
For VOUT1 output voltages above 5.5V, connect the supplemental charge pump circuit shown in Figure 5. The connection shown supplies a 10V 150mA output, but other voltages from 2 x VIN to 10V can be set by selecting the appropriate values for R1 and R2 (see DC-DC 1 Output section). C2-C4 are shown as parallel combinations of 3.3F ceramic capacitors so that a 1.1mm height restriction can be met. If height is not restricted, then larger values can be used instead of parallel capacitor combinations.
3.3V to -20V Charge-Pump Configuration
For applications requiring negative voltages down to -20V, an inverting charge-pump block can be added to the VOUT2- output (Figure 6). Typical values for CF and
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Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
Supply Connections and Layout
The MAX1664 performs both precision analog and high-power switching functions. Carefully plan supply connections, bypassing, and layout. Bypass IN and INP with a 33 isolation resistor (R9, Figure 4) between them. In addition, sufficient low-ESR bypassing must be provided on the INP bus to ensure stability of DC-DC 1. A solid ground plane under the power components, with a separate ground plane under the analog nodes, is highly recommended. These ground planes should be connected at a single, quiet point. Analog reference and feedback signals should be referred to and routed over the analog ground plane. Figure 7 shows a typical layout using separate ground planes.
REF R5 FB2R6 VOUT2-20V COUT 4.7F D5 CF
MAX1664
D4
V1 0.47F 0.22F VOUT2+ 28V R7
LX2P D2 L2
LX2N D3 FB2+ R8 PGND2
Figure 6. VOUT2- Voltage-Doubler Charge Pump
1.0"
1.0"
Figure 7a. MAX1664 Component Placement Guide
Figure 7b. MAX1664 PC Board Layout--Component Side
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Active-Matrix Liquid Crystal Display (AMLCD) Supply
___________________Chip Information
TRANSISTOR COUNT: 838
MAX1664
1.0"
Figure 7c. MAX1664 PC Board Layout--Solder Side
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Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664
________________________________________________________Package Information
TSSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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