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L6917B
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER
s s s s s s s s s
s s s s s
2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD TRANSIENT RESPONSE INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT TTL-COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT COMPLIANT WITH VRM 9.0 0.8% INTERNAL REFERENCE ACCURACY 10% ACTIVE CURRENT SHARING ACCURACY DIGITAL 2048 STEP SOFT-START OVERVOLTAGE PROTECTION OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S R dsON OR A SENSE RESISTOR 300 kHz INTERNAL OSCILLATOR OSCILLATOR EXTERNALLY ADJUSTABLE UP TO 600kHz POWER GOOD OUTPUT AND INHIBIT FUNCTION REMOTE SENSE BUFFER PACKAGE: SO-28
SO-28 ORDERING NUMBERS:L6917BD L6917BDTR (Tape & Reel)
APPLICATIONS s POWER SUPPLY FOR SERVERS AND WORKSTATIONS s POWER SUPPLY FOR HIGH CURRENT MICROPROCESSORS s DISTRIBUTED DC-DC CONVERTERS BLOCK DIAGRAM
ROSC / INH
DESCRIPTION The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. The device implements a dual-phase step-down controller with a 180 phase-shift between each phase. A precise 5-bit digital to analog converter (DAC) allows adjusting the output voltage from 1.100V to 1.850V with 25mV binary steps. The high precision internal reference assures the selected output voltage to be within 0.8%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load over current and load over/under voltage. An internal crowbar is provided turning on the low side mosfet if an over-voltage is detected. In case of over-current, the system works in Constant Current mode.
SGND
VCCDR BOOT1
LOGIC PWM ADAPTIVE ANTI CROSS-CONDUCTION
PGOOD
2 PHASE OSCILLATOR PWM1
UGATE1 HS PHASE1
CURRENT CORRECTION
+
DIGITAL SOFT START
CH 1 OVER CURRENT
LGATE1 LS ISEN1
VCC VCCDR LOGIC AND PROTECTIONS
TOTAL CURRENT
+
<>
CURRENT READING
PGNDS1 PGND
VID4 VID3 VID2 VID1 VID0
CH1 OVER CURRENT AVG CURRENT
DAC
CH2 OVER CURRENT
CURRENT READING
PGNDS2
ISEN2 LOGIC PWM ADAPTIVE ANTI CROSS-CONDUCTION
CH 2 OVER CURRENT
LGATE2 LS
10k 10k 10k REMOTE BUFFER
+
IFB
FBG FBR
CURRENT CORRECTION
ERROR AMPLIFIER
PHASE2
PWM2
UGATE2 HS
10k
Vcc
BOOT2
VSEN
FB
COMP
Vcc
September 2002
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L6917B
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc, VCCDR VBOOT-VPHASE VUGATE1-VPHASE1 VUGATE2-VPHASE2 LGATE1, PHASE1, LGATE2, PHASE2 to PGND All other pins to PGND Vphase Sustainable Peak Voltage t < 20ns @ 600kHz to PGND Boot Voltage Parameter Value 15 15 15 Unit V V V
-0.3 to Vcc+0.3 -0.3 to 7 26
V V V
THERMAL DATA
Symbol Rth j-amb Tmax Tstorage Tj PMAX Parameter Thermal Resistance Junction to Ambient Maximum junction temperature Storage temperature range Junction Temperature Range Max power dissipation at Tamb = 25C Value 60 150 -40 to 150 -25 to 125 2 Unit C/W C C C W
PIN CONNECTION
LGATE1 VCCDR PHASE1 UGATE1 BOOT1 VCC GND COMP FB VSEN FBR FBG ISEN1 PGNDS1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SO28
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PGND LGATE2 PHASE2 UGATE2 BOOT2 PGOOD VID4 VID3 VID2 VID1 VID0 OSC / INH / FAULT ISEN2 PGNDS2
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L6917B
ELECTRICAL CHARACTERISTICS VCC = 12V 10%, TJ = 0 to 70C unless otherwise specified
Symbol Parameter Test Condition Min Typ Max Unit
Vcc SUPPLY CURRENT ICC ICCDR IBOOTx Vcc supply current VCCDR supply current Boot supply current HGATEx and LGATEx open VCCDR=VBOOT=12V LGATEx open; VCCDR=12V HGATEx open; PHASEx to PGND VCC=VBOOT=12V 7.5 2 0.5 10 3 1 12.5 4 1.5 mA mA mA
POWER-ON Turn-On VCC threshold Turn-Off VCC threshold Turn-On VCCDR Threshold Turn-Off VCCDR Threshold OSCILLATOR/INHIBIT/FAULT fOSC Initial Accuracy OSC = OPEN OSC = OPEN; Tj=0C to 125C RT to GND=74k ISINK=5mA OSC = OPEN 278 270 450 0.8 70 1.8 OVP or UVP Active 4.75 300 500 0.85 75 2 5.0 2.2 5.25 322 330 550 0.9 kHz kHz kHz V % V V VCC Rising; VCCDR=5V VCC Falling; VCCDR=5V VCCDR Rising VCC=12V VCCDR Falling VCC=12V 7.8 6.5 4.2 9 7.5 4.4 10.2 8.5 4.6 V V V
4.0
4.2
4.4
V
fOSC,Rosc Total Accuracy INH dMAX Vosc FAULT Inhibit threshold Maximum duty cycle Ramp Amplitude Voltage at pin OSC
REFERENCE AND DAC Output Voltage Accuracy IDAC VID pull-up Current VID pull-up Voltage ERROR AMPLIFIER DC Gain SR Slew-Rate COMP=10pF 80 15 dB V/s VID0, VID1, VID2, VID3, VID4 see Table1; FBR = VOUT; FBG = GND VIDx = GND VIDx = OPEN -0.8 0.8 %
4 3.1
5 -
6 3.4
A V
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER) DC Gain CMRR Common Mode Rejection Ratio 1 40 V/V dB
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L6917B
ELECTRICAL CHARACTERISTICS (continued) VCC = 12V 10%, TJ = 0 to 70C unless otherwise specified
Symbol Parameter Input Offset SR Slew Rate Test Condition FBR=1.100V to1.850V; FBG=GND VSEN=10pF Min -12 15 Typ Max 12 Unit mV V/s
DIFFERENTIAL CURRENT SENSING IISEN1, IISEN2 IPGNDSx IISEN1, IISEN2 IFB Bias Current Iload=0 45 50 55 A A A A A
Bias Current Bias Current at Over Current Threshold Active Droop Current Iload<0% Iload=100%
45 80
50 85
55 90
47.5
0 50
1 52.5
GATE DRIVERS tRISE HGATE IHGATEx RHGATEx tRISE LGATE ILGATEx RLGATEx High Side Rise Time High Side Source Current High Side Sink Resistance Low Side Rise Time Low Side Source Current Low Side Sink Resistance VBOOTx-VPHASEx=10V; CHGATEx to PHASEx=3.3nF VBOOTx-VPHASEx=10V VBOOTx-VPHASEx=12V; VCCDR=10V; CLGATEx to PGNDx=5.6nF VCCDR=10V VCCDR=12V 0.7 1.5 15 30 ns
2 2 30 2.5 55
A ns
1.8 1.1 1.5
A
P GOOD and OVP/UVP PROTECTIONS PGOOD PGOOD OVP UVP VPGOOD Upper Threshold (VSEN/DACOUT) Lower Threshold (VSEN/DACOUT) Over Voltage Threshold (VSEN) Under Voltage Trip (VSEN/DACOUT) PGOOD Voltage Low VSEN Rising VSEN Falling VSEN Rising VSEN Falling IPGOOD = -4mA 108 84 2.0 56 0.3 60 0.4 112 88 116 92 2.25 64 0.5 % % V % V
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L6917B
Table 1. VID Settings
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output Voltage (V) OUTPUT OFF 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850
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L6917B
PIN FUNCTION
N 1 2 3 4 5 Name LGATE1 VCCDR Channel 1 low side gate driver output. Mosfet driver supply. It can be varied from 5V to 12V. Description
PHASE1 This pin is connected to the source of the upper mosfet and provides the return path for the high side driver of channel 1. UGATE1 Channel 1 high side gate driver output. BOOT1 Channel 1 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs. boot). Device supply voltage. The operative supply voltage is 12V. All the internal references are referred to this pin. Connect it to the PCB signal ground. This pin is connected to the error amplifier output and is used to compensate the control feedback loop. This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. A current proportional to the sum of the current sensed in both channel is sourced from this pin (50A at full load, 70A at the Over Current threshold). Connecting a resistor between this pin and VSEN pin allows programming the droop effect. Connected to the output voltage it is able to manage Over & Under-voltage conditions and the PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for Remote Sense of the regulated voltage. If no Remote Sense is implemented, connect it directly to the regulated voltage in order to manage OVP, UVP and PGOOD. Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to perform a remote sense. If no remote sense is implemented, connect directly to the output voltage (in this case connect also the VSEN pin directly to the output regulated voltage). Remote sense buffer inverting input. It has to be connected to the negative side of the load to perform a remote sense. Pull-down to ground if no remote sense is implemented. Channel 1 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg in order to program the positive current limit at 140% as follow: 35 A R g IMA X = -------------------------R se nse Where 35A is the current offset information relative to the Over Current condition (offset at OC threshold minus offset at zero load). The net connecting the pin to the sense point must be routed as close as possible to the PGNDS1 net in order to couple in common mode any picked-up noise.
6 7 8 9
VCC GND COMP FB
10
VSEN
11
FBR
12
FBG
13
ISEN1
14
PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point (*) must be routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up noise. PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense point (*) must be routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up noise.
15
(*) Through a resistor Rg.
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L6917B
PIN FUNCTION (continued)
N 16 Name ISEN2 Description Channel 2 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg in order to program the positive current limit at 140% as follow: 35 A R g IMA X = -------------------------R se nse Where 35A is the current offset information relative to the Over Current condition (offset at OC threshold minus offset at zero load). The net connecting the pin to the sense point must be routed as close as possible to the PGNDS2 net in order to couple in common mode any picked-up noise. 17 OSC/ INH/ FAULT Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the external frequency is increased according to the equation: 14.82 10 fS = 300KHz + ----------------------------R O SC ( K ) Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to the equation: 12.91 10 fS = 300KHz - ----------------------------R O SC ( K ) If the pin is not connected, the switching frequency is 300KHz. Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit state. The pin is forced high when an over or under voltage is detected. This condition is latched; to recover it is necessary turn off and on VCC. 18-22 VID4-0 Voltage IDentification pins. These input are internally pulled-up and TTL compatible. They are used to program the output voltage as specified in Table 1 and to set the power good thresholds. Connect to GND to program a `0' while leave floating to program a `1'. This pin is an open collector output and is pulled low if the output voltage is not within the above specified thresholds. If not used may be left floating. Channel 2 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs. boot).
7 6
23
PGOOD
24
BOOT2
25 26 27 28
UGATE2 Channel 2 high side gate driver output. PHASE2 This pin is connected to the source of the upper mosfet and provides the return path for the high side driver of channel 2. LGATE2 PGND Channel 2 low side gate driver output. Power ground pin. This pin is common to both sections and it must be connected through the closest path to the low side mosfets source pins in order to reduce the noise injection into the device.
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Device Description The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses. The output voltage of the converter can be precisely regulated, programming the VID pins, from 1.100V to 1.850V with 25mV binary steps, with a maximum tolerance of 0.8% over temperature and line voltage variations. The device provides an average current-mode control with fast transient response. It includes a 300kHz free-running oscillator adjustable up to 600kHz. The error amplifier features a 15V/s slew rate that permits high converter bandwidth for fast transient performances. Current information is read across the lower mosfets rDSON or across a sense resistor in fully differential mode. The current information corrects the PWM output in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at 10% over static and dynamic conditions. The device protects against over-current, with an OC threshold for each phase, entering in constant current mode. Since the current is read across the low side mosfets, the constant current keeps constant the bottom of the inductors current triangular waveform. When an under voltage is detected the device latches and the FAULT pin is driven high. The device performs also over voltage protection that disable immediately the device turning ON the lower driver and driving high the FAULT pin. Oscillator The device has been designed in order to operate an each phase at the same switching frequency of the internal oscillator. So, input and output resulting frequency is doubled. The switching frequency is internally fixed to 300kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 25A and may be varied using an external resistor (R OSC) connected between OSC pin and GND or Vcc. Since the OSC pin is maintained at fixed voltage (typ). 1.235V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 12KHz/A. In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships: 1.237 kHz 14.82 10 R OS C vs. GND: f S = 300kH z + ----------------------------- 12 ---------- = 300 kHz + ----------------------------( K ) A R ( K ) R
O SC O SC 7 6
12 - 1.237 kHz 12.918 10 R OS C vs. 12V: f S = 300 kHz - ----------------------------- 12 ---------- = 300kH z - ------------------------------( K ) A R ( K ) R
O SC O SC
Note that forcing a 25A current into this pin, the device stops switching because no current is delivered to the oscillator. Figure 1. ROSC vs. Switching Frequency
7000 1000 900
Rosc(K) vs. GND
0 100 200 300
6000
Rosc(K) vs. 12V
800 700 600 500 400 300 200 100 0 300 400 500 600 700 800 900 1000
5000 4000 3000 2000 1000 0
Frequency (KHz)
Frequency (KHz)
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L6917B
Digital to Analog Converter The built-in digital to analog converter allows the adjustment of the output voltage from 1.100V to 1.850V with 25mV as shown in the previous table 1. The internal reference is trimmed to ensure the precision of 0.8% and a zero temperature coefficient around 70C. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5A current generator up to 3.3V max); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. VID code "11111" programs the NOCPU state: all mosfets are turned OFF and the condition is latched. The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the overvoltage protection (OVP) thresholds. Soft Start and INHIBIT At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in 2048 clock periods as shown in figure 2. Before soft start, the lower power MOS are turned ON after that VCCDR reaches 2V (independently by Vcc value) to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start begins, the reference is increased; when it reaches the bottom of the oscillator triangular waveform (1V typ) also the upper MOS begins to switch and the output voltage starts to increase with closed loop regulation.. At the end of the digital soft start, the Power Good comparator is enabled and the PGOOD signal is then driven high (See fig. 2). The Under Voltage comparator enabled when the reference voltage reaches 0.8V. The Soft-Start will not take place, if both V CC and VCCDR pins are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of the two supplies the device shuts down. Forcing the OSC/INH/FAULT pin to a voltage lower than 0.8V the device enter in INHIBIT mode: all the power mosfets are turned off until this condition is removed. When this pin is freed, the OSC/INH/FAULT pin reaches the band-gap voltage and the soft start begins. Figure 2. Soft Start
V IN =VCCDR
Turn ON threshold 2V
V LGATEx
t
V OUT
t
PGOOD
t
2048 Clock Cycles
t
Acquisition: CH1 = PGOOD; CH2 = VOUT; CH4 = LGATEx
Timing Diagram
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L6917B
Driver Section The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the RDSON), maintaining fast switching transition. The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VCCDRV pin is required to start operations of the device. The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanoseconds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet gate drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the inductor is negative, the source of high-side mosfet will never drop. To allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. Several combination of supply can be chosen to optimize performance and efficiency of the application. Power conversion is also flexible, 5V or 12V bus can be chosen freely. The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capacitive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with VBOOT-VPHASE = 12V; similarly, for the lower drivers, the source current is 2.4A while the sink current is 2A with VCCDR = 12V. Figure 3. Drivers peak current: High Side (left) and Low Side (right)
CH3 = HGATE1; CH4 = HGATE2
CH3 = LGATE1; CH4 = LGATE2
Current Reading and Over Current The current flowing trough each phase is read using the voltage drop across the low side mosfets rDSON or across a sense resistor (RSENSE) and internally converted into a current. The transconductance ratio is issued by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points. The full differential current reading rejects noise and allows to place sensing element in different locations without affecting the measurement's accuracy. The current reading circuitry reads the current during the time in
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which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two pins at the same voltage sinking from the ISENx pin the necessary current. The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and negative current. This circuit reproduces the current flowing through the sensing element using a high speed Track & Hold transconductance amplifier. In particular, it reads the current during the second half of the OFF time reducing noise injection into the device due to the mosfet turn-on (See fig. 4). Track time must be at least 200ns to make proper reading of the delivered current. Figure 4. Current Reading Timing (Left) and Circuit (Right)
ILS1
LGATEX
ILS2
Rg ISENX
Total current information
IISENx Rg PGNDSX Track & Hold
50A
This circuit sources a constant 50A current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following equation: R SENSE I PHASE I ISENx = 50A + ---------------------------------------------- = 50 A + I INFO x Rg Where RSENSE is an external sense resistor or the rds,on of the low side mosfet and Rg is the transconductance resistor used between ISENx and PGNDSx pins toward the reading points; IPHASE is the current carried by each phase and, in particular, the current measured in the middle of the oscillator period The current information reproduced internally is represented by the second term of the previous equation as follow: R SENSE I PHASE I INFO x = ---------------------------------------------Rg Since the current is read in differential mode, also negative current information is kept; this allow the device to check for dangerous returning current between the two phases assuring the complete equalization between the phase's currents. From the current information of each phase, information about the total current delivered (IFB = IINFO1 + IINFO2) and the average current for each phase (IAVG = (IINFO1 + IINFO2)/2 ) is taken. IINFOX is then compared to IAVG to give the correction to the PWM output in order to equalize the current carried by the two phases. The transconductance resistor Rg has to be designed in order to have current information of 25A per phase at full nominal load; the over current intervention threshold is set at 140% of the nominal (IINFOx = 35A). According to the above relationship, the limiting current (ILIM) for each phase, which has to be placed at one half of the total delivered maximum current, results: 35 A R g I L IM = -------------------------R SENSE I LIM R SENSE Rg = ------------------------------------35 A
An over current is detected when the current flowing into the sense element is greater than 140% of the nominal
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RSENSE
IPHASE
L6917B
current (IINFOx>35A): the device enters in Quasi-Constant-Current operation. The low-side mosfets stays ON until IINFO becomes lower than 35A skipping clock cycles. The high side mosfets can be turned ON with a TON imposed by the control loop at the next available clock cycle and the device works in the usual way until another OCP event is detected. The device limits the bottom of the inductor current triangular waveform. So the average current delivered can slightly increase also in Over Current condition since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the 140% bottom. The worst-case condition is when the duty cycle reaches its maximum value (d=75% internally limited). When this happens, the device works in Constant Current and the output voltage decrease as the load increase. Crossing the UVP threshold causes the device to latch (FAULT pin is driven high). Figure 5 shows this working condition Figure 5. Constant Current operation Ipeak IMAX 140%
UVP
Vout
Droop effect
TonMAX
TonMAX
Inom IOCP IMAX
Iout
It can be observed that the peak current (Ipeak) is greater than the 140% but it can be determined as follow: V IN - Vout M IN Ipea k = 1.4 I NOM + -------------------------------------- To n M AX L Where INOM is the nominal current and Vout MIN is the minimum output voltage (VID-40% as explained below). The device works in Constant-Current, and the output voltage decreases as the load increase, until the output voltage reaches the under-voltage threshold (VoutMIN). When this threshold is crossed, all mosfets are turned off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation. The maximum average current during the Constant-Current behavior results: Ip eak - 1.4 I NOM I M AX = 1.4 I NOM + 2 -----------------------------------------------2 In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed (TonMAX) while the OFF time depends on the application: Ipe ak - 1.4 INOM 1 f = -----------------------------------------T O FF = L -----------------------------------------------Vout To n M AX + T O FF Over current is set anyway when IINFOx reaches 35A. The full load value is only a convention to work with convenient values for IFB. Since the OCP intervention threshold is fixed, to modify the percentage with respect to the load value, it can be simply considered that, for example, to have on OCP threshold of 170%, this will correspond to IINFOx = 35A (IFB = 70A). The full load current will then correspond to IINFOx = 20.5A (IFB = 41A).
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L6917B
Integrated Droop Function The device uses a droop function to satisfy the requirements of high performance microprocessors, reducing the size and the cost of the output capacitor. This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) proportional to the output current. Since the device has an average current mode regulation, the information about the total current delivered is used to implement the Droop Function. This current (equal to the sum of both IINFOx) is sourced from the FB pin. Connecting a resistor between this pin and Vout, the total current information flows only in this resistor because the compensation network between FB and COMP has always a capacitor in series (See fig. 7). The voltage regulated is then equal to: VOUT = VID - RFB * IFB Since IFB depends on the current information about the two phases, the output characteristic vs. load current is given by: R SENSE V OUT = VID - R FB --------------------- I OUT Rg Figure 6. Output transient response without (a) and with (b) the droop function
ESR DROP ESR DROP
VMAX VDROOP
VNOM
VMIN
(a)
(b)
Figure 7. Active Droop Function Circuit
RFB To VOUT
COMP
FB
I FB VPROG
The feedback current is equal to 50A at nominal full load (IFB = IINFO1 + IINFO2) and 70A at the OC threshold, so the maximum output voltage deviation is equal to: VFULL_POSITIVE_LOAD = +RFB * 50A VPOSITIVE_OC_THRESHOLD = +RFB * 70A
Droop function is provided only for positive load; if negative load is applied, and then IINFOx < 0, no current is sunk from the FB pin. The device regulates at the voltage programmed by the VID.
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Output Voltage Protection and Power Good The output voltage is monitored by pin VSEN. If it is not within +12/-10% (typ.) of the programmed value, the powergood output is forced low. Power good is an open drain output and it is enabled only after the soft start is finished (2048 clock cycles after start-up). The device provides over voltage protection; when the voltage sensed by the V SEN pin reaches 2.1V (typ.), the controller permanently switches on both the low-side mosfets and switches off both the high-side mosfets in order to protect the CPU. The OSC/INH/FAULT pin is driven high (5V) and power supply (Vcc) turn off and on is required to restart operations. The over Voltage percentage is set by the ratio between the OVP threshold (set at 2.1V) and the reference programmed by VID. 2.1V O VP[%] = ---------------------------------------------------------------------------- 100 Refer ence Voltage ( VID ) Under voltage protection is also provided. If the output voltage drops below the 60% of the reference voltage for more than one clock period the device turns off and the FAULT pin is driven high. Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than Vout reaches 0.8V). During soft-start the reference voltage used to determine the OV and UV thresholds is the increasing voltage driven by the 2048 soft start digital counter. Remote Voltage Sense A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without any additional external components. In this way, the output voltage programmed is regulated between the remote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors. If remote sense is not required, the output voltage is sensed by the VSEN pin connecting it directly to the output voltage. In this case the FBG and FBR pins must be connected anyway to the regulated voltage. Input Capacitor The input capacitor is designed considering mainly the input rms current that depends on the duty cycle as reported in figure 8. Considering the dual-phase topology, the input rms current is highly reduced comparing with a single phase operation. Figure 8. Input rms Current vs. Duty Cycle (D) and Driving Relationships
Rms Current Normalized (IRMS/IOUT)
0.50
Single Phase
Dual Phase 0.25
I rms
IOUT = 2 I OUT 2
2D (1 - 2D)
if D < 0 .5 if D > 0.5
(2D - 1) (2 - 2D)
0.25 0.50 0.75 Duty Cycle (VOUT/VIN)
It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst case condition that happens for D = 0.25 and D = 0.75.
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L6917B
The power dissipated by the input capacitance is then equal to: P RM S = ESR ( I RM S )
2
Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the high rms value needed by the CPU power supply application and also to minimize components cost, the input capacitance is realized by more than one physical capacitor. The equivalent rms current is simply the sum of the single capacitor's rms current. Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high frequency noise decoupling, noise generated by parasitic components along power path. Output Capacitor Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the range of tenth A/s, the output capacitor is a basic component for the fast response of the power supply. Dual phase topology reduces the amount of output capacitance needed because of faster load transient response (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180 phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage ripple. When a load transient is applied to the converter's output, for first few microseconds the current to the load is supplied by the output capacitors. The controller recognizes immediately the load transient and increases the duty cycle, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): VOUT = IOUT * ESR A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: I OUT L V OUT = --------------------------------------------------------------------------------------------2 C OUT ( V INM IN D M AX - V OUT ) Where DMAX is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: V IN - V OUT V OUT L = ----------------------------- -------------V IN fs I L Where fSW is the switching frequency, VIN is the input voltage and V OUT is the output voltage. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. The response time is the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output
2
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L6917B
voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for I load transient in case of enough fast compensation network response: L I t a pplic atio n = ----------------------------V IN - V OUT L I t rem ov al = -------------V OUT
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available. Figure 9. Inductor ripple current vs Vout
9
L=1.5H, Vin=12V
8
Inductor Ripple [A]
7 6 5 4 3 2 1 0 0.5 1.5 2.5
L=2H, Vin=12V L=3H, Vin=12V L=1.5H, Vin=5V L=2H, Vin=5V L=3H, Vin=5V
3.5
Output Voltage [V]
MAIN CONTROL LOOP The L6917B control loop is composed by the Current Sharing control loop and the Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 10 reports the block diagram of the main control loop. Figure 10. Main Control Loop Diagram
L1 PWM1 IINFO2 IINFO1 L2 PWM2 ERROR AMPLIFIER 4/5 COMP ZF(S) + FB ZFB REFERENCE PROGRAMMED BY VID CO RO
+
1/5
1/5
CURRENT SHARING DUTY CYCLE CORRECTION
+
D02IN1392
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L6917B
s
Current Sharing (CS) Control Loop
Active current sharing is implemented using the information from Tran conductance differential amplifier in an average current mode control scheme. A current reference equal to the average of the read current (IAVG) is internally built; the error between the read current and this reference is converted to a voltage with a proper gain and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See fig. 11). The current sharing control is a high bandwidth control loop allowing current sharing even during load transients. The current sharing error is affected by the choice of external components; choose precise Rg resistor (1% is necessary) to sense the current. The current sharing error is internally dominated by the voltage offset of Tran conductance differential amplifier; considering a voltage offset equal to 2mV across the sense resistor, the current reading error is given by the following equation: I RE AD 2mV ------------------- = --------------------------------------R SENSE I M AX I M AX Where IREAD is the difference between one phase current and the ideal current (IMAX/2). For Rsense = 4m and Imax = 40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and Rsense mismatches. Figure 11. Current Sharing Control Loop
+
L1 PWM1
1/5
1/5
CURRENT SHARING DUTY CYCLE CORRECTION
IINFO2 IINFO1
+
COMP
PWM2
L2
D02IN1393
VOUT
s
Average Current Mode (ACM) Control Loop
The average current mode control loop is reported in figure 12. The current information IFB sourced by the FB pin flows into RFB implementing the dependence of the output voltage from the read current. The ACM control loop gain results (obtained opening the loop after the COMP pin): PWM Z F ( s ) ( R DROOP + Z P ( s ) ) G LO O P ( s ) = -------------------------------------------------------------------------------------------------------------------ZF (s ) 1 ( Z P ( s ) + Z L ( s ) ) -------------- + 1 + ----------- R FB A(s) A ( s ) Where: R s en se - R DROOP = ------------------ R FB is the equivalent output resistance determined by the droop function; Rg - ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load Ro;
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- ZF(s) is the compensation network impedance; - ZL(s) is the parallel of the two inductor impedance; - A(s) is the error amplifier gain; 4 V IN - PWM = -- ------------------ * is the ACM PWM transfer function where DVosc is the oscillator ramp amplitude 5 V O SC and has a typical value of 2V Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control loop gain results: ZF ( s) V IN Rs Z P ( s ) 4 G LO O P ( s ) = - -- ------------------ ----------------------------------- ------- + -------------- 5 V OS C Z P ( s ) + Z L ( s ) Rg R FB With further simplifications, it results: Z F ( s ) R o + R DROOP V IN 1 + s Co ( R DROOP //Ro + ESR ) 4 G L OO P ( s ) = - -- ------------------ -------------- ------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------5 V O SC R FB RL RL 2 L L R o + -----s C o -- + s --------------- + Co ESR + Co ------ + 1 2 2 2 2 Ro Considering now that in the application of interest it can be assumed that Ro>>RL; ESR<dB
ZF CF
IFB RF RFB
GLOOP
VCOMP REF K ZF(s)
PWM
L/2 d*VIN Cout ESR
VOUT LC Rout Z T
1 4 VIN K = -- --------------- ---------5 Vo sc R FB
dB
Compensation network can be simply designed placing Z = LC and imposing the cross-over frequency T as desired obtaining:
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L6917B
R F B V O SC 5 L -R F = ---------------------------------- T ------------------------------------------------------- -V IN 2 ( R DROOP + ESR ) 4 L C o -2 C F = ------------------RF
LAYOUT GUIDELINES Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimise the performance of the control loops. Integrated power drivers reduce components count and interconnections between control functions and drivers, reducing the board space. Here below are listed the main points to focus on when starting a new layout and rules are suggested for a correct implementation.
s
Power Connections.
These are the connections where switching and continuous current flows from the input supply towards the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces. The critical components, i.e. the power transistors, must be located as close as possible, together and to the controller. Considering that the "electrical" components reported in fig. 13 are composed by more than one "physical" component, a ground plane or "star" grounding connection is suggested to minimize effects due to multiple connections. Figure 13. Power connections and related connections layout guidelines (same for both phases)
VIN
Rgate HGATEx PHASEx L
+VCC PHASEx L
BOOTx CBOOTx HS
VIN
HS
Rgate LGATEx PGNDx
LS
COUT D CIN LOAD
SGND
VCC
LS
COUT D CIN LOAD
CVCC
a. PCB power and ground planes areas
b. PCB small signal components placement
Fig. 13a shows the details of the power connections involved and the current loops. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors (electrolytic or Ceramic or both) are required.
s
Power Connections Related.
Fig.13b shows some small signal components placement, and how and where to mix signal and power ground planes. The distance from drivers and mosfet gates should be reduced as much as possible. Propagation delay times
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as well as for the voltage spikes generated by the distributed inductance along the copper traces are so minimized. In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a consequence, the higher are the voltage spikes corresponding to the gate pwm rising and falling signals. Even if these spikes are clamped by inherent internal diodes, propagation delays, noise and potential causes of instabilities are introduced jeopardizing good system behavior. One important consequence is that the switching losses for the high side mosfet are significantly increased. For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance (see fig 14). In addition, since the PHASEx pin is the return path for the high side driver, this pin must be connected directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets, the return path is the PGND pin: it can be connected directly to the power ground plane (if implemented) or in the same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power ground plane is implemented) must also be designed to handle current peaks in excess of 2A (30 mils wide is suggested). Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system efficiency. Figure 14. Device orientation (left) and sense nets routing (right)
Towards HS mosfet
(30 mils wide)
To LS mosfet
(or sense resistor)
Towards LS mosfet
(30 mils wide)
Towards HS mosfet
(30 mils wide)
To LS mosfet
(or sense resistor)
To regulated output
The placement of other components is also important: - The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to minimize the loop that is created. - Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins. - Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capacitor sustains the peak currents requested by the low-side mosfet drivers. - Refer to SGND all the sensible components such as frequency set-up resistor (when present) and also the optional resistor from FB to GND used to give the positive droop effect. - Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation effect and to ensure the right precision to the regulation when the remote sense buffer is not used. - An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in reducing noise. - PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be observed on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device can absorb energy and it can cause damages. The voltage spikes must be limited by proper layout, the use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber network on the low side mosfets, to a value lower than 26V, for 20nSec, at Fosc of 600kHz max. s Current Sense Connections. Remote Buffer: The input connections for this component must be routed as parallel nets from the FBG/FBR
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pins to the load in order to compensate losses along the output power traces and also to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load regulation, increasing output tolerance. Current Reading: The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx pins in order to limit the noise injection into the device. The PCB traces connecting these resistors to the reading point must be routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important to avoid any offset in the measurement and to get a better precision, to connect the traces as close as possible to the sensing elements, dedicated current sense resistor or low side mosfet Rdson. Moreover, when using the low side mosfet RdsON as current sense element, the ISENx pin is practically connected to the PHASEx pin. DO NOT CONNECT THE PINS TOGETHER AND THEN TO THE HS SOURCE! The device won't work properly because of the noise generated by the return of the high side driver. In this case route two separate nets: connect the PHASEx pin to the HS Source (route together with HGATEx) with a wide net (30 mils) and the ISENx pin to the LS Drain (route together with PGNDSx). Moreover, the PGNDSx pin is always connected, through the Rg resistor, to the PGND: DO NOT CONNECT DIRECTLY TO THE PGND! In this case, the device won't work properly. Route anyway to the LS mosfet source (together with ISENx net). Right and wrong connections are reported in Figure 15. Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter. Figure 15. PCB layout connections for sense nets NOT CORRECT
VIA to GND plane To PHASE connection
CORRECT
To LS Drain and Source To HS Gate and Source
Wrong (left) and correct (right) connections for the current reading sensing nets.
APPLICATION EXAMPLES The dual-pahse topology can be applied to several different applications ranging from CPU power supply (for which the device has been designed) to standard high current DC-DC power supply. The application benefits of all the advantages due to the dual-phase topology ranging from output ripple reduction to dynamic performance increase. After a general demo board overview, the following application examples will be illustrated: - CPU Power Supply: 5 to 12 VIN; 1.7VOUT; 45A - CPU Power Supply: 12VIN; VRM 9.0 Output; 50A - High Current DC-DC: 12VIN; 3.3 to 5VOUTT; 35A Demo Board Description The demo board shows the operation of the device in a dual phase application. This evaluation board allows output voltage adjustability (1.100V - 1.850V) through the switches S0-S4 and high output current capability. The board has been laid out with the possibility to use up to two D2PACK mosfets for the low side switch in order to give maximum flexibility in the mosfet's choice. The four layers demo board's copper thickness is of 70m in order to minimize conduction losses considering the high current that the circuit is able to deliver. Demo board schematic circuit is reported in Figure 16.
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L6917B
Figure 16. Demo Board Schematic
Vin
JP6
GNDin
DZ1
JP1 JP2
R16
VCCDR VCC
R10 2 6 C7
BOOT1
C9,C10 C11..C13
Vcc C5 GNDcc D4 C8
D3
C6
5 4 3
24 25 26
BOOT2
C4 L1
Q2 R15
UGATE1
UGATE2
Q4 R14
C3 L2 VoutCORE C14, C23 R19 R20 GNDCORE
PHASE1
PHASE2
R18 Q1 D1 Q1a R6
PGNDS1 LGATE1
R17 1 13 27 16 R3
PGNDS2 LGATE2
Q3 R12 Q3a
R13
ISEN1 ISEN2
D2
U1
L6917B
14 R5 S4 S3 S2 S1 S0
VID4
15
PGND
R1 R4
28 22
VID3 VID2 VID1
21 20 19 18
23 10
PGOOD VSEN
PGOOD JP3
R7
FB
VID0
9 R8 C2 11 12 8
FBG COMP
OSC / INH
17
JP4
JP5
R2
SGND
C1
R9
7
FBR
FBG FBR
Several jumpers allow setting different configurations for the device: JP3, JP4 and JP5 allow configuring the remote buffer as desired. Simply shorting JP4 and JP5 the remote buffer is enabled and it senses the output voltage on-board; to implement a real remote sense, leave these jumpers open and connect the FBG and FBR connectors on the demo board to the remote load. To avoid using the remote buffer, simply short all the jumpers JP3, JP4 and JP5. Local sense through the R7 is used for the regulation. The input can be configured in different ways using the jumpers JP1, JP2 and JP6; these jumpers control also the mosfet driver supply voltage. Anyway, power conversion starts from VIN and the device is supplied from VCC (See Figure 17). Figure 17. Power supply configuration
To Vcc pin
Vin
JP6
To HS Drains (Power Input) To BOOTx (HS Driver Supply)
DZ1
JP1 JP2
GNDin
Vcc GNDcc
To VCCDR pin (LS Driver Supply)
Two main configurations can be distinguished: Single Supply (V CC = VIN = 12V) and Double Supply (VCC = 12V VIN = 5V or different).
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- Single Supply: In this case JP6 has to be completely shorted. The device is supplied with the same rail that is used for the conversion. With an additional zener diode DZ1 a lower voltage can be derived to supply the mosfets driver if Logic level mosfet are used. In this case JP1 must be left open so that the HS driver is supplied with VIN-VDZ1 through BOOTx and JP2 must be shorted to the left to use VIN or to the right to use VIN-VDZ1 to supply the LS driver through VCCDR pin. Otherwise, JP1 must be shorted and JP2 can be freely shorted in one of the two positions. - Double Supply: In this case VCC supply directly the controller (12V) while VIN supplies the HS drains for the power conversion. This last one can start indifferently from the 5V bus (Typ.) or from other buses allowing maximum flexibility in the power conversion. Supply for the mosfet driver can be programmed through the jumpers JP1, JP2 and JP6 as previously illustrated. JP6 selects now VCC or VIN depending on the requirements. Some examples are reported in the following Figures 18 and 19. Figure 18. Jumpers configuration: Double Supply
Vcc = 12V
Vin = 5V GNDin
JP6
Vcc = 12V
Vin = 5V GNDin
JP6
HS Drains = 5V HS Supply = 5V
DZ1
JP1 JP2
HS Drains = 5V HS Supply = 12V
DZ1
JP1 JP2
Vcc = 12V GNDcc
VCCDR (LS Supply) = 5V
Vcc = 12V GNDcc
VCCDR (LS Supply) = 12V
(a) VCC = 12V; VBOOTx = VCCDR = VIN = 5V
(b) V CC = VBOOTx = VCCDR =12V; VIN = 5V
Figure 19. Jumpers configuration: Single Supply
Vcc = 12V
Vin = 12V GNDin
JP6
Vcc = 12V
Vin = 12V GNDin
JP6
HS Drains = 12V HS Supply = 5.2V
DZ1 6.8V
JP1 JP2
HS Drains = 12V HS Supply = 12V
DZ1
JP1 JP2
Vcc = Open GNDcc
VCCDR (LS Supply) = 12V
Vcc = Open GNDcc
VCCDR (LS Supply) = 12V
(a) VCC = VIN = VCCDR = 12V; VBOOTx = 5.2V
(b) VCC = VIN= VBOOTx = VCCDR = 12V
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PCB and Components Layouts Figure 20. PCB and Components Layouts
Component Side
Internal PGND Plane
Figure 21. PCB and Components Layouts
Internal SGND Plane
Solder Side
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CPU Power Supply: 5 to 12VIN; 1.7VOUT; 45A Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast reaction, this helps in reducing output and input capacitor. Inductance value is also reduced. A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compensation network. It can be considered to use the 5V rail for the power conversion in order to allow compatibility with standard ATX power supply. - Current Reading Network and Over Current: Since the maximum output current is IMAX = 45A, the over current threshold has been set to 46A (23A per phase) in the worst case (max mosfet temperature). This because the device limits the valley of the triangular ripple across the inductors. Considering to sense the output current across the low-side mosfet RdsON, STB90NF03L has 6.5m max at 25C that becomes 9.1m considering the temperature variation (+40%); the resulting Tran conductance resistor Rg has to be: I MAX RdsO N 46 9.1m Rg = ------------ -------------------- = ----- ------------- = 5.9k 2 35 2 35 (R3 to R6)
- Droop function Design: Considering a voltage drop of 100mv at full load, the feedback resistor RFB has to be: 100mV R FB = ------------------- = 1.43k 70 A (R7)
- Inductor design: Each phase has to deliver up to 22.5A; considering a current ripple of 5A (<25%), the resulting inductance value is: 1 12 - 1.7 1.7 Vin - Vo ut d L = ---------------------------- ----------- = -------------------- ------- ------------------- = 1 H l 12 300000 5 Fsw - Output Capacitor: Five Rubycon MBZ (2200F / 6.3V / 12m max ESR) has been used implementing a resulting ESR of 2.4m resulting in an ESR voltage drop of 45A*2.4m = 108mV after a 45A load transient. - Compensation Network: A voltage loop bandwidth of 20kHz is considered to let the device fast react after load transient. The RF CF network results:
R F B V O SC 5 1 L 1.43k 2 5 RF = --------------------------------- -- T ------------------------------------------------------ = ---------------------- -- 20k 2 ------------------------------------------------------------------ = 6200 (R8) -V IN 4 2 ( R DRO OP + ESR ) 12 4 9.1m 1.43k + 2.4m 2 ------------ 5.9k
(L1, L2)
1 L 6 2200 -----C o -2 2 C F = ------------------- = ---------------------------------------- = 15 nF 6.2k RF
(C2)
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Part List
R1 R2, R20 R3, R4, R5, R6 R7 R8 R10 R12 to R16, R19 R17, R18 C2 C3, C4 C5, C6, C7 C8, C9, C10 C11, C12, C13 C19 to C24 L1, L2 U1 Q1, Q3 Q2, Q4 D1, D2 D3, D4 10k Not Mounted 5.1k 1.43k 6.2k 82 2.2 0 15n 100n 1 10 1800 / 16V 2200 / 6.3V 1 L6917B STB90NF03L STB70NF03L STPS340U 1N4148 Ceramic Ceramic Rubycon MBZ Rubycon MBZ TO50 - 52B - 6 Turns STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics SO28 D2PACK D2PACK SMB SOT23 1% 1% SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 1206 SMD 1206 Radial 23x10.5 Radial 23x10.5
System Efficiency Figure 22 shows the demo board measured efficiency versus load current for different values of input voltage. Mosfet temperature is always lower than 115 C, at Tamb = 25C. Figure 22. Efficiency (fosc = 200kHz; Vout = 1.7V)
95 90 85
Efficiency [%]
80 75 70 65 60 55 50 45 0 5 10 15 20 25 30 35 40
Vin= 12V Vin=5V
Output Current [A]
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CPU Power Supply: 12VIN - VRM 9.0 - 50A thermal Figure 23 shows the device in a high current CPU core power supply solution. The output voltage can be adjusted with binary step from 1.100V to 1.850V following VRM 9.0 specifications. The demo board assembled with the following part list is capable to deliver up to 50A in open air without any kind of airflow. Peak current can reach 60A without any limitations. For higher DC current, to avoid mosfet change, airflow or heat sink are required. Figure 23. CPU Power Supply Schematic
Vin
JP6
GNDin
JP1
DZ1 R16
JP2
R10
VCCDR
C9,C10 C11..C13
Vcc C5 GNDcc D4 C8
2
6
VCC
C7
BOOT1
D3
C6
5 4
24 25
BOOT2
UGATE1
UGATE2
C4 L1
Q2 R15
PHASE1
Q4 R14
PHASE2
C3 L2 VoutCORE C14, C23 R19 R20 GNDCORE
3 1
26 27
R18
LGATE1 LGATE2
R17 Q3 R12
ISEN1 ISEN2
Q1 D1 Q1a R6
PGNDS1
R13 13
D2 Q3a
U1
L6917B
16 R3
PGNDS2
14 R5 S4 S3 S2 S1 S0
VID4
15
PGND
R1 R4
28 22
VID3
21
VID2 VID1
23 10
PGOOD VSEN
PGOOD Ra R7 JP3
20 19 18
VID0
FB
9 R8 C2
COMP
Ca
JP4 JP5
OSC / INH
17
To Vcc
Rosc
R2
SGND
C1
R9
7 11
FBR
12
8
FBG
FBG FBR
Part List
R1 R2, R9 R3, R4, R5, R6 R7 R8 R10 R12 to R15 R16, R17, R18 Ra Rosc C1 10k Not Mounted 3.3k 3.6k 3.3k 82 2.2 0 1k 1.3M Not Mounted 1% 1% 1% SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805
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Part List (continued)
C2 C3, C4 C5, C6, C7, C8 C9, C10 C11 to C13 C14 to C23 Ca L1, L2 U1 Q1,Q1a, Q3,Q3a Q2, Q4 D1, D2 D3, D4 47n 100n 1 10 1800/ 16V 2200/ 6.3V 68n 0.5 L6917B SUB85N03-04P SUB70N03-09BP STPS340U 1N4148 77121 Core - 3 Turns STMicroelectronics Vishay - Siliconix Vishay - Siliconix STMicroelectronics STMicroelectronics SO28 D2PACK D2PACK SMB SOT23 Ceramic Ceramic Ceramic Rubycon MBZ Rubycon MBZ SMD 0805 SMD 0805 SMD 1206 SMD 1206 Radial 10x10.5 Radial 10x10.5 SMD 0805
Efficiency Figure 24 showes the system efficiency for output current ranging form 5A up to 50A. Figure 24. Efficiency (fosc = 200kHz; Vout = 1.7V)
89 87
Efficiency [%]
85 83 81 79 77 75 0 5 10 15 20 25 30 35 40 45 50 55
Output Current [A]
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L6917B
Current Sharing Figure 25 shows the current balancing between the two phases for different values of output current. Figure 25.
Load Transient Response Figure 26 shows the system response from 0 to 50A load transient. To obtain such a response, 5 additional capacitors have been added to the output filter to reproduce the motherboard output filter. Noise can be further reduced by adding ceramic decoupling capacitors. Figure 26. 1.7V Output Voltage Ripple During 0 to 50A Load Transient
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L6917B
High Current DC-DC: 12VIN - 3.3 (or 5V) OUT - 35A Figure 27 shows the device in a high current server power supply application. Adding an external resistor divider after the remote sense buffer gives the possibility to increase the regulated voltage. Considering for example a divider by two (two equal resistors) the DAC range is doubled from 2.200V to 3.700V with 50mV binary steps. The external resistor divider must be designed in order to give negligible effects to the remote buffer gain, this means that the resistors value must be much lower than the remote buffer input resistance (20k). In this way, it is possible to regulate the 3.3V and 2.5V rails from the 12V available from the AC/DC converter. The 5V rail can be obtained with further modifications to the external divider. The regulator assures all the advantages of the dual phase conversion especially in the 5V conversion where the duty cycle is near the 50% and practically no ripple is present in the input capacitors. The board is able to deliver up to 35A "thermal" at Tamb 25C without airflow. Higher currents can be reached for reasonable times considering the overall dynamic thermal capacitance. Figure 27. Server power supply schematic
Vin
JP6
GNDin
JP1
DZ1
JP2
R16
VCCDR VCC
R10 2 6 C7
BOOT1 BOOT2
C9,C10 C11..C13
Vcc C5 GNDcc D4 C8
D3
C6
5
UGATE1
24
UGATE2
C4 L1
Q2 R15
PHASE1
4 3 R18
LGATE1
25 R14
PHASE2
Q4
C3 L2 VoutCORE C14, C23 R19 R20 GNDCORE
26 R17
LGATE2
Q1 D1 Q1a R6
PGNDS1
1 R13
ISEN1
27 R12
ISEN2
Q3 Q3a R3
PGNDS2
D2
13
U1
L6917B
16
14 R5 S4 S3 S2 S1 S0
VID4
15
PGND
R1 R4
28 22
VID3 PGOOD
21
VID2
23
VSEN
PGOOD JP3
20
VID1
10 R7
FB
19
VID0
18
OSC / INH
9
JP4 JP5
17 To Vcc Rosc R2
SGND
R8 C2
COMP
C1
R9
7 11
FBR
12
8
FBG
FBG FBR
The following part list refers to the following application: - Input Voltage: 12V; - Output voltage: 3.3V; - Oscilator frequency: 200kHz; - Output voltage tolerance (over static and dynamic conditions): 2.5%.
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L6917B
Part List
R1 R2, R9 R3, R6 R4, R5 R7 R8 R10 R12 to R15 R16, R17, R18 R19 R20 ROSC C1 C2 C3, C4 C5, C6, C7, C8 C9, C10 C11 to C13 C14,C16,C18,C20,C22 L1, L2 U1 Q1,Q1a,Q2, Q3,Q3a,Q4 D1, D2 D3, D4 DZ1 10k Not Mounted 1.3k 390 75 750 82 2.2 0 300 390 1.3M Not Mounted 220n 100n 1 10 100/ 20V 2200/16V 2.8 L6917B STB90NF03L STPS340U 1N4148 Not Mounted Ceramic Ceramic Ceramic OSCON 20SA100M SANYO 77121 Core - 9 Turns STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics SO28 D2PACK SMB SOT23 Minimelf 1% 1% 1% 1% 1% 1% SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 1206 SMD 1206 Radial 10x10.5 Radial 10x23
Figure 28. System Efficiency for a 12V/3.3V Application (fosc = 200kHz)
Figure 29. Load Transient Response: 0A to 35A @ 1A/s
93 92 91 90 89 88 0 5 10 15 20 25 30 35 40
Efficiency [%]
Output Current [A]
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L6917B
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO28
8 (max.)
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L6917B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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