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CMOS STATIC RAM 256K (64K x 4-BIT)
Integrated Device Technology, Inc.
IDT61298SA
FEATURES:
* 64K x 4 high-speed static RAM * Fast Output Enable (OE) pin available for added system flexibility * High speed (equal access and cycle times) -- Commercial: 12/15 ns (max.) * JEDEC standard pinout * 300 mil 28-pin SOJ * Produced with advanced CMOS technology * Bidirectional data inputs and outputs * Inputs/Outputs TTL-compatible * Three-state outputs * Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The lDT61298SA is a 262,144-bit high-speed static RAM organized as 64K x 4. It is fabricated using IDT's highperformance, high-reliability CMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost-effective approach for memory intensive applications. The IDT61298SA features two memory control functions: Chip Select (CS) and Output Enable (OE). These two functions greatly enhance the IDT61298SA's overall flexibility in high-speed memory applications. Access times as fast as 12ns are available. The IDT61298SA offers a reduced power standby mode, ISB1, which enables the designer to considerably reduce device power requirements. This capability significantly decreases system power and cooling levels, while greatly enhancing system reliability. All inputs and outputs are TTL-compatible and the device operates from a single 5 volt supply. Fully static asynchronous
FUNCTIONAL BLOCK DIAGRAM
A0 VCC D E C O D E R A15 GND 262,144-BIT MEMORY ARRAY
I/O0 I/O1 I/O2 I/O3
I/O CONTROL INPUT DATA CONTROL
CS WE OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2971 drw 01
COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
MAY 1996
DSC-2971/6
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IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (Continued)
circuitry, along with matching access and cycle times, favor the simplified system design approach. The IDT61298SA is packaged in a 300 mil, 28-pin SOJ, providing improved board-level packing densities.
TRUTH TABLE(1,2)
CS
L L L H VHC
(3)
OE
L X H X X
WE
H L H X X
I/O DATAOUT DATAIN High-Z High-Z High-Z
Function Read Data Write Data Outputs Disabled Deselected - Standby (ISB) Deselected - Standby (ISB1)
2971 tbl 01
NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC.
PIN CONFIGURATION
NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC A15 A14 A13 A12 A11 A10 NC NC I/O3 I/O2 I/O1 I/O0
Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Com'l. -0.5 to +7.0
Unit V
VTERM
(2)
TA TBIAS TSTG PT IOUT
0 to +70 -55 to +125 -55 to +125 1.0 50
C C C W mA
SO28-5
21 20 19 18 17 16 15
GND
CS OE
WE
2971 drw 02
SOJ TOP VIEW
NOTES: 2971 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
PIN DESCRIPTIONS
Name A0-A14 I/O0-I/O7 Description Addresses Data Input/Output Chip Select Write Enable Output Enable Ground Power
2971 tbl 04
CAPACITANCE
(TA = +25C, f = 1.0MHz, SOJ Package)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 5 7 Unit pF pF
CS WE OE
GND VCC
NOTE: 2971 tbl 03 1. This parameter is determined by device characterization, but is not production tested.
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IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Temperature 0C to +70C GND 0V Vcc 5V 10%
2971 tbl 05
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Min. 4.5 0 2.2
(1)
Typ. 5.0 0 -- --
Max. 5.5 0 VCC + 0.5V 0.8
Unit V V V V
Input Low Voltage -0.5
NOTE: 2971 tbl 06 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
61298SA12 Symbol ICC Parameter Dynamic Operating Current CS = VIL, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS VHC, VCC = Max., f = 0(2), VLC VIN VHC
Com'l. Mil.
61298SA15
Com'l. Mil.
Unit mA
160
--
140
--
ISB
50
--
45
--
mA
ISB1
20
--
20
--
mA
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
2971 tbl 07
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
2971 tbl 08
5V 480 DATAOUT 255 30pF*
DATAOUT 255
5V 480
5pF*
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Figure 1. AC Test Load *Includes scope and jig capacitances
Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
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IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V 10%
IDT61298SA Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOL = 10mA, VCC = Min. IOH = -4mA, VCC = Min. Min. -- -- -- -- 2.4 Typ. -- -- -- -- -- Max. 5 A 5 0.4 0.5 -- V V
2971 tbl 09
Unit A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%)
61298SA12 Symbol Read Cycle tRC tAA tACS tCLZ(1) tCHZ tOE tOLZ(1) tOHZ tOH tPU
(1) (1) (1)
61298SA15 Min. 15 -- -- 4 -- -- 0 -- 3 0 -- 15 10 10 0 10 0 7 0 -- 4 Max. -- 15 15 -- 7 7 -- 6 -- -- 15 -- -- -- -- -- -- -- -- 6 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2971 tbl 10
Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time
Min. 12 -- -- 4 -- -- 0 -- 3 0 -- 12 9 9 0 9 0 6 0 -- 4
Max. -- 12 12 -- 6 6 -- 6 -- -- 12 -- -- -- -- -- -- -- -- 6 --
tPD(1) tWC tCW tAW tAS tWP tWR tDW tDH tWHZ
(1)
Write Cycle
Write Enable to Output in High-Z Output Active from End-of-Write
tOW(1)
NOTES: 1. This parameter is guaranteed with AC test load (Figure 2) by device characterization, but is not production tested.
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IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t RC ADDRESS t AA tOH
OE
t OLZ t OE (5) t OHZ
(5)
CS
t ACS t CLZ DATAOUT
(5)
t CHZ DATA VALID
(5)
2971 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT DATA VALID
2971 drw 06
tOH
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
t ACS t CLZ (5) DATAOUT t PU VCC ICC SUPPLY CURRENT ISB
2971 drw 07
t CHZ DATA VALID t PD
(5)
NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
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IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1,2,3,5) WE
tWC ADDRESS tAW
CS
tAS tWP
(3)
tWR
WE
tWHZ DATAOUT
(4) (6)
tOW
(6) (4)
tDW DATAIN
tDH
DATA VALID
2971 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1,2,5) CS
tWC ADDRESS tAW
CS
tAS tCW tWR
WE
tDW DATAIN DATA VALID
2971 drw 09
tDH
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the spectified tWP. 4. During this period, I/O pins are in the output state so that the input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state.
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IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT 61298 Device Type SA Power XX Speed XX Package X Process/ Temperature Range
Blank
Commercial (0C to +70C)
Y
300-mil SOJ (SO28-5)
12 15
Commercial Only Commercial Only
Speed in nanoseconds
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