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| EL2072C EL2072C 730 MHz Closed Loop Buffer Features 730 MHz b 3 dB bandwidth (0 5 VPP) 5 ns settling to 0 2% VS e g5V 15 mA Low distortion HD2 HD3 of b 65 dBc at 20 MHz Overload short-circuit protected Closed-loop unity gain Low cost Direct replacement for CLC110 General Description The EL2072 is a wide bandwidth fast settling monolithic buffer built using an advanced complementary bipolar process This buffer is closed loop to achieve lower output impedance and higher gain accuracy Designed for closed-loop unity gain the EL2072 has a 730 MHz b 3 dB bandwidth and 5 ns settling to 0 2% while consuming only 15 mA of supply current The EL2072 is an obvious high-performance solution for video distribution and line-driving applications With low 15 mA supply current and a 70 mA output drive performance in these areas is assured The EL2072's settling to 0 2% in 5 ns low distortion and ability to drive capacitive loads make it an ideal flash A D driver The wide 730 MHz bandwidth and extremely linear phase allow unmatched signal fidelity The EL2072 can be used inside an amplifier loop or PLL as its wide bandwidth and fast rise time have minimal effect on loop dynamics Elantec products and facilities comply with MIL-I-45028A and other applicable quality specifications For information on Elantec's processing see Elantec document QRA-1 Elantec's Processing Monolithic Integrated Circuits Applications Video buffer Video distribution HDTV buffer High-speed A D buffer Photodiode CCD preamps IF processors High-speed communications Ordering Information Part No Temp Range Package Outline MDP0031 MDP0027 EL2072CN b 40 C to a 85 C 8-Pin P-DIP EL2072CS b 40 C to a 85 C 8-Pin SO Connection Diagram DIP and SO Package 2072 - 1 December 1995 Rev E Top View Manufactured under U S Patent No 4 893 091 Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation 1991 Elantec Inc EL2072C 730 MHz Closed Loop Buffer Absolute Maximum Ratings (TA e 25 C) Supply Voltage (VS) Output Current g7V Output is short-circuit protected to ground however maximum reliability is obtained if IOUT does not exceed 70 mA gVS Operating Temperature Junction Temperature Storage Temperature Thermal Resistance b 40 C to a 85 C 175 C b 60 C to a 150 C iJA e 95 C W P-DIP iJA e 175 C W SO Input Voltage Note See EL2071 EL2171 for Thermal Impedance curves Important Note All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore TJ e TC e TA Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002 100% production tested at TA e 25 C and QA sample tested at TA e 25 C TMAX and TMIN per QA test plan QCX0002 QA sample tested per QA test plan QCX0002 Parameter is guaranteed (but not tested) by Design and Characterization Data Parameter is typical value at TA e 25 C for information purposes only DC Electrical Characteristics VS e g5V RL e 100X RS e 50X unless otherwise specified Parameter VOS Description Output Offset Voltage Test Conditions Temp 25 C TMIN TMAX TCVOS Average Offset Voltage Drift Input Bias Current 25 C b TMAX 25 C b TMIN 25 C TMAX TMIN TCIB Average Input Bias Current Drift Small Signal Gain RL e 100X 25 C b TMAX 25 C b TMIN 25 C TMIN TMAX ILIN Integral End Point linearity g2V F S Min Typ 20 Max 80 16 0 13 0 Test Level I V V IV II V IV I V Units mV mV mV mV C mA mA nA C VV VV %F S %F S %F S dB mA TD is 3 3in 20 0 20 0 10 0 50 0 100 0 50 0 100 0 IB 200 0 200 0 0 96 0 95 02 0 98 300 0 700 0 AV 25 C TMIN TMAX 04 08 03 IV IV IV II PSRR IS Power Supply Rejection Ratio Supply Current Quiescent No Load All All 45 0 65 0 15 0 20 0 II 2 EL2072C 730 MHz Closed Loop Buffer DC Electrical Characteristics VS e g5V RL e 100X RS e 50X unless otherwise specified Parameter RIN Description Input Resistance Test Conditions Contd Temp 25 C TMIN TMAX Min 100 0 50 0 200 0 16 22 25 20 30 35 50 0 45 0 g3 2 g3 0 g4 0 Typ 160 0 Max Test Level I V V IV IV IV IV II V II V Units kX kX kX pF pF X X mA TD is 2 4in TD is 3 5in mA V V CIN Input Capacitance 25 C TMIN TMAX ROUT Output Impedance (DC) 25 C TMIN TMAX IOUT Output Current 25 C TMAX TMIN 70 0 VOUT Output Voltage Swing RL e 100X 25 C TMAX TMIN AC Electrical Characteristics VS e g5V Parameter Description Test Conditions RL e 100X RS e 50X unless otherwise specified Temp Min Typ Max Test Level Units FREQUENCY RESPONSE SSBW b 3 dB Bandwidth (VOUT k 0 5 VPP) 25 C TMIN TMAX 400 0 400 0 300 0 55 0 50 0 730 0 V IV IV MHz MHz MHz MHz MHz LSBW b 3 dB Bandwidth (VOUT e 5 0 VPP) 25 C TMIN TMAX 90 0 IV IV GAIN FLATNESS GFPL Peaking VOUT k 0 5 VPP k 200 MHz 25 C TMAX TMIN 00 05 06 08 V IV IV V IV IV IV IV IV IV dB dB dB dB dB dB ns ns GFR Rolloff VOUT k 0 5 VPP k 200 MHz 25 C TMIN TMAX 00 08 10 12 GDL Group Delay k 200 MHz 25 C TMIN TMAX 0 75 10 12 LPD Linear Phase Deviation VOUT k 0 5 VPP k 200 MHz 25 C TMIN TMAX 07 15 20 3 EL2072C 730 MHz Closed Loop Buffer AC Electrical Characteristics Parameter Description Contd Test Level VS e g5V RL e 100X RS e 50X unless otherwise specified Test Conditions Temp Min Typ Max Units TIME-DOMAIN RESPONSE TR1 TF1 Rise Time Fall Time Input Signal Rise Fall e 300 ps Rise Time Fall Time Input Signal Rise Fall s 1 ns TS1 OS Settling Time to 0 2% Input Signal Rise Fall s 1 ns Overshoot Input Signal Rise Fall e 300 ps Slew Rate 2 0V Step 0 5V Step 0 5V Step 25 C TMIN TMAX 5 0V Step 25 C TMIN TMAX All 25 C TMIN TMAX 25 C TMIN TMAX DISTORTION HD2 2nd Harmonic Distortion at 20 MHz 2 VPP 25 C TMIN TMAX HD2A 2nd Harmonic Distortion at 50 MHz 3rd Harmonic Distortion at 20 MHz 3rd Harmonic Distortion at 50 MHz 2 VPP 25 C TMAX TMIN 2 VPP 25 C TMIN TMAX 2 VPP 25 C TMIN TMAX b 60 0 b 65 0 b 50 0 b 55 0 b 50 0 b 48 0 b 55 0 b 45 0 b 40 0 b 55 0 b 55 0 b 50 0 b 45 0 04 10 14 IV IV IV IV IV IV IV IV IV ns ns ns ns ns % % V ms V ms TR2 TF2 45 75 85 50 00 10 0 10 0 15 0 SR 500 0 450 0 800 0 V IV IV IV IV V IV IV IV dBc dBc dBc dBc dBc dBc dBc dBc dBc HD3 HD3A EQUIVALENT INPUT NOISE NF Noise Floor l 100 kHz Integrated Noise 100 kHz to 200 MHz 25 C TMIN TMAX 25 C TMIN TMAX 40 0 b 158 0 b 155 0 b 154 0 IV IV IV IV dBm (1 Hz) TD is 5 1in dBm (1 Hz) mV mV INV 57 0 63 0 4 EL2072C 730 MHz Closed Loop Buffer Typical Performance Curves (VS e g5V Forward Gain and Phase RL e 100X RS e 50X) Gain Flatness Deviation from Linear Phase Reverse Gain and phase Input Impedance Output Impedance Recommended RS vs Load Capacitance Integral Linearity Error Frequency Response vs Rload lS21l vs Cload with Recommended Rs 2072 - 2 5 EL2072C 730 MHz Closed Loop Buffer Typical Performance Curves (VS e g5V Small Signal Pulse Response RL e 100X RS e 50X) Contd Long-Term Settling Time Large Signal Pulse Response 2nd Harmonic Distortion 3rd Harmonic Distortion 2-Tone 3rd Order Intermodulation Intercept 2072 - 3 6 EL2072C 730 MHz Closed Loop Buffer Burn-In Circuit 2072 - 4 Printed Circuit Layout As with any high-frequency device good PCB layout is necessary for optimum performance This is especially important for the EL2072 which has a typical bandwidth of 730 MHz Ground plane construction is a requirement as is good power-supply bypassing close to the package A closely-placed 0 01 mF ceramic capacitor between each supply pin and the ground plane is usually sufficient decoupling Pins 2 3 6 and 7 should be connected to the ground-plane to minimize capacitive feedthrough and all input and output traces should be laid out as transmission lines and terminated as close to the EL2072 package as possible Increasing capacitance on the output of the EL2072 will add phase shift decreasing phase margin and increasing frequency-response peaking A small series resistor before the capacitance decouples this effect and should be used for large capacitance values Please refer to the graphs for the appropriate resistor value to be used 7 EL2072C EL2072C 730 MHz Closed Loop Buffer General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown Elantec Inc reserves the right to make changes in the circuitry or specifications contained herein at any time without notice Elantec Inc assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement WARNING Life Support Policy December 1995 Rev E Elantec Inc 1996 Tarob Court Milpitas CA 95035 Telephone (408) 945-1323 (800) 333-6314 Fax (408) 945-9305 European Office 44-71-482-4596 8 Elantec Inc products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec Inc Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death Users contemplating application of Elantec Inc products in Life Support Systems are requested to contact Elantec Inc factory headquarters to establish suitable terms conditions for these applications Elantec Inc 's warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages Printed in U S A |
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