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19-1908; Rev 0; 5/01
KIT ATION EVALU ABLE AVAIL
Quad LVDS Line Receivers with Integrated Termination
General Description Features
o Integrated Termination Eliminates Four External Resistors (MAX9126) o Pin Compatible with DS90LV032A o Guaranteed 500Mbps Data Rate o 300ps Pulse Skew (max) o Conform to ANSI TIA/EIA-644 LVDS Standard o Single +3.3V Supply o Low 70A Shutdown Supply Current o Fail-Safe Circuit
MAX9125/MAX9126
The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for applications requiring high data rates, low power, and reduced noise. The MAX9125/MAX9126 are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled-impedance media of approximately 100. The transmission media may be printed circuit (PC) board traces or cables. The MAX9125/MAX9126 accept four LVDS differential inputs and translate them to 3.3V CMOS outputs. The MAX9126 features integrated parallel termination resistors (nominally 115), which eliminate the requirement for four discrete termination resistors and reduce stub length. The MAX9125 inputs are high impedance and require an external termination resistor when used in a point-to-point connection. The devices support a wide common-mode input range of 0.05V to 2.35V, allowing for ground potential differences and common-mode noise between the driver and the receiver. A fail-safe feature sets the output high when the inputs are open, or when the inputs are undriven and shorted or parallel terminated. The EN and EN inputs control the high-impedance output and are common to all four receivers. Inputs conform to the ANSI TIA/EIA-644 LVDS standard. The MAX9125/ MAX9126 operate from a single +3.3V supply, are specified for operation from -40C to +85C, and are available in 16-pin TSSOP and SO packages. Refer to the MAX9124 data sheet for a quad LVDS line driver.
Ordering Information
PART MAX9125EUE MAX9125ESE MAX9126EUE MAX9126ESE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 SO 16 TSSOP 16 SO
Typical Application Circuit
LVDS SIGNALS MAX9126
MAX9124
Applications
Digital Copiers Laser Printers Cellular Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution
Pin Configuration appears at end of data sheet.
LVTTL/LVCMOS DATA INPUT
TX
115
RX
TX
115
RX
LVTTL/LVCMOS DATA OUTPUT
TX
115
RX
TX
115
RX
100 SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
________________________________________________________________ Maxim Integrated Products
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Quad LVDS Line Receivers with Integrated Termination MAX9125/MAX9126
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V EN, EN to GND ...........................................-0.3V to (VCC + 0.3V) OUT_ to GND .............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW 16-Pin SO (derate 8.7mW/C above +70C)................696mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection (Human Body Model) IN_+, IN_-, OUT_............7.5kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER LVDS INPUTS (IN_+, IN_-) Differential Input High Threshold Differential Input Low Threshold Input Current (MAX9125) Power-Off Input Current (MAX9125) Input Resistor 1 Input Resistor 2 Differential Input Resistance (MAX9126) LVCMOS/LVTTL OUTPUTS (OUT_) IOH = -4.0mA (MAX9125) Output High Voltage VOH IOH = -4.0mA (MAX9126) Output Low Voltage Output Short-Circuit Current Output High-Impedance Current VOL IOS IOZ Open, undriven short, or undriven 100 parallel termination VID = +100mV Open or undriven short VID = +100mV 2.7 2.7 2.7 2.7 3.2 3.2 3.2 3.2 0.1 -15 -10 0.25 -120 +10 V mA A V VTH VTL IIN_+, IIN_IIN_+, IIN_RIN1 RIN2 RDIFF 0.1V VID 0.6V, 0.6V |VID/2| to 2.4V - |VID/2|, TA =
TYP MAX UNITS
IOL = +4.0mA, VID = -100mV Enabled, VID = +100mV, VOUT_ = 0 (Note 2) Disabled, VOUT_ = 0 or VCC
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Quad LVDS Line Receivers with Integrated Termination
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER LOGIC INPUTS (EN, EN) Input High Voltage Input Low Voltage Input Current SUPPLY Supply Current Disabled Supply Current ICC ICCZ Enabled, inputs open Disabled, inputs open 9 70 15 500 mA A VIH VIL IIN VIN = VCC or 0 2.0 0 -15 VCC 0.8 15 V V A SYMBOL CONDITIONS MIN
MAX9125/MAX9126
|VID/2| to 2.4V - |VID/2|, TA =
TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, CL = 10pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40C to +85C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew [tPHLD - tPLHD] (Note 5) Differential Channel-to-Channel Skew (Note 6) Differential Part-to-Part Skew (Note 7) Differential Part-to-Part Skew (Note 8) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 9) SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX CONDITIONS Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 RL = 2k, Figures 4 and 5 RL = 2k, Figures 4 and 5 RL = 2k, Figures 4 and 5 RL = 2k, Figures 4 and 5 All channels switching 250 300 0.34 0.32 MIN 1.8 1.8 TYP 2.4 2.3 100 MAX 3.3 3.3 300 400 0.8 1.5 1.2 1.2 12 12 17 17 UNITS ns ns ps ps ns ns ns ns ns ns ns ns MHz
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Quad LVDS Line Receivers with Integrated Termination MAX9125/MAX9126
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, CL = 10pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40C to +85C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4) Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH , VTL, and VID. Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes scope probe and test jig capacitance. Note 5: tSKD1 is the magnitude difference of differential propagation delays in a channel; tSKD1 = |tPHLD - tPLHD|. Note 6: tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same part. Note 7: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at the same VCC and within 5C of each other. Note 8: tSKD4 is the magnitude difference of any differential propagation delays between parts operating over rated conditions. Note 9: fMAX generator output conditions: tR = tF < 1ns (0% to 100%), 50% duty cycle, VOL = 1.1V, VOH = 1.3V. Receiver output criteria: 60% to 40% duty cycle, VOL = 0.4V (max), VOH = 2.7V (min), load = 10pF.
Typical Operating Characteristics
(VCC = +3.3V, |VID| = 200mV, VCM = +1.2V, CL = 10pF, frequency = 10MHz, TA = +25C, unless otherwise noted.) (Figures 2 and 3)
SUPPLY CURRENT vs. SWITCHING FREQUENCY, FOUR CHANNELS SWITCHING
MAX9125/6 toc01
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9125/6 toc02
DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9125/6 toc03
100 90 80 SUPPLY CURRENT (mA) 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 VCC = +3V VCC = +3.3V VCC = +3.6V
2.8
2.8 2.7 2.6 2.5 2.4 2.3 2.2 tPHLD tPLHD
2.6 tPHLD 2.4
2.2
tPLHD
2.0 1000 -40 -15 10 35 60 85 SWITCHING FREQUENCY (MHz) TEMPERATURE (C)
100
500
900
1300
1700
2100
2500
DIFFERENTIAL INPUT VOLTAGE (mV)
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Quad LVDS Line Receivers with Integrated Termination
Typical Operating Characteristics (continued)
(VCC = +3.3V, |VID| = 200mV, VCM = +1.2V, CL = 10pF, frequency = 10MHz, TA = +25C, unless otherwise noted (Figures 2 and 3).)
MAX9125/MAX9126
DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE
MAX9125/6 toc04
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
MAX9125/6 toc05
PULSE SKEW vs. SUPPLY VOLTAGE
MAX9125/6 toc06
2.6 DIFFERENTIAL PROPAGATION DELAY (ns)
2.6 DIFFERENTIAL PROPAGATION DELAY (ns)
200 175 150 SKEW (ps) 125 100
2.5 tPHLD 2.4
2.5 tPHLD 2.4
2.3 tPLHD 2.2 0 0.5 1.0 1.5 2.0 2.5 COMMON-MODE VOLTAGE (V)
2.3 tPLHD 2.2 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 75 50 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
PULSE SKEW vs. TEMPERATURE
MAX9125/6 toc07
TRANSITION TIME vs. CAPACITIVE LOAD
900 800 TRANSITION TIME (ps) 700 600 500 400 300 200 100 tTHL tTLH
MAX9125/6 toc08
200 175 150 SKEW (ps) 125 100 75 50 -40 -15 10 35 60 85 TEMPERATURE (C)
1000
0 5 10 15 20 25 CAPACITIVE LOAD (pF)
Pin Description
PIN 1, 7, 9, 15 2, 6, 10, 14 3, 5, 11, 13 4, 12 8 16 NAME IN_IN_+ OUT_ EN, EN GND VCC Inverting Differential Receiver Inputs Noninverting Differential Receiver Inputs LVCMOS/LVTTL Receiver Outputs Receiver Enable Inputs. When EN = low and EN = high, the outputs are disabled and in high impedance. For other combinations of EN and EN, the outputs are active. Ground Power Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. FUNCTION
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Quad LVDS Line Receivers with Integrated Termination MAX9125/MAX9126
Table 1. Input/Output Function Table
ENABLES EN L EN H VID +100mV VID -100mV All other combinations of ENABLE inputs MAX9125 MAX9126 Open, undriven short, or undriven 100 parallel termination Open or undriven short INPUTS (IN_+) - (IN_-) X OUTPUT OUT_ Z H L
H
VCC RIN2 RIN2
VCC
VCC - 0.3V IN_+ RIN1 OUT_ RIN1 IN_MAX9125 IN_RDIFF RIN1 IN_+ RIN1
VCC - 0.3V
OUT_
MAX9126
Figure 1. Inputs with Internal Fail-Safe Circuitry
Detailed Description
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9125/MAX9126 are 500Mbps, four-channel LVDS receivers intended for high-speed, point-to-point, low-power applications. Each channel accepts an LVDS input and translates it to an LVTTL/LVCMOS output. The receiver is capable of detecting differential signals as low as 100mV and as high as 1V within an
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input voltage range of 0 to 2.4V. The 250mV to 400mV differential output of an LVDS driver is nominally centered around a +1.2V offset. This offset, coupled with the receiver's 0 to 2.4V input voltage range, allows an approximate 1V shift in the signal (as seen by the receiver). This allows for a difference in ground references of the transmitter and the receiver, the commonmode effects of coupled noise, or both. The LVDS standards specify an input voltage range of 0 to 2.4V referenced to receiver ground. The MAX9126 has an integrated termination resistor internally connected across each receiver input. The internal termination saves board space, eases layout, and reduces "stub length" compared to an external termination resistor. In other words, the transmission line is terminated on the IC.
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Quad LVDS Line Receivers with Integrated Termination MAX9125/MAX9126
IN_+ PULSE** GENERATOR IN_50* 50* CL OUT_
RECEIVER ENABLED 1/4 MAX9125/MAX9126
*50 REQUIRED FOR PULSE GENERATOR. **WHEN TESTING MAX9126, ADJUST THE PULSE GENERATOR OUTPUT TO ACCOUNT FOR INTERNAL TERMINATION RESISTOR.
Figure 2. Transition Time and Propagation Delay Test Circuit
IN_O (DIFFERENTIAL) IN_+ tPLHD tPHLD VOH 80% NOTE: VCM = (VIN_- + VIN_+) 2 50% 50% 80% VID O (DIFFERENTIAL)
20% OUT_ tTLH tTHL
20% VOL
Figure 3. Transition Time and Propagation Delay Timing Diagram
VCC
S1
IN_+ GENERATOR 50 EN EN 1/4 MAX9125/MAX9126 IN_-
RL DEVICE UNDER TEST OUT_ CL
CL INCLUDES LOAD AND TEST JIG CAPACITANCE. S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS. S1 = GND FOR tPZH AND tPHZ MEASUREMENTS.
Figure 4. High-Z Delay Test Circuit
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Quad LVDS Line Receivers with Integrated Termination MAX9125/MAX9126
EN WHEN EN = VCC 1.5V 1.5V 0 3V
3V 1.5V EN WHEN EN = GND tPZL tPLZ OUTPUT WHEN VID = -100mV OUTPUT WHEN VID = +100mV 0.5V tPHZ 0.5V 50% GND tPZH VOH VCC 50% VOL 1.5V 0
Figure 5. High-Z Delay Waveforms
Fail-Safe
The fail-safe feature of the MAX9125/MAX9126 sets the output high when: * Inputs are open. * Inputs are undriven and shorted. * Inputs are undriven and terminated. A fail-safe circuit is important because under these conditions, noise at the inputs may switch the receiver and it may appear to the system that data is being received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when the LVDS driver outputs are high impedance. A short condition can occur because of a cable failure. The fail-safe input network (Figure 1) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). When the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than VCC - 0.3V and the fail-safe circuit is not activated. If the inputs are open or if the inputs are undriven and shorted or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the fail-safe circuit pulls both inputs above VCC 0.3V, activating the fail-safe circuit and forcing the output high.
Applications Information
Power-Supply Bypassing
Bypass the VCC pin with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel, as close to the device as possible, with the smaller valued capacitor closest to VCC.
Differential Traces
Input trace characteristics affect the performance of the MAX9125/MAX9126. Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is also matched to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Each channel's differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and vias to further prevent impedance discontinuities.
Cables and Connectors
Transmission media typically have a controlled differential impedance of 100. Use cables and connectors
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Quad LVDS Line Receivers with Integrated Termination
that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. For LVDS applications, use a four-layer PC board that provides separate power, ground, LVDS signals, and output signals. Isolate the input LVDS signals from the output LVCMOS/LVTTL signals to prevent coupling. Separate the input LVDS signal plane from the LVCMOS/LVTTL output signal plane with the power and ground planes for best results.
MAX9125/MAX9126
Termination
The MAX9126 has an integrated termination resistor connected across the inputs of each receiver. The value of the integrated resistor is specified in the DC characteristics. The MAX9125 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line. Termination resistance values range between 90 and 132, depending on the characteristic impedance of the transmission medium. When using the MAX9125, minimize the distance between the input termination resistors and the MAX9125 receiver inputs. Use 1% surface-mount resistors.
Chip Information
TRANSISTOR COUNT: 940 PROCESS: CMOS
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Quad LVDS Line Receivers with Integrated Termination MAX9125/MAX9126
Functional Diagram
VCC IN1+ Rx IN1OUT1 IN1IN1+ RDIFF Rx OUT1 VCC
IN2+ Rx IN2OUT2
IN2+ RDIFF IN2Rx OUT2
IN3+ Rx IN3OUT3
IN3+ RDIFF IN3Rx OUT3
IN4+ Rx IN4OUT4
IN4+ RDIFF IN4Rx OUT4
EN EN MAX9125 GND
EN EN MAX9126 GND
Pin Configuration
TOP VIEW
IN1- 1 IN1+ 2 OUT1 3 EN 4 OUT2 5 IN2+ 6 IN2- 7 GND 8 16 VCC 15 IN414 IN4+
MAX9125 MAX9126
13 OUT4 12 EN 11 OUT3 10 IN3+ 9 IN3-
TSSOP/SO 10 ______________________________________________________________________________________
Quad LVDS Line Receivers with Integrated Termination
Package Information
TSSOP,NO PADS.EPS
MAX9125/MAX9126
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Quad LVDS Line Receivers with Integrated Termination MAX9125/MAX9126
Package Information (continued)
SOICN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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