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CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
Integrated Device Technology, Inc.
IDT72021 IDT72031 IDT72041
FEATURES:
* First-In/First-Out Dual-Port memory * Bit organization - IDT72021--1K x 9 - IDT72031--2K x 9 - IDT72041--4K x 9 * Ultra high speed - IDT72021--25ns access time - IDT72031--35ns access time - IDT72041--35ns access time * Easily expandable in word depth and/or width * Asynchronous and simultaneous read and write * Functionally equivalent to IDT7202/03/04 with Output Enable (OE) and Almost Empty/Almost Full Flag (AEF) * Four status flags: Full, Empty, Half-Full (single device mode), and Almost Empty/Almost Full (7/8 empty or 7/8 full in single device mode) * Output Enable controls the data output port * Auto-retransmit capability * Available in 32-pin DIP and PLCC * Military product compliant to MIL-STD-883, Class B * Industrial temperature range (-40oC to +85oC) is avail able, tested to military electrical specifications
DESCRIPTION:
IDT72021/031/041s are high-speed, low-power, dual-port memory devices commonly known as FIFOs (First-In/FirstOut). Data can be written into and read from the memory at independent rates. The order of information stored and extracted does not change, but the rate of data entering the FIFO might be different than the rate leaving the FIFO. Unlike a Static RAM, no address information is required because the read and write pointers advance sequentially. The IDT72021/ 031/041s can perform asynchronous and simultaneous read and write operations. There are four status flags, (HF, FF, EF, AEF) to monitor data overflow and underflow. Output Enable (OE) is provided to control the flow of data through the output port. Additional key features are Write (W), Read (R), Retransmit (RT), First Load (FL), Expansion In (XI) and Expansion Out (XO). The IDT72021/031/041s are designed for those applications requiring data control flags and Output Enable (OE) in multiprocessing and rate buffer applications. The IDT72021/031/041s are fabricated using IDT's CMOS technology. Military grade product is manufactured in compliance with the latest version of MIL-STD-883, Class B, for high reliability systems.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUT (D0-D8)
W
WRITE CONTROL
1 2
WRITE POINTER 1024/ 2048/ 4096 THREESTATE BUFFERS
RAM ARRAY 1024 x 9 2048 x 9 4096 x 9
READ POINTER
OE
RESET LOGIC
RS
FL/RT
R
READ CONTROL FLAG LOGIC EXPANSION LOGIC
DATA OUTPUTS (Q0-Q8)
EF FF AEF
XI
XO/HF
2677 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2677/7
5.09
1
IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
VCC D3 D8 D5
VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D32-1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC D4 D5 D6 D7
W
INDEX
VCC D4
W
D8 D3 D2
432 D2 D1 D0 5 6 7 8 9 10 11 12 13
1
32 31 30 29 28 27 26 25 24 23 22 21 D6 D7
D1 D0
XI AEF FF
Q0 Q1 Q2
J32-1
FL/RT RS OE EF XO/HF
Q7 Q6
XI AEF FF
Q0 Q1 Q2 Q3 Q8
FL/RT RS OE EF XO/HF
Q7 Q6 Q5 Q4
14 15 16 17 18 19 20
R
GND
2677 drw 02
Q3 Q8 GND
GND
Q4 Q5
R
GND
2677 drw 03
PLCC TOP VIEW
DIP TOP VIEW
PIN DESCRIPTIONS
Symbol D0-D8 Name Inputs Reset I/O I I Data inputs for 9-bit wide data. When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM array. HF and FF go HIGH, and AEF and EF go LOW. A reset is required before an initial WRITE after power-up. R and W must be HIGH during RS cycle. When WRITE is LOW, data can be written into the RAM array sequentially, independent of READ. In order for WRITE to be active, FF must be HIGH. When the FIFO is full (FF-LOW), the internal WRITE operation is blocked. When READ is LOW, data can be read from the RAM array sequentially, independent of WRITE. In order for READ to be active, EF must be HIGH. When the FIFO is empty (EF-LOW), the internal READ operation is blocked. The three-state output buffer is controlled by the read signal and the external output control (OE). This is a dual-purpose input. In the single device configuration (XI grounded), activating retransmit (FL/RT-LOW) will set the internal READ pointer to the first location. There is no effect on the WRITE pointer. R and W must be HIGH before setting FL/RT LOW. Retransmit is not compatible with depth expansion. In the depth expansion configuration, FL/RT-LOW indicates the first activated device. In the single device configuration, XI is grounded. In depth expansion or daisy chain expansion, XI is connected to XO (expansion out) of the previous device. When OE is set HIGH, the data flow through the three-state output buffer is inhibited regardless of an active READ operation. A read operation does increment the read pointer in this situation. When OE is set LOW, Q0-Q8 are still in a HIGH impedance condition if no READ occurs. For a complete READ operation with data appearing on Q0-Q8, both R and OE should be asserted LOW. When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is HIGH, the device is not full. When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH, the device is not empty. When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH, the device is greater than 1/8 full, but less than 7/8 full. This is a dual purpose output. In the single device configuration (XI grounded), the device is more than half full when HF is LOW. In the depth expansion configuration (XO connected to XI of the next device), a pulse is sent from XO to XI when the last location in the RAM array is filled. Data outputs for 9-bit wide data.
2677 tbl 01
Description
RS W R FL/RT
Write
I
Read
I
First Load/ Retransmit
I
XI OE
Expansion In Output Enable
I I
FF EF AEF XO/HF
Full Flag Empty Flag Almost-Empty/ Almost-Full Flag Expansion Out/ Half-Full Flag
O O O O
Q0-Q8
Outputs
O
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IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATUS FLAG
Number of Words in FIFO 1K 0 1-127 128-512 513-896 897-1023 1024 2K 0 1-255 256-1024 1025-1792 1793-2047 2048 4K 0 1-511 512-2048 2049-3584 3585-4095 4096
CAPACITANCE (TA = +25C, f = 1.0 MHz)
FF AEF HF
H H H H H L L L H H L L H H H L L L
EF
L H H H H H
Symbol CIN COUT
Parameter(1) Input Capacitance Output Capacitance
Condition VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
2677 tbl 03
NOTE: 1. These parameters are sampled and not 100% tested.
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCCM Parameter Military Supply Voltage Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input High Voltage Military Input Low Voltage Commercial and Military Min. 4.5 4.5 0 2.0 2.2 -- Typ. 5.0 5.0 0 -- -- -- Max. 5.5 5.5 0 -- -- 0.8 Unit V V V V V V
2677 tbl l 02
ABSOLUTE MAXIMUM RATINGS
Symbol Rating VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature IOUT DC Output Current
(1)
Com'l. Mil. Unit -0.5 to +7.0 -0.5 to +7.0 V
VCCC GND VIH
0 to +70
-55 to +125
C C C mA VIH VIL(1)
-55 to +125 -65 to +135 -55 to +125 -65 to +155 50 50
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
2677 tbl 05
NOTE: 2677 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty.
5.09
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IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS -- IDT72021
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5V10%, TA = -55C to +125C)
IDT72021 Commercial tA =25,35ns Symbol ILI
(1)
IDT72021 Military tA =30,40ns Min. -10 -10 2.4 -- -- -- -- Typ. -- -- -- -- -- -- -- Max. 10 10 -- 0.4 140 20 900 1 10 -- -1
IDT72021 Commercial tA =50ns Min. Typ. -- -- -- -- 50 5 -- Max. 1 10 -- 0.4 80 8 500 -10 -10 2.4 -- -- -- --
IDT72021 Military tA =50ns Min. Typ. Max. -- -- -- -- 70 8 -- 10 10 -- 0.4 100 15 900 Unit A A V V mA mA A
2677 tbl 06
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage IOH = -2mA Output Logic "0" Voltage IOL = 8mA Active Power Supply Current Standby Current (R = W = RS = FL/RT = VIH) Power Down Current (All Input = VCC - 0.2V)
Min. -1 -10 2.4 -- -- -- --
Typ. -- -- -- -- -- -- --
Max.
ILO(2) VOH VOL ICC1(3,4) ICC2(3) ICC3(3)
-10 2.4 -- -- -- --
0.4 120 12 500
DC ELECTRICAL CHARACTERISTICS -- IDT72031, IDT72041
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5V10%, TA = -55C to +125C)
IDT72031 IDT72041 Commercial tA =35,50ns Symbol ILI
(1)
IDT72031 IDT72041 Military tA =40,50ns Min. -10 -10 2.4 -- -- -- -- Typ. Max. Unit -- -- -- -- 100 12 -- 10 10 -- 0.4 150 25 4 A A V V mA mA mA
2677 tbl 07
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage IOUT = -2mA Output Logic "0" Voltage IOUT = 8mA
Min. -1 -10 2.4 -- -- -- --
Typ. -- -- -- -- 75 8 --
Max. 1 10 -- 0.4 120 12 2
ILO(2) VOH VOL ICC1
(3,5)
Active Power Supply Current Standby Current (R = W = RS = FL/RT = VIH) Power Down Current (All Input = VCC - 0.2V)
ICC2(3) ICC3(3)
NOTES: 1. Measurements with 0.4 VIN VCC. 2. R VIH, 0.4 VOUT VCC. 3. ICC measurements are made with OE = HIGH. 4. Tested at f = 20MHz. 5. Tested at f = 15.3 MHz.
5.09
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IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS -- IDT72021(1)
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5V10%, TA = -55C to +125C)
Com'l 72021L25 Symbol fS tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSS tRSR tRTC tRT tRTR tRSF1 tRSF2 tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tRF tWF tOEHZ tOELZ tAOE Parameter Shift Frequency Min. Max. -- 35 -- 10 25 5 5 5 -- 35 25 10 15 0 35 25 25 10 35 25 10 -- -- -- -- 25 -- -- -- -- 25 -- -- 0 0 -- 28.5 -- 25 -- -- -- -- -- 18 -- -- -- -- -- -- -- -- -- -- -- -- 35 35 25 25 -- 25 25 35 35 -- 35 35 12 12 15 Mil. 72021L30 Min. -- 40 -- 10 30 5 5 5 -- 40 30 10 18 0 40 30 30 10 40 30 10 -- -- -- -- 30 -- -- -- -- 30 -- -- 0 0 -- Max. 25 -- 30 -- -- -- -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- 40 40 30 30 -- 30 30 40 40 -- 40 40 15 15 18 Com'l 72021L35 Min. -- 45 -- 10 35 5 5 5 -- 45 35 10 18 0 45 35 35 10 45 35 10 -- -- -- -- 35 -- -- -- -- 35 -- -- 0 0 -- Max. 22.2 -- 35 -- -- -- -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- 45 45 30 30 -- 30 30 45 45 -- 45 45 17 17 20 Mil. 72021L40 Min. -- 50 -- 10 40 5 5 5 -- 50 40 10 20 0 50 40 40 10 50 40 10 -- -- -- -- 40 -- -- -- -- 40 -- -- 0 0 -- Max. 20 -- 40 -- -- -- -- -- 25 -- -- -- -- -- -- -- -- -- -- -- -- 50 50 35 35 -- 35 35 50 50 -- 50 50 20 20 25 Com'l & Mil. 72021L50 Min. Max. Unit -- 65 -- 15 50 10 5 5 -- 65 50 15 30 5 65 50 50 15 65 50 15 -- -- -- -- 50 -- -- -- -- 50 -- -- 0 0 -- 15 -- 50 -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- -- -- -- 65 65 45 45 -- 45 45 65 65 -- 65 65 25 25 30 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2677 tbl 08
R Cycle Time
Access Time
R Recovery Time R Pulse Width(2) R Pulse LOW to Data Bus at Low-Z(3) W Pulse HIGH to Data Bus at Low-Z(3,4) Data Valid from R Pulse HIGH R Pulse HIGH to Data Bus at High-Z(3) W Cycle Time W Pulse Width(2) W Recovery Time
Data Set-up Time Data Hold Time
RS Cycle Time RS Pulse Width(2) RS Set-up Time RS Recovery Time RT Cycle Time RT Pulse Width(2) RT Recovery Time RS to EF and AEF LOW RS to HF and FF HIGH R LOW to EF LOW R HIGH to FF HIGH R Pulse Width After EF HIGH W HIGH to EF HIGH W LOW to EF LOW W LOW to HF LOW R HIGH to HF HIGH W Pulse Width after FF HIGH R HIGH to Transitioning AEF W LOW to Transitioning AEF OE HIGH to High-Z (Disable)(3) OE LOW to Low-Z (Enable)(3) OE LOW Data Valid (Q0-Q8)
NOTES: 1. Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum value are not allowed. 3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode.
5.09
5
IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS -- IDT72031, IDT72041(1)
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5V10%, TA = -55C to +125C)
Com'l 72031L35 72041L35 Symbol fS tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSS tRSR tRTC tRT tRTR tRSF1 tRSF2 tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tRF tWF tOEHZ tOELZ tAOE Shift Frequency Parameter Min. -- 45 -- 10 35 5 5 5 -- 45 35 10 18 0 45 35 35 10 45 35 10 -- -- -- -- 35 -- -- -- -- 35 -- -- 0 0 -- Max. 22.2 -- 35 -- -- -- -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- 45 45 30 30 -- 30 30 45 45 -- 45 45 17 17 20 Mil. 72031L40 72041L40 Min. -- 50 -- 10 40 5 5 5 -- 50 40 10 20 0 50 40 40 10 50 40 10 -- -- -- -- 40 -- -- -- -- 40 -- -- 0 0 -- Max. 20 -- 40 -- -- -- -- -- 25 -- -- -- -- -- -- -- -- -- -- -- -- 50 50 35 35 -- 35 35 50 50 -- 50 50 20 20 25 Com'l and Mil. 72031L50 72041L50 Min. -- 65 -- 15 50 10 5 5 -- 65 50 15 30 5 65 50 50 15 65 50 15 -- -- -- -- 50 -- -- -- -- 50 -- -- 0 0 -- Max. 15 -- 50 -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- -- -- -- 65 65 45 45 -- 45 45 65 65 -- 65 65 25 25 30 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2677 tbl 09
R Cycle Time
Access Time
R Recovery Time R Pulse Width(2) R Pulse LOW to Data Bus at Low-Z(3) W Pulse HIGH to Data Bus at Low-Z(3,4) Data Valid from R Pulse HIGH R Pulse HIGH to Data Bus at High-Z(3) W Cycle Time W Pulse Width(2) W Recovery Time
Data Set-up Time Data Hold Time
RS Cycle Time RS Pulse Width(2) RS Set-up Time RS Recovery Time RT Cycle Time RT Pulse Width(2) RT Recovery Time RS to EF and AEF LOW RS to HF and FF HIGH R LOW to EF LOW R HIGH to FF HIGH R Pulse Width After EF HIGH W HIGH to EF HIGH W LOW to EF LOW W LOW to HF LOW R HIGH to HF HIGH W Pulse Width after FF HIGH R HIGH to Transitioning AEF W LOW to Transitioning AEF OE HIGH to High-Z (Disable)(3) OE LOW to Low-Z (Enable)(3) OE LOW Data Valid (Q0-Q8)
NOTES: 1. Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum value are not allowed. 3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode.
5.09
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IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure 1
2677 tbl 10
5V
1.1K TO OUTPUT PIN 680 30pF*
2677 drw 04
or equivalent circuit
Figure 1. Output Load * Includes scope and jig capacitances.
t RSC t RS RS t RSS W t RSS R t RSF1 AEF, EF t RSF2 HF, FF
2677 drw 05
t RSR
Figure 2. Reset NOTES: 1. EF, FF, HF, and AEF may change status during Reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS.
t RC t RR tA R t RLZ Q 0 -Q 8 t WPW W tDS D 0 -D 8 tDH t DV DATA OUT VALID t WC t WR tA
t RPW
t RHZ DATA OUT VALID
DATA IN VALID
DATA IN VALID
2677 drw 06
Figure 3. Asynchronous Write and Read Operation NOTE: 1. Assume OE is asserted LOW.
5.09
7
IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LAST WRITE R
IGNORED WRITE
FIRST READ
ADDITIONAL READS
FIRST WRITE
W t WFF FF
2677 drw 07
tRFF
Figure 4. Full Flag From Last Write to First Read
LAST READ W
IGNORED READ
FIRST WRITE
ADDITIONAL WRITES
FIRST READ
R t REF EF tA
(1)
tWEF
DATA OUT
VALID
VALID
2677 drw 08
Figure 5. Empty Flag From Last Read to First Write NOTE: 1. Assume OE is asserted LOW.
tRTC tRT
RT
t RTR
W,R AEF, HF, EF, FF
Figure 6. Retransmit
FLAG VALID
2677 drw 09
5.09
8
IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W t WEF EF t RPE R
2677 drw 10
Figure 7. Empty Flag Timing Figure 9. Almost-Empty/Almost-Full Flag and Half-Full Timings
R t RFF FF t WPF W
2677 drw 11
Figure 8. Full Flag Timing
W
R
HALF-FULL
tWHF
(1/2) HALF-FULL + 1 (7/8 FULL)
tRHF
HALF-FULL (1/2)
HF tWF
tRF
ALMOST-FULL (7/8 FULL + 1)
(7/8 FULL)
AEF
ALMOST-EMPTY (1/8 FULL-1)
AEF
(1/8 FULL)
ALMOST-EMPTY (1/8 FULL-1)
2677 drw 12
Figure 9. Almost-Empty/Almost-Full Flag and Half-Full Timings
tRC
tRR
R
TERMINATE READ CYCLE
OE
tRLZ Q0-8
tA
tOEHZ DATA 1
SECOND READ BY CONTROLLING OE tAOE tOELZ DATA 1
tDV HIGH IMPEDANCE
2677 drw 13
Figure 10. Output Enable and Read Operation Timings
5.09
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IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
WRITE TO LAST PHYSICAL LOCATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W R t XOL XO t XOH
READ FROM LAST PHYSICAL LOCATION
t XOL
t XOH
2677 drw 14
Figure 11. Expansion Out
t XI t W
XIS
XI
t XIR
WRITE TO FIRST PHYSICAL LOCATION
t XIS R
Figure 12. Expansion In
READ FROM FIRST PHYSICAL LOCATION
2677 drw 15
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION The IDT72021/031/041 is in the Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 13).
(HALF-FULL FLAG) HF WRITE (W) 9 DATA IN (D) FULL FLAG (FF) RESET (RS)
AEF READ (R) 9
IDT 72021/031/041
DATA OUT (Q) EMPTY FLAG (EF) RETRANSMIT (RT) OUTPUT ENABLE (OE)
EXPANSION IN (XI)
2677 drw 16
Figure 13. Block Diagram of Single 1K/2K/4K x 9 FIFO
5.09
10
IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF, FF, HF, and AEF) can be detected from any one
device. Figure 14 demonstrates an 18-bit word width by using two IDT72021/031/041 devices. Any word width can be attained by adding additional IDT72021/031/041s.
AEF 18 DATA IN (D) 9
HF 9
AEF
HF
OUTPUT ENABLE (OE) WRITE (W) FULL FLAG (FF) RESET (RS) 9 9 RETRANSMIT (RT) IDT 72021/031/041 IDT 72021/031/041 READ (R) EMPTY FLAG (EF)
XI
XI 18 DATA OUT (Q)
2677 drw 17
Figure 14. Block Diagram of 1K/2K/4K x 18 FIFO Memory Used in Width Expansion Configuration NOTE: 1. Flag detection is accomplished by monitoring the FF, EF, HF and AEF signals on either (any) device used in the width expansion configuration. Do not connect any output signals together.
DEPTH EXPANSION (DAISY CHAIN) MODE The IDT72021/031/041 can easily be adapted to applications when the requirements are for greater than 1K/2K/4K words. Figure 15 demonstrates Depth Expansion using three IDT72021/031/041s. Any depth can be attained by adding additional devices. The IDT72021/031/041 operates in the Depth Expansion configuration when the following conditions are met: 1. The first device must be designed by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 15. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 15. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. For additional information refer to Tech Note 9: "Cascading FIFOs or FIFO Modules". COMPOUND EXPANSION MODE The two expansion techniques described above can be applied together in a straight forward manner to achieve large FIFO arrays (see Figure 16).
BIDIRECTIONAL MODE Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT72021/031/041s as shown in Figure 17. Care must be taken to assure that the appropriate flag is monitored by each system (i.e., FF is monitored on the device where W is used; EF is monitored on the device where R is used). Both Depth Expansion and Width Expansion may be used in this mode. DATA FLOW-THROUGH MODES Two types of flow-through modes are permitted: a read flow-through and write flow-through mode. For the read flowthrough mode (Figure 18), the FIFO permits the reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of W, called the first write edge. It remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode after tRHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. In the interval of time that R was LOW, more words can be written to the FIFO (the subsequent writes after the first write edge will be deassert the Empty Flag); however, the same word (written on the first write edge), presented to the output bus as the read pointer, would not be incremented when R was LOW. On toggling R, the other words that are written to the FIFO will appear on the output bus as in the read cycle timings.
5.09
11
IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line, being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W
line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. For additional information refer to Tech Note 8: "Operating FIFOs on Full and Empty Boundary Conditions" and Tech Note 6: "Designing with FIFOs".
TRUTH TABLES TABLE I--RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Mode Reset Retransmit Read/Write
RS
0 1 1
Inputs
RT
X 0 1
XI
0 0 0
Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Unchanged Increment(1) Increment(1)
EF
0 X X
Outputs
FF
1 X X
HF
1 X X
AEF
0 X X
2677 tbl 11
NOTE: 1. Pointer will increment if flag is HIGH.
TABLE II--RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Mode Reset First Device Reset All Other Devices Read/Write
RS
0 0 1
Inputs
FL
0 1 X
XI
(1) (1) (1)
Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Location Zero X X
EF
0 0 X
Outputs
FF
1 1 X
NOTE: 2677 tbl 12 1. XI is connected to XO of previous device. See Figure 15. RS = Reset Input FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output, XI = Expansion Input, HF = Half-Full Flag Output, AEF = Almost Empty/Almost Full Flag.
XO W FF D 9 9 IDT 72021/ 031/041 EF 9 FL XI XO FULL 9 FF IDT 72021/ 031/041 FL XI XO FF 9 RS FL XI
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R Q VCC
EF
EMPTY
EF IDT 72021/ 031/041
Figure 15. Block Diagram of 3K/6K/12K x 9 FIFO Memory (Depth Expansion) NOTE: 1. IDT only guarantees depth expansion with identical IDT part numbers and speed. 5.09 12
IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
***
Q0 -Q N
R, W, RS
IDT72021/ 031/041 DEPTH EXPANSION BLOCK
IDT72021/ 031/041 DEPTH EXPANSION BLOCK
***
IDT72021/ 031/041 DEPTH EXPANSION BLOCK
D 0 -D N
***
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Figure 16. Compound FIFO Expansion NOTES: 1. For depth expansion block see section od Depth Expansion and Figure 15. 2. For Flag detection see section on Width Expansion and Figure 14.
WA FFA DA 0-8 AEF
SYSTEM A IDT IDT 72021/ 7201A 031/041
RB EFB HFB QB 0-8
SYSTEM B
QA 0-8 RA HFA EFA
IDT 72021/ 031/041
DB 0-8 WB FFB
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AEF
Figure 17. Bidirectional FIFO Mode
DATA IN
W t RPE R
EF t REF t WEF t WLZ DATA OUT
(1)
tA DATA OUT VALID
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Figure 18. Read Data Flow-Through Mode NOTE: 1. Assume OE is asserted LOW.
5.09
13
IDT72021, IDT72031, IDT72041 CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
R t WPF W t RFF FF t WFF DATA IN tA DATA OUT
(1)
t DH
DATA IN VALID t DS DATA OUT VALID
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Figure 19. Write Data Flow-Through Mode NOTE: 1. Assume OE is asserted LOW.
ORDERING INFORMATION
IDT XXXXX Device Type X Power X Speed X Package X Process/ Temperature Range Blank B Commercial (0C to+70C) Military (-55C to+125C) Compliant to MIL-STD-883, Class B
D J
CERDIP Plastic Leaded Chip Carrier
25 30 35 40 50
72021-Com'l. Only 72021-Mil. Only 72021/031/041-Com'l. Only 72021/031/041-Mil. Only 72021/031/041-Com'l & Mil.
Access Time (tA) Speed in Nanoseconds
L 72021 72031 72041
Low Power 1024 x 9-Bit FIFO 2048 x 9-Bit FIFO 4096 x 9-Bit FIFO
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5.09
14

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