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CXD2464R
Timing Generator for LCD Panels For the availability of this product, please contact the sales office.
Description The CXD2464R is a timing signal generator for driving the LCX026, LCX016 and LCX012BL LCD panels. This chip has a built-in serial interface circuit which supports various XGA, SVGA and VGA signals, and (double speed) NTSC and PAL signals through external control from a microcomputer, etc. Features * Generates the LCX026/LCX016/LCX012BL drive pulse. * Supports various SVGA (horizontal scanning frequency: 35 to 54kHz, vertical scanning frequency: 56 to 86Hz) and VGA (horizontal scanning frequency: 31 to 38kHz, vertical scanning frequency: 59 to 75Hz) signals. * Supports simple (skip scan) display of XGA signals (1024 x 768 dots, horizontal scanning frequency: 57kHz, vertical scanning frequency: 71Hz or less, clock frequency: 62.5MHz or less). * Supports simple (skip scan) display of SVGA signals (800 x 600 dots). * Supports Macintosh16 signals (LCX016) * Supports PC-98 signals (640 x 400 dots, horizontal scanning frequency: 24 to 38kHz, vertical scanning frequency: 56 to 86Hz). * Supports NTSC and PAL signals * Line double-speed display realized with a built-in double-speed controller (clock frequency: 33.3MHz or less) (Line memory PD485505: NEC) * Allows control of sample-and-hold position of CXA2112R sample-and-hold driver. * Supports up/down inversion and/or right/left inversion. * Supports line inversion and field inversion * AC drive of LCD panels during no signal Note) Supported signals vary according to LCD panel. 64 pin LQFP (Plastic)
Applications LCD projectors, etc. Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25C, VSS = 0V) * Supply voltage VDD VSS - 0.5 to +7.0 V * Input voltage VI VSS - 0.5 to VDD + 0.5 V * Output voltage VO VSS - 0.5 to VDD + 0.5 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDD 4.5 to 5.5 * Operating temperature Topr -20 to +75
V C
Note) "Macintosh" is a registered trademark of Apple Computer Inc.. "PC-98" is a registered trademark of NEC. "VGA" is a registered trademark of IBM Corp.. Other company names and product names, etc. contained in these materials are trademarks or registered trademarks of the respective companies. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98327-PS
CXD2464R
Block Diagram
CKI1 XCLR
19 24 SYSTEM CLEAR MASTER CLOCK AUX. PLL COUNTER 56 8 23 40 55 AUX. PLL DECODER V-SYNC SEPARATOR V-RESET PULSE GENERATOR 2 VSS VDD
17
CKI2
64
VSYNC
HD 38 RSTR 54 RCK 57 RSTW 58 WCK 59 HDN 63
PLL COUNTER
PLL DECODER
V-CONTROL COUNTER
PLL PHASE COMPARATOR H-POSITION COUNTER
H-SYNC DETECTOR V-POSITION COUNTER
1
HSYNC
HST 27 HCK1 28 HCK2 29 BLK 30 CLR 31 ENB 32 PCG 36 CLP1 39 CLP2 41 PRG 42
H-POSITION DECODER
V POSITION DECODER
H-TIMING PULSE GENERATOR
33 VCK V-TIMING PULSE GENERATOR 34 VST 41 FLDO 43 FRP 44 XFRP
PULSE ELIMINATOR
FIELD & LINE CONTROLLER
ADDITIONAL PULSE GENERATOR
AUX. V-COUNTER DECODER
XVS 50 XHS 51 IRACT 52 ORACT 53 20 21 22 25 26 37 45 46 47 48 49 SERIAL DATA I/F
60 SCTR 61 SCLK 62 SDAT
MODE2
SHPA
DWN
XRGT
MODE3
MODE1
3
4
5
6
7
TEST 9 10 11 12 13 14 15 16 18 35
Note) CLP2 and FLDO pulses share the same pins.
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SHPC
SHPD
RGT
SHPB
INV
CXD2464R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol HSYNC VSYNC TST0 TST1 TST2 TST3 TST4 VSS0 TST5 TST6 TST7 TST8 TST9 TST10 TST11 TST12 CKI2 TST13 XCLR MODE3 MODE2 MODE1 VSS1 VDD0 RGT XRGT HST HCK1 HCK2 BLK CLR ENB VCK I/O I I -- -- -- -- -- -- -- -- -- -- -- -- -- -- I I I O O O -- -- O O O O O O O O O Description Horizontal sync signal input pin Vertical sync signal input pin Test pin (Connect to GND.) Test pin (Connect to VDD.) Test pin (Not connected.) Test pin (Connect to GND.) Test pin (Not connected.) GND Test pin (Connect to GND.) Test pin (Connect to VDD.) Test pin (Not connected.) Test pin (Not connected.) Test pin (Not connected.) Test pin (Not connected.) Test pin (Not connected.) Test pin (Connect to GND.) Clock 2 input pin (for scan converter) Test pin (Not connected.) System clear pin (Set to L: SVGA (VESA 72Hz)) Mode switching pin 3 output Mode switching pin 2 output Mode switching pin 1 output GND VDD Right/left inversion discrimination signal output (H output: Normal, L output: Reverse) Right/left inversion discrimination signal output (H output: Reverse, L output: Normal) HST pulse output HCK 1 pulse output HCK 2 pulse output BLK pulse output CLR pulse output ENB pulse output VCK pulse output -3- Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- -- -- -- -- -- -- -- -- -- -- -- --
CXD2464R
Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol VST TST14 PCG DWN HD CLP1 VSS2 CLP2/FLDO PRG FRP XFRP SHPA SHPB SHPC SHPD INV XVS XHS IRACT ORACT RSTR VSS3 VDD1 RCK RSTW WCK SCTR SCLK SDAT HDN CKI1
I/O O -- O O O O -- O O O O O O O O O O O O O O -- -- O O O I I I O I VST pulse output Test pin (Not connected.) PCG pulse output
Description
Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H: Pull up, L: Pull down
Up/down inversion discrimination signal output (H output: Down, L output: Up) HD pulse output Pedestal clamp pulse 1 output GND Pedestal clamp pulse 2 output/FLDO pulse output Precharge signal pulse output AC drive inversion timing output AC drive inversion timing output (reverse polarity of FRP) External sample-and-hold driver control signal (for CXA2112R) External sample-and-hold driver control signal (for CXA2112R) External sample-and-hold driver control signal (for CXA2112R) External sample-and-hold driver control signal (for CXA2112R) External sample-and-hold driver control signal (for CXA2112R) Auxiliary pulse output for CXD2449Q Auxiliary pulse output for CXD2449Q Auxiliary pulse output for scan converter Auxiliary pulse output for scan converter Reset read output (for high-speed line buffer) GND VDD Read clock output (for high-speed line buffer) Reset write output (for high-speed line buffer) Write clock output (for high-speed line buffer) Chip select input pin (serial transfer block) Serial clock input pin (serial transfer block) Serial data input pin (serial transfer block) Phase comparator pulse output Clock 1 input pin
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CXD2464R
Electrical Characteristics 1. DC characteristics Item Supply voltage Symbol VDD Conditions (VDD = 5.0 0.5V, VSS = 0V, Topr = -20 to +75C) Min. 4.5 VSS CMOS input 0.7VDD 0.3VDD 2.2 TTL Schmitt trigger input 0.4 IOH = -2mA IOL = 4mA IOH = -4mA IOL = 8mA 3 5 6 8 -10 -40 -40 -100 VDD - 0.8 0.4 10 -240 40 56 VDD - 0.8 0.4 V 0.8 V Typ. 5.0 Max. 5.5 VDD Unit V V V XCLR CKI1, CKI2 HSYNC VSYNC SCTR, SCLK SDAT 1 2 4 XCLR 7 At a 30pF load Applicable pins
Input, output voltages VI, Vo Input voltage 1 VIH VIL Vt+ Input voltage 2 Vt- Vt+ - Vt- Output voltage 1 VOH VOL Output voltage 2 VOH VOL Input leak current Output leak current Current consumption II IIL IOZ IDD
V
A A mA
1 INV, SHPA, SHPB, SHPC, SHPD, MODE1, MODE2, MODE3, HD, HDN, CLR, ENB, PRG, PCG, CLP1, CLP2/FLDO, VST, BLK, FRP, XFRP, VCK, DWN, RGT, XRGT, IRACT, ORACT, XHS, XVS 2 RSTR, RSTW, RCK, WCK, HCK1, HCK2, HST 3 Normal input pins (VIN = VSS or VDD) 4 HSYNC, VSYNC, SCLK, SDAT, SCTR, CKI1, CKI2 5 Pins with pull-up resistors (VIN = VSS) 6 At high impedance (VIN = VSS or VDD) 7 SHPA, SHPC 8 fclk = 62.5MHz, VDD = 5.0V
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CXD2464R
2. AC characteristics Item Symbol Applicable pins
(VDD = 5.0 0.5V, VSS = 0V, Topr = -20 to +75C) Min. 16.0 20.0 30.0 20 20 -10 10 15 15 48 48 52 52 CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF % ns Typ. Max. Conditions Unit
XGA, Mac16 Clock input cycle CKI1, 2 SVGA VGA Output rise time Output fall time Cross-point time difference Output rise delay time Output fall delay time HCK1 Duty HCK2 Duty
tr tf
t
All outputs All outputs HCK1, 2 All outputs All outputs HCK1 HCK2
tpr tpf tH/(tH + tL) tL/(tH + tL)
Note) The minimum value for the clock input cycle (CKI1) when using the built-in double-speed controller is 30.0ns. 3. Serial transfer AC characteristics Symbol Item SCTR setup time with respect to rise of SCLK SDAT setup time with respect to rise of SCLK SCTR hold time with respect to rise of SCLK SDAT hold time with respect to rise of SCLK SCLK L level pulse width SCLK H level pulse width (VDD = 5.0 0.5V, Vss = 0V, Topr =-20 to +75C) Min. 4Tns 2Tns 4Tns 2Tns 2Tns 2Tns 5Tns 5Tns T: Master clock cycle (ns) Note) Consider the frequency at free run (no signal). When the above characteristic specification is not satisfied at free run, operating guarantee is not performed as serial transfer. Typ. Max.
ts0 ts1 th0 th1 tw1L tw1H tw2 tw3
4. External clock input AC characteristics Symbol Item
(VDD = 5.0 0.5V, Vss = 0V, Topr = -20 to +75C) Min. 2ns 6ns 6ns 6ns T/2ns T/2ns Typ. Max.
ts0 th0 twL twH
HSYNC setup time with respect to rise of CKI1/2 HSYNC hold time with respect to rise of CKI1/2 CKI1/2 L level pulse width CKI1/2 H level pulse width
T: Master clock cycle (ns) Note) During external clock input, set serial data HR to L. The pulse synchronized with the horizontal sync signal is generated by detecting the front edge of horizontal sync signal and then resetting internal PLL counter. -6-
CXD2464R
5. Timing definitions AC characteristics
100% CKI1/2 0V tpr Output 10% 90% tr tf Output 90% tpf 10% VDD 0V VDD 0V VDD
VDD HCK1 50% 50% 0V VDD HCK2 50% 50% 0V t t
HCK1
50% tH
50% tL
50%
Note) HCK2 is the reverse phase of HCK1.
Serial transfer AC characteristics
ts0 SCTR 50% tw1L SCLK 50% ts1 SDAT 50% D15 th1
D14 D9
th0
tw3 50%
tw1H
tw2 50% ts1 D8 th1 D7 D0 D15
Note) See "Serial transfer timing" for the timing relationship between D15 to D0 and each pulse.
External clock input AC characteristics
th0 HSYNC (negative polarity) ts0 th0 ts0
50% twL twH 50% 50%
50%
CKI2
50%
50%
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CXD2464R
Pixel Arrangement The LCD panels supported by the CXD2464R are the LCX026, the LCX016 and the LCX012BL. The pixel arrangement is a square arrangement for both panels. The shaded region in the diagram is not displayed, however, for the LCX026 and the LCX016, since the CXD2464R has a built-in display area variable circuit, the display area dots varies according to the mode1 to match the various signal protocols. LCX026 pixel arrangement
Gate SW
Gate SW
Gate SW
Photo-shielding area
Display area
604 dots
6 dots 804 dots 816 dots 6 dots
1 dot
MODE1 MODE2 MODE3 L L L H L H H L -- L H L
Display mode SVGA PAL VGA/NTSC PC-98
Number of horizontal display dots 804 762 644 644
Number of vertical display dots 604 572 484 404
Number of display dots 485,616 435,864 311,696 260,176 Unit: dot
--: don't care 1 See the description of serial data specifications for details. -8-
1 dot
606 dots
CXD2464R
LCX016 pixel arrangement
Gate SW
Gate SW
Gate SW
Photo-shielding area
Display area
624 dots
4 dots 832 dots 840 dots 4 dots
1 dot
MODE1 MODE2 MODE3 L L L L H H L L H H L L L H L H L H
Display mode Macintosh16 SVGA PAL VGA/NTSC PC-98 WIDE
Number of horizontal display dots 832 800 762 640 640 832
Number of vertical display dots 624 600 572 480 400 480
Number of display dots 519,168 480,000 435,864 307,200 256,000 399,360 Unit: dot
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1 dot
626 dots
CXD2464R
LCX012BL pixel arrangement
Gate SW
Gate SW
Gate SW
Photo-shielding area
Display area
1 dot
5 dots 644 dots 654 dots 5 dots
Number of horizontal display dots 644
Number of vertical display dots 484
Number of display dots 311,696 Unit: dot
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1 dot
484 dots
486 dots
CXD2464R
Input Signal Protocol 1. Horizontal sync signal a) A standard signal (HSYNC) should be input for the following display modes. LCX026 : SVGA (800 x 600), VGA/NTSC (640 x 480), PC-98 (640 x 400), PAL (762 x 572) LCX016 : Macintosh16 (832 x 624), SVGA (800 x 600), VGA/NTSC (640 x 480), PC-98 (640 x 400), PAL (762 x 572), WIDE (832 x 480) LCX012BL : VGA/NTSC/PAL (640 x 480), PC-98 (640 x 400) However, since the CXD2464R requires a double speed signal as input during NTSC/PAL doublespeed display when not using the built-in double-speed controller, a simply double-speeded, 1/2 cycle, 1/2 width horizontal sync signal (HSYNC) should be input at that time. b) The input sync signal polarity is not fixed, and is set by the serial data (HPOL). 2. Vertical sync signal a) A sync-separated, normal-speed VSYNC should be input as the vertical sync signal. b) The input sync signal polarity is not fixed, and is set by the serial data (VPOL). c) The phase relationship between HSYNC and VSYNC is specified as follows for the CXD2464R.
(1) SVGA, VGA, PC-98 (LCX026)/Macintosh16, SVGA, VGA, PC-98 (LCX016)/VGA, PC-98 (LCX012BL)
HSYNC
VSYNC Sync signal phase reference
(2) Double-speed NTSC (LCX026/LCX016/LCX012BL)
Double-speed HSYNC
VSYNC Sync signal phase reference
(3) Double-speed PAL (LCX026/LCX016/LCX012BL)
Double-speed HSYNC VSYNC Sync signal phase reference
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CXD2464R
(4) NTSC (LCX026/LCX016/LCX012BL)
Sync signal phase reference VSYNC ODD FIELD HSYNC EVEN FIELD
(5) PAL (LCX026/LCX016/LCX012BL)
Sync signal phase reference VSYNC ODD FIELD HSYNC EVEN FIELD
Note) (2) and (3) show the timing when supporting input of double-speed signals (4) and (5) show the timing when using the built-in double-speed controller (CXD2464R) and a line memory (PD485505: NEC)
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CXD2464R
Description of Operation Sync signal input The HSYNC and VSYNC input pins support separate SYNC only. When using a composite SYNC input, use a separate IC for sync separation, etc. Clock input (1) CKI1 pin CKI1 is the clock input pin from an external PLL IC. A 1/N frequency divider output for PLL IC is output from the HDN pin. HDN polarity at this time is set by serial data HDNPOL. (2) CKI2 pin CKI2 is a clock input pin when using a scan converter that operates with synchronous input signals and asynchronous clock in the system. Since two types of clocks are input in this case, the circuit that basically operates with the respective clocks of CKI1 and CKI2 is asynchronous. For details, refer to the explanation of pulse setting for the scan converter in this specification (starting on page 37). AC driving of LCD panels for no signal The following measures have been adopted to allow AC driving of LCD panels even when there is no signal. Horizontal direction pulse The PLL is set to free running status. Therefore, the frequency of the horizontal direction pulse is dependent on the PLL free running frequency. Vertical direction pulse The number of lines is counted by an internal counter (AUX-VD COUNTER) and the vertical direction pulses (VST, FRP) are output at a specified cycle. For the CXD2464R, no signal (free running) status is judged if there is no VSYNC input for longer than the following periods (free running detection timing). Mode Double-speed NTSC Double-speed PAL Other V cycle for no signal Free running detection 263H 313H 650H 468H 900H
Note) The double-speed NTSC and PAL modes are the modes when using the built-in double-speed controller.
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CXD2464R
XCLR pin The CXD2464R should be forcibly reset during power on in order to initialize the serial transfer block and other internal circuits. Serial transfer operation 1. Control method The CXD2464R operation timing is controlled by serial data. The control data is comprised of an 8-bit address and 8-bit data, and the individual data is loaded at the rise of SCLK. This load operation starts from the fall of SCTR and is completed at the next rise of SCTR. Serial transfer timing
SCTR
SCLK
SDAT
D15
D14 D13 D12
D11 D10
D9
D8
D7
D6
D5
D4 Data
D3
D2
D1
D0
Address
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CXD2464R
2. Control data When using the CXD2464R, set the control data corresponding to each signal source according to the formats in the table below. Address D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D7 -- D6 -- D5 -- Data D4 -- D3 -- D2 D1 D0 Function
PLLP10 PLLP9 PLLP8 (A) PLL frequency division ratio (1/N) 1 PLLP7 PLLP6 PLLP5 PLLP4 PLLP3 PLLP2 PLLP1 PLLP0 0 1 0 1 0 1 0 1 0 1 0 HP7 VP7 -- -- -- -- -- -- -- -- -- HP6 VP6 -- -- -- -- -- -- -- -- -- HR -- IRD6 -- IRU6 HP5 VP5 -- -- -- -- -- HP4 VP4 -- HP3 VP3 HP2 VP2 HP1 VP1 HP0 VP0 (B) H-POSITION (C) V-POSITION
HSTP3 HSTP2 HSTP1 HSTP0 (D) HST-POSITION
PCGP4 PCGP3 PCGP2 PCGP1 PCGP0 (E) PCG-POSITION PRGP4 PRGP3 PRGP2 PRGP1 PRGP0 (E) PRG-POSITION -- INV -- -- CLPP1 CLPP0 (F) CLP-POSITION (G) S/H control for CXD2112R
SHP3 SHP2 SHP1 SHP0 FRP1 FRP0 CKTST1 RCK
CKTST0 FLD
VPOL HPOL HDNPOL CLPPOL PCGPOL PRGPOL -- MBKB MBKA MBK2 MBK1 MBK0 (H) Mode settings
MODE021 MODEB MODEA MODE3 MODE2 MODE1 DWN -- IRD5 -- IRU5 RGT SLLAP IRD4 -- IRU4 HST -- IRD3 -- IRU3 -- PCG DSP PC98 IRD8 IRD0 IRU8 IRU0 (I) IRACT rise position (I) IRACT fall position
1 VGAV 0 1 0 1 -- IRD7 -- IRU7
IRD10 IRD9 IRD2 IRD1
IRU10 IRU9 IRU2 IRU1
0 ORRS3 ORRS2 ORRS1 ORRS0
ORP10 ORP9 ORP8 (J) ORACT reset cycle ORACT frequency 1 ORP7 ORP6 ORP5 ORP4 ORP3 ORP2 ORP1 ORP0 0 ORD10 ORD9 ORD8 (K) ORACT fall position 1 ORD7 ORD6 ORD5 ORD4 ORD3 ORD2 ORD1 ORD0 0 ORU10 ORU9 ORU8 (K) ORACT rise position 1 ORU7 ORU6 ORU5 ORU4 ORU3 ORU2 ORU1 ORU0 0 HPRS10 HPRS9 HPRS8 (L) H position counter reset position 1 HPRS7 HPRS6 HPRS5 HPRS4 HPRS3 HPRS2 HPRS1 HPRS0 -- -- -- -- -- 0 -- -- -- -- -- -- -- PRE (M) Preset -- -- -- -- -- -- -- -- -- -- --
Settings other than those above are invalid
Note) PLLP0, HP0, VP0, HSTP0, PCGP0, PRGP0, CLPP0, SHP0, IRD0, IRU0, ORRS0, ORP0, ORD0, ORU0, HPRS0: LSB
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CXD2464R
Each control data is described in detail below. (A) to (M) (A) PLLP10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 These bits set the frequency division ratio (master clock) of the internal 1/N frequency divider for the PLL. The data is 11 bits and the frequency division ratio can be set up to 2048. The actual frequency division ratio should be set as follows. Number of clk for the horizontal period - 2 = Actual number of dots set Examples of settings for major modes are shown below. Examples using the LCX026 1) SVGA (800 x 600) PLLP setting value = 1040 (horizontal period) - 2 1038 (HLLLLLLHHHL: LSB) PLLP Setting data 10 H 9 L 8 L 7 L 6 L 5 L 4 L 3 H 2 H 1 H 0 L VESA SVGA72
2) VGA (640 x 480) PLLP setting value = 832 (horizontal period) - 2 830 (LHHLLHHHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 L 5 H 4 H 3 H 2 H 1 H 0 L VESA VGA72
3) PC-98 (640 x 400) PLLP setting value = 848 (horizontal period) - 2 846 (LHHLHLLHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 H 5 L 4 L 3 H 2 H 1 H 0 L
4) NTSC (640 x 480) PLLP setting value = 1560 (horizontal period) - 2 1558 (HHLLLLHLHHL: LSB) PLLP Setting data 10 H 9 H 8 L 7 L 6 L 5 L 4 H 3 L 2 H 1 H 0 L
5) PAL (762 x 572) PLLP setting value = 1880 (horizontal period) - 2 1878 (HHHLHLHLHHL: LSB) PLLP Setting data 10 H 9 H 8 H 7 L 6 H 5 L 4 H 3 L 2 H 1 H 0 L
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CXD2464R
Examples using the LCX016 1) Macintosh16 (832 x 624) PLLP setting value = 1152 (horizontal period) - 2 1150 (HLLLHHHHHHL: LSB) PLLP Setting data 10 H 9 L 8 L 7 L 6 H 5 H 4 H 3 H 2 H 1 H 0 L
2) SVGA (800 x 600) PLLP setting value = 1040 (horizontal period) - 2 1038 (HLLLLLLHHHL: LSB) PLLP Setting data 10 H 9 L 8 L 7 L 6 L 5 L 4 L 3 H 2 H 1 H 0 L VESA SVGA72
3) VGA (640 x 480) PLLP setting value = 832 (horizontal period) - 2 830 (LHHLLHHHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 L 5 H 4 H 3 H 2 H 1 H 0 L VESA VGA72
4) PC-98 (640 x 400) PLLP setting value = 848 (horizontal period) - 2 846 (LHHLHLLHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 H 5 L 4 L 3 H 2 H 1 H 0 L
5) NTSC WIDE (832 x 480) PLLP setting value = 1014 (horizontal period) - 2 1012 (LHHHHHHLHLL: LSB) PLLP Setting data 10 L 9 H 8 H 7 H 6 H 5 H 4 H 3 L 2 H 1 L 0 L
6) NTSC (640 x 480) PLLP setting value = 1560 (horizontal period) - 2 1558 (HHLLLLHLHHL: LSB) PLLP Setting data 10 H 9 H 8 L 7 L 6 L 5 L 4 H 3 L 2 H 1 H 0 L
7) PAL (762 x 572) PLLP setting value = 1880 (horizontal period) - 2 1878 (HHHLHLHLHHL: LSB) PLLP Setting data 10 H 9 H 8 H 7 L 6 H 5 L 4 H 3 L 2 H 1 H 0 L
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CXD2464R
Examples using the LCX012BL 1) VGA (640 x 480) PLLP setting value = 896 (horizontal period) - 2 894 (LHHLHHHHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 H 5 H 4 H 3 H 2 H 1 H 0 L VESA VGA72
2) PC-98 (640 x 400) PLLP setting value = 848 (horizontal period) - 2 846 (LHHLHLLHHHL: LSB) PLLP Setting data 10 L 9 H 8 H 7 L 6 H 5 L 4 L 3 H 2 H 1 H 0 L
3) NTSC, PAL (640 x 480) PLLP setting value = 1560 (horizontal period) - 2 1558 (HHLLLLHLHHL: LSB) PLLP Setting data 10 H 9 H 8 L 7 L 6 L 5 L 4 H 3 L 2 H 1 H 0 L
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CXD2464R
(B) HP7, 6, 5, 4, 3, 2, 1, 0 These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment of up to 256 clk with 8 bits is possible using the front edge of HSYNC as the reference.
Thp HSYNC
Image display period
Thp: Timing from the edge of HSYNC to the start of image display
Minimum and maximum Thp setting values for each mode LCX026 HP Min. Max. 7 6 5 4 3 2 1 0 800 x 600 762 x 572 640 x 480 640 x 400 HHHHHHHH LLLLLLLL 161 clk 416 clk 115 clk 370 clk
LCX016 HP Min. Max. 7 6 5 4 3 2 1 0 832 x 624 800 x 600 762 x 572 640 x 480 640 x 400 832 x 480 HHHHHHHH LLLLLLLL 185 clk 440 clk 155 clk 410 clk 109 clk 364 clk
LCX012BL HP Min. Max. 7 6 5 4 3 2 1 0 644 x 484 HHHHHHHH LLLLLLLL 112 clk 367 clk
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CXD2464R
(C) VP7, 6, 5, 4, 3, 2, 1, 0 These bits set the vertical display start position. The minimum adjustment width is 1H, and adjustment of up to 256H with 8 bits is possible using the following references. Progressive signal input Front edge of VSYNC Interlace signal input First 1H of VSYNC Here, the interlace signal input indicates NTSC or PAL display (using the built-in double-speed controller). In this case, the image is raised or lowered by two lines on the panel side with respect to a 1H adjustment. (1) Progressive
Tvp
Image display period
VSYNC HSYNC Tvp: Timing from the edge of VSYNC to the start of image display
Minimum and maximum Tvp setting values LCX026 VP Min. Max. 76543210 LLLLLLLL HHHHHHHH 9H 264H
LCX016/LCX012BL VP Min. Max. 76543210 LLLLLLLL HHHHHHHH 7H 262H
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CXD2464R
(2) Interlace (a) NTSC
Tvp Image display period
VSYNC HSYNC (ODD FIELD) HSYNC (EVEN FIELD) Tvp: Timing from the edge of VSYNC to the start of image display
Minimum and maximum Tvp setting values LCX026 VP Min. Max. 76543210 LLLLLLLL HHHHHHHH 5.5H 260.5H
LCX016/LCX012BL VP Min. Max. 76543210 LLLLLLLL HHHHHHHH 4.5H 259.5H
(b) PAL
Tvp Image display period
VSYNC HSYNC (ODD FIELD) HSYNC (EVEN FIELD) Tvp: Timing from the edge of VSYNC to the start of image display
Minimum and maximum Tvp setting values LCX026 VP Min. Max. 76543210 LLLLLLLL HHHHHHHH 5.5H 260.5H
LCX016/LCX012BL VP Min. Max. 76543210 LLLLLLLL HHHHHHHH 4.5H 259.5H - 21 -
CXD2464R
(D) HSTP3, 2, 1, 0 These bits control the HST phase relative to HCK, and correct the delay between HST and HCK that occurs within the panel. The phase of 12 position (in 1 clk increments) can be controlled with 4 bits.
HST HCK1
1 clk (1 x 1 clk) HSTP3, 2, 1, 0 : LLLL 0 : LLLH 1
HST HCK1 10 clk (10 x 1 clk) HSTP3, 2, 1, 0 : HLHL 10 11 clk (11 x 1 clk) : HLHH, HHXX > 10
Notes) 1. When setting to the LCX012BL mode, the phases of HST and HCK1, 2 are as shown above regardless of RGT. 2. In the LCX026 and LCX016 modes, when set to the SVGA mode and RGT: L or to a mode other than the SVGA mode and RGT: H, the phase relationship between HST and HCK1, 2 is as shown above. 3. The polarity of HCK1, 2 is reversed when set to panel mode switching, panel display area switching and right/left inversion modes other than as described in notes 1 and 2 above.
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CXD2464R
(E) PCGP4, 3, 2, 1, 0/PRGP4, 3, 2, 1, 0 These bits set the width of PCG and PRG pulses to 32 positions with 5 bits in 4 clk units. The rise positions of PCG and PRG pulses are determined by serial data HP (see (B)), modes 1, 2 and 3 (see (H-7)) and PCG (see (H-12)) position. The pulse widths of PCG and PRG can be arbitrarily set within the above range using the rise positions for the reference. When setting PCGP4, 3, 2, 1, 0 = n (decimal), the panel width at that time is calculated by: (n + 1) x 4 (clk) When setting PCGP4 to 0, the pulse fall position changes relative to the pulse rise position. This applies similarly to PRGP4 to 0. For example, when setting PCGP4, 3, 2, 1, 0: HLLHH = 19 (decimal), the panel width becomes: (19 + 1) x 4 = 80 clk Since the optimum values for pulse width of PCG and PRG pulses vary according to the LCD panel used, set while also referring to the panel specifications. Example) MCK: 50MHz (1 clk = 20ns)
PCGP4, 3, 2, 1, 0 : LHHHL (LSB) = 14 (decimal)
60 clk = 1.2s PCG
PRG 84 clk = 1.68s PRGP4, 3, 2, 1, 0 : HLHLL (LSB) = 20 (decimal)
Notes) PCGPOL and PRGPOL are both assumed to be "H". Polarity is reversed when PCGPOL and PRGPOL are each "L".
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CXD2464R
(F) CLPP1, 0 These bits adjust the clamp pulse output timing. The timing can be set to 4 positions with 2 bits.
The centers of the CLP1 and CLP2 pulses match.
Wclp1 CLP1 CLP2 Wclp2 HST
Tclp1
Tclp2
XGA (LCX026), Macintosh16 (LCX016) CLPP1 CLPP0 Tclp1 L L H H L H L H 46 clk Tclp2 23 clk Wclp1 Wclp2 69 clk 115 clk 69 clk 115 clk 69 clk 115 clk 69 clk 115 clk HHHHLLHH (243): LSB HHHHHHHH (255): LSB HP Limit (CLP1) HP Limit (CLP2) HHHHHHHH (255): LSB HHHHLLHH (243): LSB HHLHHHLL (220): LSB
69 clk 46 clk 92 clk 69 clk 115 clk 92 clk
SVGA (LCX026, LCX016) CLPP1 CLPP0 Tclp1 L L H H L H L H 38 clk Tclp2 19 clk Wclp1 Wclp2 58 clk 58 clk 58 clk 58 clk 96 clk 96 clk 96 clk 96 clk HHHHLHHL (246): LSB HHHHHHHH (255): LSB HP Limit (CLP1) HP Limit (CLP2) HHHHHHHH (255): LSB HHHHLHHL (246): LSB HHHLLLHH (227): LSB
57 clk 38 clk 76 clk 57 clk 95 clk 76 clk
VGA/NTSC, PAL, PC-98 (LCX026, LCX012BL), VGA/NTSC, PAL, PC-98, WIDE (LCX016) CLPP1 CLPP0 Tclp1 L L H H L H L H 26 clk Tclp2 13 clk Wclp1 Wclp2 38 clk 38 clk 38 clk 38 clk 64 clk 64 clk 64 clk 64 clk HHHHHLLL (248): LSB HHHHHHHH (255): LSB HP Limit (CLP1) HP Limit (CLP2) HHHHHHHH (255): LSB HHHHHLLL (248): LSB HHHLHLHH (235): LSB
39 clk 26 clk 52 clk 39 clk 65 clk 52 clk
Note) When CLPP1, 0 is set to HL or HH, the pulses may not be output due to the internal logic depending on the HP serial data setting value. HP Limit is the upper limit for the serial data HP that allows output of CLP1 and 2 pulses when setting each mode. HSTP is LLHH (LSB) (serial data).
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CXD2464R
(G) INV, SHP3, 2, 1, 0 This IC allows control of the sample-and-hold position of the CXA2112R sample-and-hold driver by setting serial data in place of not having a sample-and-hold pulse output. INV set by serial data is output from the INV pin (Pin 49). Connect this INV to INV_CNT (Pin 52) of the CXA2112R. In addition, data set with SHP3, 2, 1, 0 is reflected in the SHPA, SHPB, SHPC and SHPD output pins (pins 45, 46, 47 and 48) as shown in the table below. Setting SHP3, 2, 1, 0 LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH SHPA L H Z Z L L Z Z Output SHPB L H L H L H L H SHPC L L L L H H H H Setting SHPD SHP3, 2, 1, 0 L L L L H H H H HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH SHPA L H Z Z L L Z Z Output SHPB L H L H L H L H SHPC Z Z Z Z Z Z Z Z SHPD L L L L H H H H
Z: High Impedance State
The sample-and-hold position of the CXA2112R can be set by connecting SHPA to SHPD as shown in the diagram below. Refer to the specification of the CXA2112R for further details.
CXD2464R
CXA2112R
SHPA (Pin 45) 45 (SHPC (Pin 47)) (47)
46 SHPB (Pin 46) (SHPD (Pin 48)) (48)
1 (2)
POS_CNT1 (pin 1) (POS_CNT2 (pin 2))
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CXD2464R
(H) Mode settings Mode FLD FRP1 FRP0 CKTEST0, 1 RCK VPOL HPOL HDNPOL CLPPOL PCGPOL PRGPOL MBKB MBKA MBK2 MBK1 MBK0 MODE021 MODEB MODEA MODE3 MODE2 MODE1 VGAV HR DWN RGT HST PCG DSP PC98 Input signal attribute switching (H: Data, L: AV) External reset switching (H: No reset, L: Reset) Up/down inversion discrimination signal input (H: Down, L: Up) Right/left inversion discrimination signal input (H: Normal, L: Reverse) HST width switching (H: 12 dots wide, L: 24 dots wide) PCG width switching (H: Main, L: Sub) Double-speed mode switching (H: Normal, L: Double-speed) PC-98 (400 line) display switching (H: No display, L: Display) H-8 H-9 H-10 H-11 H-12 H-13 H-14 Panel display area switching Mode description FLD pulse output switching (H: FLD, L: CLP2) FRP polarity inversion cycle switching (H: 1F, L: 2F) FRP polarity inversion cycle switching (H: 1H, L: F) Test setting (Set to H.) Clock output setting (H: CLK STOP, L: CLK OUT) Input VSYNC polarity switching (H: Positive, L: Negative) Input HSYNC polarity switching (H: Positive, L: Negative) HDN pulse output polarity switching (H: Positive, L: Negative) CLP pulse output polarity switching (H: Positive, L: Negative) PCG pulse output polarity switching (H: Positive, L: Negative) PRG pulse output polarity switching (H: Positive, L: Negative) Skip scan interval switching Skip scan (FRP) timing switching (H: Main, L: Sub) Skip scan mode switching (H/H: No skip scan, H/L: 6, 4 skip scan, L/H: 5, 4 skip scan, L/L: 6, 7 skip scan) Test setting (Set to L.) Panel mode switching (H/H: LCX026 mode, L/H: LCX016 mode, L/L: LCX012BL mode) H-7 H-6 H-5 H-1 H-2 H-3 H-4
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CXD2464R
(H-1) FLD This bit switches the outputs of field identification pulse FLDO and clamp pulse CLP2. The FLDO pulse when FLD is H and the CLP2 pulse when FLD is L are output from Pin 41 (CLP2/FLDO). Refer to the timing chart for details. (H-2) FRP1, 0 These bits are the data for switching the LCD AC conversion signal cycle. FRP1, 0 should normally be set to HH.
1H
FRP1, 0: HH (1F/1H inversion) FRP1, 0: LH (2F/1H inversion) FRP1, 0: HL (1F inversion) FRP1, 0: LL (2F inversion)
1F
(H-3) CKTST0, 1 These bits set testing. CKTST0, 1 should normally be set to H. Note) If these bits are set to L, pulses may not be output normally. (H-4) RCK This bit sets testing. RCK should normally be set to H.
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CXD2464R
(H-5) VPOL, HPOL, HDNPOL, CLPPOL, PCGPOL, PRGPOL These bits are the data for switching input or output signal polarity. Set these bits according to the explanation below. (1) VPOL and HPOL are the data for switching the input vertical and horizontal sync signal polarity. Since signal processing is performed with the sync signal polarity fixed to positive by the internal logic, the data must be switched according to the polarity of the input sync signal. Therefore, individually set VPOL and HPOL to H when the polarity of the input sync signal is positive, and to L when the polarity is negative. The HDN pulse (H return pulse) is the 1/N frequency divider output pulse for the PLL IC. The width of the HDN pulse is calculated according to the setting of PLLP10 to 0 for the value of frequency division N, and that value is N/2. HDNPOL is the data for setting the output polarity of this HDN pulse, and the relationship between its setting and pulse polarity is shown in the diagram below.
N clk HSYNC HDNPOL: H HDN HDNPOL: L N/2 clk
(2)
HPOL: L
(3)
CLPPOL sets the output polarity of clamp pulses CLP1 and CLP2. When CLPPOL is H, both CLP1 and CLP2 have positive polarity, and when CLPPOL is L, both CLP1 and CLP2 have negative polarity. See the Timing Charts for details. PCGPOL and PRGPOL set the output polarity for the PCG and PRG pulses, respectively. When PCGPOL is H, the polarity of the PCG pulse is positive, and when PCGPOL is L, polarity is negative. This applies similarly to the relationship between PRGPOL and PRG pulses. See the Timing Charts for details.
(4)
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CXD2464R
(H-6) MBK2, 1, 0, B, A These bits set the skip-scan-related mode timings. These timings enable XGA (scanning line conversion from 768 to 598 vertical lines by 5, 4 skip scan) display for the LCX026, XGA (scanning line conversion from 768 to 615 vertical lines by 6, 4 skip scan) display for the LCX016, and SVGA (scanning line conversion from 600 to 480 vertical lines by 6, 4 skip scan) and double-speed PAL (scanning line conversion from 575 to 480 vertical lines by 6, 7 skip scan) display for the LCX012BL. However, for XGA and SVGA display, the horizontal direction is supported by external signal processing. Note) Supported input signals (XGA, SVGA) differ for each panel. Use the XGA skip scan display of the LCX026 in the XGA mode, the XGA skip scan display of the LCX016 in the Macintosh16 mode, and the SVGA skip scan display of the LCX012BL in the VGA or SVGA mode. At that time, the display area other than the image display area is written by the blanking level of the video signal according to the mode. Setting during LCX026 panel driving When the input signal is XGA (1024 x 768), set the operation of the CXD2464R to the XGA mode of the LCX026, and set the serial data HSTP to HSTP3/2/1/0: HLLH (LSB). See the Timing Charts for details.
9 clk HST
HCK1
HCK2 HSTP3, 2, 1, 0: HLLH (LSB)
(1) MBK2 This bit sets the FRP-related skip scan timing.
VST VCK FRP HST/PCG ENB MBK2: H (MAIN) MBK2: L (SUB)
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CXD2464R
(2) MBK1, 0 These bits set the skip scan mode. Select the XGA, SVGA or double-speed PAL skip scan mode. MBK1, 0 LL LH HL HH Skip scan mode 6, 7 skip scan 5, 4 skip scan 6, 4 skip scan No skip scan
Display start timing VST VCK FRP HST/PCG ENB MBK1, 0: LH (026 XGA5, 4 skip scan) 123 45
Display start timing VST VCK FRP HST/PCG ENB 123 4567
Display start timing
12345
67
MBK1, 0: HL (016 XGA, 012BL SVGA6, 4 skip scan)
ODD/EVEN FIELD MBK1, 0: LL (012BL double-speed, PAL6, 7 skip scan)
Note) MBK2: H and MBKB, A: LL.
- 30 -
CXD2464R
(3) MBK B, A These bits change skip scan timing for each field (interlace) or for each V cycle (progressive). These bits determine the skip scan timing for the next 1V period using the skip scan timing when the field identification pulse (FLDO) is L as the reference. The optimal skip scan position can be set by setting a skip scan interval of 0 to 3H. Although the charts below show 5, 4 skip scan timing, but the timing is the same for 6, 4 and 6, 7 skip scan.
Display start timing VST VCK Reference timing FRP HST/PCG ENB FLDO L 123 4567
Display start timing VST VCK FRP HST/PCG ENB FLDO H MBK B, A: LL Display start timing VST VCK FRP HST/PCG ENB FLDO H MBK B, A: HL 12 345 678 123 4567
Display start timing
1
234
5678
H MBK B, A: LH Display start timing
123
456
78
H MBK B, A: HH
Note) MBK2: H, MBK1, 0: LH - 31 -
CXD2464R
(H-7) MODE021 These bits are a test mode. MODE021 should normally be set to L. (1) MODE B, A These bits switch each timing according to the mode. Operation shifts to LCX026 mode when MBKB, A is HH, to LCX016 mode when LH, and to LCX012BL mode when LL. Be sure to set this data when using the CXD2464R in these modes. MODE B, A LL LH HH Panel LCX012BL LCX016 LCX026
(2) MODE3, 2, 1 These bits switch the panel display area. However, since the panel display area cannot be switched for the LCX012BL, VGA/NTSC mode should be set when using the LCX012BL. In addition, set to the XGA mode during XGA skip scan display using the LCX026, and to the Macintosh16 mode during XGA skip scan display using the LCX016. When using the LCX026 MODE XGA (804 x 604) SVGA (804 x 604) PAL (762 x 572) VGA/NTSC (644 x 484) PC-98 (644 x 404) 1 L L L L H 2 L L H H L 3 L H L H L
XGA skip scan display When using the LCX016 MODE Macintosh16 (832 x 624) SVGA (800 x 600) PAL (762 x 572) VGA/NTSC (640 x 480) PC-98 (640 x 400) WIDE (832 x 480) When using the LCX012BL MODE VGA/NTSC (644 x 484) 1 L 2 H 3 H - 32 - 1 L L L L H H 2 L L H H L L 3 L H L H L H
Also supports PAL display.
CXD2464R
(H-8) VGAV This bit switches the CXD2464R according to the attributes of the input signal. The CXD2464R supports input of data signals when VGAV is set to H, and input of interlaced video signals when set to L. Only the doublespeed NTSC, PAL and WIDE (LCX016 only) modes are supported, when using the built-in double-speed controller. Set VGAV to L during input of these signals. (H-9) HR This bit controls the input horizontal sync signal (HSYNC)-based PLL counter reset operation, and supports external clock input. (Reset operation is allowed when HR is L.) Resetting the internal PLL counter at the front edge of the input HSYNC generates an output pulse synchronized to HSYNC. This function should be used with systems which do not use a PLL. In addition, set the PLL frequency division ratio (1/N) resulting from the use of this mode according to: Number of clk for the horizontal period - 2 = Actual number of clk set (see page 16).
Input horizontal sync signal (HSYNC) Reset the internal PLL counter at this timing. HPOL: H
Note) Since H-POSITION specifications described in this data sheet are not satisfied due to the configuration of the internal logic, the screen center must be adjusted each time. (H-10) DWN, RGT These bits set the up/down and right/left inversion discrimination data. These settings allow display to be performed in accordance with each display system. See the Timing Charts for details. (H-11) HST This bit adjusts the HST width. HST should normally be set to H.
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CXD2464R
(H-12) PCG This bit adjusts the rise (fall) position (pulse starting timing) of the PCG pulse using VCK as a reference. This is linked with PRG and FRP. Timing at that time. PCG should normally be set to H.
VCK PRG PCG FRP Tm
Note) PCGPOL: H, PRGPOL: H
Tm value for each mode MODE XGA, Macintosh16 SVGA PAL VGA/NTSC PC-98 WIDE 32 clk 26 clk PCG = H Tm 57 clk 48 clk PCG = L Tm 46 clk 38 clk
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CXD2464R
(H-13) DSP This bit performs the double-speed display mode switching settings. Operation shifts to double-speed display mode when DSP is L. However, DSP should be set H for other modes. This function is only supported when the built-in double-speed controller is used. This controller is designed to use the PD485505 (NEC/high-speed line buffer) as the system line memory IC, and generates the doublespeed processing pulses RSTW (reset write), WCK (write clock), RSTR (reset read) and RCK (read clock). The operation of the PD485505 is as follows. Write operation is started at the RSTW timing, and this memory data is read at double speed at the RSTR timing which is delayed by 1/2H from the RSTW timing. Labeling the master clock frequency (MCK) as f, the write and read clock frequencies at this time are expressed as f/2 and f, respectively. However, the master clock should have a frequency of 33.3MHz or less when using this mode. See the IC specifications for a detailed description of PD485505 operation.
ADC R, G, B IN LINE Mem. PD485505 RSTW WCK HSYNC VSYNC CXD2464R MCK: f Double-speed display system diagram RSTR RCK
DAC
HSYNC RSTW WCK RSTR RCK f f/2
HSYNC
RSTW
RSTR Double-speed display timing
Note) See the Timing Charts for details. - 35 -
CXD2464R
(H-14) PC-98 This bit switches the PC-98 (400-vertical line) display mode. Operation shifts to PC-98 mode when PC98 is L. However, since this function supports the LCX012BL, PC98 is normally (modes other than LCX012BL/PC-98 mode) set H. This function is used to display PC-98 (640 x 400) images in the display area of the LCX012BL (644 x 484). The upper and lower 42 lines outside of the display area are black display during this mode. The vertical high-speed scanning and precharge black writing methods have been introduced as methods for writing these black areas. VCK is shifted to double-speed operation to realize vertical double-speed transfer and enable black display within the limited V blanking. Also, the black level during this period is determined by the PSIG (LCX012BL) level and written at the PCG (LCX012BL) timing. At this time, HST is masked, limiting the video signal input.
42 (A)
484
Effective display area (400 lines)
400 (B)
42 (C) 644 Unit: dot
LCX012BL panel
2-line inversion (FRP)
Effective display area (B)
VST VCK FRP HST PCG
(A)
(C)
: Black frame display areas
PC-98/400-line display timing Note) FRP is inverted every two lines during double-speed scanning. See the Timing Charts for details.
- 36 -
CXD2464R
(I) to (L) Scan converter pulse settings The following settings are not required when not using the scan converter or digital signal driver CXD2449Q. (I-1) SLLAP SLLAP is used when converting the number of pixels using the scan converter, when the clock differs between input signals and output signals, etc. SLLAP should be L during the normal operating mode. SLLAP should be H when operating with CKI1 synchronized only with input signals of the internal circuits of the IC, serial interface, PLL counter and phase comparator, and other components are operated with CKI2. (I-2) IRD10 to 0, IRU10 to 0 IRACT is an output pulse in sync with input HSYNC at an arbitrary position and width. Set the pulse fall position for IRD10 (MSB) to IRD0 (LSB), and the pulse rise position for IRU10 (MSB) to IRU0 (LSB). The setting range is from 0 to N - 1. In addition, do not set IRD and IRU to the same value.
HSYNC 128 clk IRACT
IRD: LLLLLLLLLLL (LSB), IRU: LLLHLLLLLLL (LSB), HR: H
(J-1) ORRS3, 2, 1, 0 When SLLAP is set L, ORACT pulse is completely identical to IRACT pulse when serial data SLLAP is L, and when SLLAP is set H, this is generated from a dedicated counter (loop counter similar to the PLL counter, and referred to as an OR counter) that operates by CKI2, an asynchronous clock that is independent from the input signal. In addition, pulses for LCD panel driving are also generated at this time based on the output of this counter, enabling the LCD panel to be driven with a horizontal cycle and clock that differ from the input signal. The above OR counter applies a reset with VSYNC and a fixed cycle input HSYNC in order to be in sync with input HSYNC. ORRS3, 2, 1, 0 perform this reset by HSYNC every H seconds or a cycle is set. When ORRS3, 2, 1, 0 (LSB) are set to LLLL, reset is applied for 16H cycles, and at the set number of cycles when set to other settings. Reset can be applied from 1H to a maximum of 16H cycles.
1H VSYNC
IRACT
ORACT
Timing by which reset is applied to OR counter SLLAP: H, ORRS: LHLL (LSB)
- 37 -
CXD2464R
(J-2) ORP10 to 0 ORP sets the number of frequency divisions of the OR counter described above. Similar to PLLP10 to 0, up to 2048 divisions can be set with 11 bits of data. Set the actual number of frequency divisions M as follows: M - 2 = actual number of clk set (K) ORD10 to 0, ORU10 to 0 ORACT pulses can be output at an arbitrary position and width of the OR counter operated by clock CKI2 that is asynchronous with input HSYNC when serial data SLLAP is set H. Set the pulse fall position for ORD10 (MSB) to ORD0 (LSB), and the pulse rise position for ORU10 (MSB) to ORU0 (LSB). The setting range is from 0 to M - 1. In addition, similar to IRACT, do not set ORD and ORU to the same value. As previously mentioned, when serial data SLLAP is L, ORACT pulses are identical to IRACT pulses regardless of the settings for serial data ORU and ORD. (L) HPRS10 to 0 Although the counter (H position counter) that generates horizontal display pulses is normally reset based on the PLL counter, when serial data SLLAP is H, reset can be applied to the horizontal direction display counter at an arbitrary position according to an 11-bit setting HPRS based on the OR counter. Consequently, the horizontal display starting position can be varied over a wide range. Setting of serial data HP7 to 0 becomes valid at this time.
HSYNC when reset is applied to OR counter 49 clk HSYNC 128 clk ORACT
ENB
ORD: LLLLLLLLLLL (LSB), ORU: LLLHLLLLLLL (LSB), HP: HHHHHHHH (LSB) HPRS: LLLLLHHLLLL (LSB), SLLAP: H
- 38 -
CXD2464R
(M) PRE This bit sets preset. Internal preset is reflected in the output when PRE is set L, and serial data settings are reflected in the output when PRE is set H. When the power is turned on, all internal systems are reset, and serial data PRE is set L. Namely, the CXD2464R is in the preset setting status. Always make sure to make all necessary settings before canceling this status (by setting PRE H). If serial data PRE is set H before making all required serial settings, all serial data that has not been set is set L. When serial settings have been changed when PRE is set H, those settings are immediately reflected in the output. After XCLR (system reset) Pin 19 is set L to reset the system, serial data PRE is set L and the CXD2464R enters preset setting status even after the power has been turned on. Make all required settings similar to when turning on the power after XCLR has been set H. The preset setting is VESA SVGA72 (horizontal frequency: 48.08kHz, vertical frequency: 72.19Hz, dot clock: 50.00MHz). Detailed setting values are as shown below. Address MSB LSB 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 Data PLLP10 to 8: HLL (LSB) PLLP7 to 0: LLLLHHHL (LSB) HP7 to 0: HHHLHLLH (LSB) VP7 to 0: LLLHLLHL (LSB) HSTP3 to 0: LLLH (LSB) PCGP4 to 0: LHHHL (LSB) PRGP4 to 0: HLHLL (LSB) CLPP1 to 0: LL (LSB) INV: L, SHP3 to 0: LLLL (LSB) FLD: L, FRP1 to 0: HH (LSB), CKTST: H, RCK: H VPOL: H, HPOL: H, HDNPOL: H, CLPPOL: H, PCGPOL: H, PRGPOL: H MBKB, A: LL, MBK2, 1, 0: HHH MODE021: L, MODEB, A: HH, MODE3, 2, 1: HLL VGAV: H, HR: L, DWN: H, RGT: H, HST: H, PCG: H, DSP: H, PC98: H SLLAP: L, IRD10 to 8: LLL (LSB) IRD7 to 0: LLLLLLLL (LSB) IRU10 to 8: LLL (LSB) IRU7 to 0: HLLLLLLL (LSB) ORRS3 to 0: LLLH (LSB), ORP10 to 8: LHH (LSB) ORP7 to 0: HHHLLHHL (LSB) ORD10 to 8: LLL (LSB) ORD7 to 0: LLLLLLLL (LSB) ORU10 to 8: LLL (LSB) ORU7 to 0: HLLLLLLL (LSB) HPRS10 to 8: LLL (LSB) HPRS7 to 0: LLLLLLLL (LSB) PRE: L - 39 -
CXD2464R
XHS and XVS Pulses Introduction XHS and XVS pulses are pulses for digital signal driver CXD2449Q sync signal input. XHS and XVS do not support systems using the built-in double-speed controller. Use the double-speed scan converter (CXD2428Q) with the CXD2449Q during NTSC or PAL double-speed display. XHS pulses XHS pulses are output with negative polarity in 32 clock widths 34 clocks after the fall of the IRACT pulse when serial data SLLAP is L. Similarly, XHS pulses are output with negative polarity in 32 clock widths 34 clocks after the fall of the ORACT pulse when serial data SLLAP is H. Therefore, in order to output XHS pulses correctly, respectively set serial data IRD10 to 0 and IRU10 to 0 when serial data SLLAP is L, and ORD10 to 0 and ORU10 to 0 when serial data SLLAP is H.
HSYNC 128 clk ORACT 32 clk XHS 34 clk ORD10 to 0: LLLLLLLLLLL, ORU10 to 0: LLLHLLLLLL
XVS pulses XVS pulses are output with negative polarity in 3H widths 2H after the vertical sync signal. The phase relationship between XHS and XVS pulses at this time is as shown in the diagram below.
VSYNC
HSYNC
XVS
XHS
Note) XHS and XVS pulses output ENB and BLK pulses (negative polarity), respectively, for the sake of convenience when using the built-in double-speed controller.
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LCX026 SVGA 800 x 600
MODE3/2/1 : H/L/L MODE B/A : H/H MODE021 : L DWN : H VP : LLLHLLHL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 588 (BLK) VST VCK FRP HST ENB
12
600
1
10
20
31
- 41 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX026 SVGA_1 800 x 600
RGT : H PLLP : HLLLLLLHHHL (LSB) HP : HHHLHLLL (LSB) HSTP : LLHH (LSB) PCGP : LHHHL (LSB) PRGP : HLHLL (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 910 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 19 clk 56 clk 120 clk 120 clk 920 930 940 950 960 970 980 990 1000 1010 1020 1030 0 10 20 30 40 50 Loop Counter : 1040 clk MCK f : 50.00MHz (20.00ns) 60 70 80 89
- 42 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk 32 clk
CXD2464R
LCX026 SVGA_2 800 x 600
RGT : H PLLP : HLLLLLLHHHL (LSB) HP : HHHLHLLL (LSB) HSTP : LLHH (LSB) PCGP : LHHHL (LSB) PRGP : HLHLL (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 90 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 58 clk 19 clk 19 clk 64 clk 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 Loop Counter : 1040 clk MCK f : 50.00MHz (20.00ns) 280 290 300 309
- 43 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 84 clk 60 clk 120 clk 48 clk
CXD2464R
LCX026 VGA 640 x 480
MODE3/2/1 : H/H/L MODE B/A : H/H MODE021 : L DWN : H VP : LLLHLHLL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 460 (BLK) VST VCK FRP HST ENB
12
470
480
1
10
20
30
40
49
- 44 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX026 VGA 640 x 480
RGT : H PLLP : LHHLLHHHHHL (LSB) HP : HHLLHLHL (LSB) HSTP : LLHH (LSB) PCGP : LHLLH (LSB) PRGP : LHHLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 792 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 13 clk 13 clk 13 clk 38 clk 24 clk 120 clk 40 clk 128 clk 802 812 822 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Loop Counter : 832 clk MCK f : 31.50MHz (31.75ns) 150 160 170 180
- 45 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 32 clk 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk 40 clk 56 clk 80 clk 32 clk
CXD2464R
LCX026 NTSC (ODD) 640 x 480
MODE3/2/1 : H/H/L MODE B/A : H/H MODE021 : L DWN : H VP : LLLLHHLL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 474 (BLK) VST VCK FRP HST ENB
12
480
485
1
10
20
23
- 46 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX026 NTSC (EVEN) 640 x 480
MODE3/2/1 : H/H/L MODE B/A : H/H MODE021 : L DWN : H VP : LLLLHHLL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 231 (BLK) VST VCK FRP HST ENB
12
240
243
244
250
260
266
- 47 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX026 NTSC_1 640 x 480
RGT : H PLLP : HHLLLLHLHHL (LSB) HP : HHHHHHLL (LSB) HSTP : LLHH (LSB) PCGP : LLHHL (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 1520 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 13 clk 13 clk 13 clk 38 clk 37 clk 120 clk 115 clk 115 clk 1530 1540 1550 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Loop Counter : 1560 clk MCK f : 24.54MHz (40.75ns) 150 160 170 179
- 48 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 80 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk 40 clk 28 clk 80 clk 32 clk
CXD2464R
LCX026 NTSC_2 640 x 480
RGT : H PLLP : HHLLLLHLHHL (LSB) HP : HHHHHHLL (LSB) HSTP : LLLH (LSB) PCGP : LLHHL (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 180 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 Loop Counter : 1560 clk MCK f : 24.54MHz (40.75ns) 370 380 780 789
- 49 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX026 PAL (ODD) 762 x 572
MODE3/2/1 : L/H/L MODE B/A : H/H MODE021 : L DWN : H VP : LLLHLLHL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 276 (BLK) VST VCK FRP HST ENB
12
280
288
289
300
306
- 50 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX026 PAL (EVEN) 762 x 572
MODE3/2/1 : L/H/L MODE B/A : H/H MODE021 : L DWN : H VP : LLLHLLHL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 564 (BLK) VST VCK FRP HST ENB
12
570
576
1
10
18
- 51 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX026 PAL_1 762 x 572
RGT : H PLLP : HHHLHLHLHHL (LSB) HP : HHLHLHLL (LSB) HSTP : LLHH (LSB) PCGP : LHLLL (LSB) PRGP : LHLHH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 1830 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 13 clk 13 clk 13 clk 38 clk 37 clk 120 clk 138 clk 170 clk 1840 1850 1860 1870 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Loop Counter : 1880 clk MCK f : 29.38MHz (34.04ns) 140 150 160 169
- 52 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 128 clk 128 clk 80 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 48 clk 36 clk 80 clk 32 clk
CXD2464R
LCX026 PAL_2 762 x 572
RGT : H PLLP : HHHLHLHLHHL (LSB) HP : HHLHLHLL (LSB) HSTP : LLLH (LSB) PCGP : LHLLL (LSB) PRGP : LHLHH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 170 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 Loop Counter : 1880 clk MCK f : 29.38MHz (34.04ns) 370 940 949
- 53 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX026 PC98 640 x 400
MODE3/2/1 : L/L/H MODE B/A : H/H MODE021 : L DWN : H VP : LLLHLHHL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 380 (BLK) VST VCK FRP HST ENB
12
390
400
1
10
20
30
40
47
- 54 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX026 PC98 640 x 400
RGT : H PLLP : LHHLHLLHHHL (LSB) HP : HHLHHHLH (LSB) HSTP : LLHH (LSB) PCGP : LLHLH (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 788 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 13 clk 13 clk 13 clk 38 clk 59 clk 120 clk 64 clk 85 clk 798 808 818 828 838 0 10 20 30 40 50 60 70 80 90 100 110 120 Loop Counter : 848 clk MCK f : 21.05MHz (47.50ns) 130 140 150 159
- 55 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 32 clk 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128fH 128fH 36 clk 24 clk 80 clk 32 clk
CXD2464R
LCX026 XGA 1024 x 768
MODE3/2/1 : L/L/L MODE B/A : H/H MODE021 : L DWN : H VP : LLLHLHHL (LSB) MBK2/1/0/B/A : H/L/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 742 (BLK) VST VCK FRP HST ENB
12
750
760
768
1
10
20
30
40
45
- 56 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS
CXD2464R
XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX026 XGA_1 1024 x 768
RGT : H PLLP : HLLLLLHHLLL (LSB) HP : HHLHHLHH (LSB) HSTP : HLLH (LSB) PCGP : LHHHH (LSB) PRGP : HLHLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 960 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 32 clk 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk 143 clk 23 clk 19 clk 120 clk 106 clk 970 980 990 1000 1010 1020 1030 1040 0 10 20 30 40 50 60 70 80 90 Loop Counter : 1050 clk MCK f : 52.81MHz (18.94ns) 100 110 120 129
- 57 -
CXD2464R
LCX026 XGA_2 1024 x 768
RGT : H PLLP : HLLLLLHHLLL (LSB) HP : HHLHHLHH (LSB) HSTP : HLLH (LSB) PCGP : LHHHH (LSB) PRGP : HLHLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 130 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 69 clk 23 clk 23 clk 125 clk 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 Loop Counter : 1050 clk MCK f : 52.81MHz (18.94ns) 320 330 340 349
- 58 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 88 clk 64 clk 143 clk 57 clk
CXD2464R
LCX016 Macintosh16_1 832 x 624
MODE3/2/1 : L/L/L MODE B/A : L/H MODE021 : L DWN : H VP : LLHLLLHH (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 596 (BLK) VST VCK FRP HST ENB
12
600
610
620
624
1
10
20
30
38
- 59 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 Macintosh16_1 832 x 624
RGT : H PLLP : HLLLHHHHHHL (LSB) HP : LHHLLHHH (LSB) HSTP : LLLH (LSB) PCGP : HLLLL (LSB) PRGP : HLHHH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 1022 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 32 clk 120 clk 64 clk 1032 1042 1052 1062 1072 1082 1092 1102 1112 1122 1132 1142 0 10 20 30 40 50 Loop Counter : 1152 clk MCK f : 57.28MHz (17.46ns) 60 70 80 89
- 60 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk 32 clk
CXD2464R
LCX016 Macintosh16_2 832 x 624
RGT : H PLLP : HLLLHHHHHHL (LSB) HP : LHHLLHHH (LSB) HSTP : LLLH (LSB) PCGP : HLLLL (LSB) PRGP : HLHHH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 90 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 23 clk 69 clk 23 clk 23 clk 224 clk 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 Loop Counter : 1152 clk MCK f : 57.28MHz (17.46ns) 280 290 300 309
- 61 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 68 clk 57 clk 96 clk 143 clk 57 clk
CXD2464R
LCX016 SVGA 800 x 600
MODE3/2/1 : H/L/L MODE B/A : L/H MODE021 : L DWN : H VP : LLHLLHHL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 588 (BLK) VST VCK FRP HST ENB
12
600
1
10
20
31
- 62 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 SVGA_1 800 x 600
RGT : H PLLP : HLLLHHHHHHL (LSB) HP : HHHLLLHL (LSB) HSTP : LLLH (LSB) PCGP : LHHHL (LSB) PRGP : HLHLL (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 910 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 19 clk 56 clk 120 clk 120 clk 920 930 940 950 960 970 980 990 1000 1010 1020 1030 0 10 20 30 40 50 Loop Counter : 1040 clk MCK f : 50.00MHz (20.00ns) 60 70 80 89
- 63 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk 32 clk
CXD2464R
LCX016 SVGA_2 800 x 600
RGT : H PLLP : HLLLHHHHHHL (LSB) HP : HHHLLLHL (LSB) HSTP : LLLH (LSB) PCGP : LHHHL (LSB) PRGP : HLHLL (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 90 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 58 clk 19 clk 19 clk 64 clk 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 Loop Counter : 1040 clk MCK f : 50.00MHz (20.00ns) 280 290 300 309
- 64 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 84fH 60fH 120 clk 48 clk
CXD2464R
LCX016 VGA 640 x 480
MODE3/2/1 : H/H/L MODE B/A : L/H MODE021 : L DWN : H VP : LLLHHLLL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 460 (BLK) VST VCK FRP HST ENB
12
470
480
1
10
20
30
40
49
- 65 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifith row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 VGA 640 x 480
RGT : H PLLP : LHHLLHHHHHL (LSB) HP : HHLLLHLL (LSB) HSTP : LLLH (LSB) PCGP : LHLLH (LSB) PRGP : LHHLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 792 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 13 clk 13 clk 13 clk 38 clk 24 clk 120 clk 40 clk 128 clk 802 812 822 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Loop Counter : 832 clk MCK f : 31.50MHz (31.75ns)
150
160
170
180
- 66 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 128 clk 128 clk 32 clk 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 40 clk 56 clk 80 clk 32 clk
CXD2464R
LCX016 NTSC (ODD) 640 x 480
MODE3/2/1 : H/H/L MODE B/A : L/H MODE021 : L DWN : H VP : LLLLHHHL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 474 (BLK) VST VCK FRP HST ENB
12
480
485
1
10
20
23
- 67 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 NTSC (EVEN) 640 x 480
MODE3/2/1 : H/H/L MODE B/A : L/H MODE021 : L DWN : H VP : LLLLHHHL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 231 (BLK) VST VCK FRP HST ENB
12
240
243
244
250
260
266
- 68 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 NTSC_1 640 x 480
RGT : H PLLP : HHLLLLHLHHL (LSB) HP : HHHHLHHL (LSB) HSTP : LLLH (LSB) PCGP : LLHHL (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 1520 MCK HSYNC (BLK) HD HDN CLP1 CLP2 13 clk HST HCK1 HCK2 13 clk 38 clk 37 clk 120 clk 115 clk 115fH 1530 1540 1550 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Loop Counter : 1560 clk MCK f : 24.54MHz (40.75ns) 150 160 170 179
13 clk
- 69 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 80 clk 128 clk 128 clk 40 clk 28 clk 80 clk 32 clk
CXD2464R
Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 NTSC_2 640 x 480
RGT : H PLLP : HHLLLLHLHHL (LSB) HP : HHHHLHHL (LSB) HSTP : LLLH (LSB) PCGP : LLHHL (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 180 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 Loop Counter : 1560 clk MCK f : 24.54MHz (40.75ns)
370
380
780
789
- 70 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT
CXD2464R
XHS Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 PAL (ODD) 762 x 572
MODE3/2/1 : L/H/L MODE B/A : L/H MODE021 : L DWN : H VP : LLLHLLHH (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 276 (BLK) VST VCK FRP HST ENB
12
280
288
289
300
306
- 71 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 PAL (EVEN) 762 x 572
MODE3/2/1 : L/H/L MODE B/A : L/H MODE021 : L DWN : H VP : LLLHLLHH (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 564 (BLK) VST VCK FRP HST ENB
12
570
576
1
10
18
- 72 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 PAL_1 762 x 572
RGT : H PLLP : HHHLHLHLHHL (LSB) HP : HHLLHHHH (LSB) HSTP : LLLH (LSB) PCGP : LHLLL (LSB) PRGP : LHLHH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 1830 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 13 clk 13 clk 38 clk 37 clk 120 clk 138 clk 170 clk 1840 1850 1860 1870 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Loop Counter : 1880 clk MCK f : 29.38MHz (34.04ns) 140 150 160 169
13 clk
- 73 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 128 clk 128 clk 80 clk 48 clk 36 clk 80 clk 32 clk
CXD2464R
Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX016 PAL_2 762 x 572
RGT : H PLLP : HHHLHLHLHHL (LSB) HP : HHLLHHHH (LSB) HSTP : LLLH (LSB) PCGP : LHLLL (LSB) PRGP : LHLHH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 170 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 Loop Counter : 1880 clk MCK f : 29.38MHz (34.04ns)
360
370
940
949
- 74 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 NTSC_WIDE 832 x 480
MODE3/2/1 : H/L/H MODE B/A : L/H MODE021 : L DWN : H VP : LLLHHLLL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 454 (BLK) VST VCK FRP HST ENB
12
460
470
480
1
10
20
30
49
- 75 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 NTSC_WIDE 832 x 480
RGT : H PLLP : LHHLLHHHHHL (LSB) HP : HHLLHHHL (LSB) HSTP : LLLH (LSB) PCGP : LHLLH (LSB) PRGP : LHHLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 974 MCK HSYNC (BLK) HD HDN CLP1 CLP2 13 clk HST HCK1 HCK2 13 clk 38 clk 24 clk 120 clk 79 clk 79 clk 984 994 1004 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Loop Counter : 1014 clk MCK f : 31.90MHz (31.35ns) 150 160 170 180
13 clk
- 76 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 128 clk 128 clk 32 clk 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 56 clk 40 clk 80 clk 32 clk
CXD2464R
LCX016 PC98 640 x 400
MODE3/2/1 : L/L/H MODE B/A : L/H MODE021 : L DWN : H VP : LLLHHLHL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 380 (BLK) VST VCK FRP HST ENB
12
390
400
1
10
20
30
40
47
- 77 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 PC98 640 x 400
RGT : H PLLP : LHHLHLLHHHL (LSB) HP : HHLHLHHH (LSB) HSTP : LLLH (LSB) PCGP : LLHLH (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H Loop Counter : 848 clk MCK f : 21.05MHz (47.50ns)
788 MCK HSYNC (BLK) HD HDN CLP1 CLP2
798
808
818
828
838
0
10
20
30 64 clk
40
50
60
70
80
90
100
110
120
130
140
150
159
59 clk 120 clk
85 clk
38 clk 13 clk 13 clk
13 clk
HST HCK1 HCK2
- 78 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 32 clk 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk 36 clk 24 clk 80 clk 32 clk
CXD2464R
LCX016 XGA 1024 x 768
MODE3/2/1 : L/L/L MODE B/A : L/H MODE021 : L DWN : H VP : LLLHLHHL (LSB) MBK2/1/0/B/A : H/H/L/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 752 (BLK) VST VCK FRP HST ENB
12
750
760
768
1
10
20
30
40
45
- 79 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX016 XGA_1 1024 x 768
RGT : H PLLP : HLLLHLLLLHL (LSB) HP : HHLLHLLL (LSB) HSTP : LLLH (LSB) PCGP : LHHHH (LSB) PRGP : HLHLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 1002 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 23 clk 20 clk 120 clk 110 clk 1012 1022 1032 1042 1052 1062 1072 1082 0 10 20 30 40 50 60 70 80 90 Loop Counter : 1092 clk MCK f : 52.81MHz (18.94ns) 100 110 120 129
- 80 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 32 clk 34 clk Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk
CXD2464R
LCX016 XGA_2 1024 x 768
RGT : H PLLP : HLLLHLLLLHL (LSB) HP : HHLLHLLL (LSB) HSTP : LLLH (LSB) PCGP : LHHHH (LSB) PRGP : HLHLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 130 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 69 clk 23 clk 23 clk 130 clk 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 Loop Counter : 1092 clk MCK f : 52.81MHz (18.94ns) 320 330 340 349
- 81 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS Note) When RGT is Low, HCK1 and 2 are inversed. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 88 clk 64 clk 143 clk 57 clk
CXD2464R
LCX012BL VGA 640 x 480
MODE3/2/1 : H/H/L MODE B/A : L/L MODE021 : L DWN : H VP : LLLHLHHL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 460 (BLK) VST VCK FRP HST ENB
12
470
480
1
10
20
30
40
49
- 82 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX012BL VGA 640 x 480
RGT : H PLLP : LHHLLHHHHHL (LSB) HP : HHLLLHHH (LSB) HSTP : LLLH (LSB) PCGP : LHLLH (LSB) PRGP : LHHLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H Loop Counter : 832 clk MCK f : 31.50MHz (31.75ns)
792 MCK HSYNC (BLK) HD HDN CLP1 CLP2
802
812
822
0
10
20 40 clk
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
24 clk 120 clk
128 clk
38 clk 13 clk 13 clk 13 clk
HST HCK1 HCK2
- 83 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 32 clk 34 clk 128 clk 128 clk
80 clk 80 clk 32 clk
56 clk 40 clk
CXD2464R
Note) When RGT is Low, HCK1 and 2 have the same polarity. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL NTSC (ODD) 640 x 480
MODE3/2/1 : H/H/L MODE B/A : L/L MODE021 : L DWN : H VP : LLLLHHLH (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 474 (BLK) VST VCK FRP HST ENB
12
480
485
1
10
20
23
- 84 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX012BL NTSC (EVEN) 640 x 480
MODE3/2/1 : H/H/L MODE B/A : L/L MODE021 : L DWN : H VP : LLLLHHLH (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 231 (BLK) VST VCK FRP HST ENB
12
240
243
244
250
260
266
- 85 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX012BL NTSC_1 640 x 480
RGT : H PLLP : HHLLLLHLHHL (LSB) HP : HHHHHLLH (LSB) HSTP : LLLH (LSB) PCGP : LLHHL (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 1520 MCK HSYNC (BLK) HD HDN CLP1 CLP2 13 clk HST HCK1 HCK2 CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 80 clk Note) When RGT is Low, HCK1 and 2 have the same polarity. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk 40 clk 28 clk 80 clk 32 clk 13 clk 38 clk 37 clk 120 clk 115 clk 115 clk 1530 1540 1550 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Loop Counter : 1560 clk MCK f : 24.54MHz (40.75ns) 150 160 170 179
13 clk
- 86 -
CXD2464R
LCX012BL NTSC_2 640 x 480
RGT : H PLLP : HHLLLLHLHHL (LSB) HP : HHHHHLLH (LSB) HSTP : LLLH (LSB) PCGP : LLHHL (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L Loop Counter : 1560 clk MCK f : 24.54MHz (40.75ns)
180 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT
190
202
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
780
789
- 87 -
CXD2464R
XHS Note) When RGT is Low, HCK1 and 2 have the same polarity. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL PAL (ODD) 640 x 480
MODE3/2/1 : H/H/L MODE B/A : L/L MODE021 : L DWN : H VP : LLLHLLHL (LSB) MBK2/1/0/B/A : H/L/L/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 276 (BLK) VST VCK FRP HST ENB
12
280
288
289
300
306
- 88 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX012BL PAL (EVEN) 640 x 480
MODE3/2/1 : H/H/L MODE B/A : L/L MODE021 : L DWN : H VP : LLLHLLHL (LSB) MBK2/1/0/B/A : H/L/L/L/L FRP1/0 : H/H VPOL : L VGAV : L PC98 : H VSYNC HSYNC HD HDN 564 (BLK) VST VCK FRP HST ENB
12
570
576
1
10
18
- 89 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP polarity is not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX012BL PAL_1 640 x 480
RGT : H PLLP : HHLLLLHLHHL (LSB) HP : HHHLHHHH (LSB) HSTP : LLLH (LSB) PCGP : LLHHL (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L 1830 MCK HSYNC (BLK) HD HDN CLP1 CLP2 13 clk HST HCK1 HCK2 CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 128 clk 128 clk 80 clk Note) When RGT is Low, HCK1 and 2 have the same polarity. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 40 clk 28 clk 80 clk 80 clk 32 clk 13 clk 38 clk 13 clk 37 clk 120 clk 115 clk 141 clk 1840 1850 1860 1870 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Loop Counter : 1560 clk MCK f : 24.38MHz (41.02ns) 140 150 160 169
- 90 -
CXD2464R
LCX012BL PAL_2 640 x 480
RGT : H PLLP : HHLLLLHLHHL (LSB) HP : HHHLHHHH (LSB) HSTP : LLLH (LSB) PCGP : LLHHL (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : L
Loop Counter : 1560 clk MCK f : 21.38MHz (41.02ns)
170 MCK HSYNC (BLK) HD HDN CLP1 CLP2 HST HCK1 HCK2 CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
940
949
- 91 -
CXD2464R
XHS Note) When RGT is Low, HCK1 and 2 have the same polarity. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL PC98 640 x 400
MODE3/2/1 : H/H/L MODE B/A : L/L MODE021 : L DWN : H VP : LLLLLHLL (LSB) MBK2/1/0/B/A : H/H/H/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : L VSYNC HSYNC HD HDN 380 (BLK) VST VCK FRP HST ENB
12
390
400
1
10
20
30
40
47
- 92 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
LCX012BL PC98 640 x 400
Loop Counter : 848 clk MCK f : 21.05MHz (47.50ns) 100 110 120 130 140 150 159
RGT : H PLLP : LHHLHLLHHHL (LSB) HP : HHLHHLHH (LSB) HSTP : LLLH (LSB) PCGP : LLHLH (LSB) PRGP : LHLLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 788 MCK HSYNC (BLK) HD HDN CLP1 CLP2 13 clk HST HCK1 HCK2 CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 32 clk 34 clk Note) When RGT is Low, HCK1 and 2 have the same polarity. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 128 clk 128 clk 36 clk 24 clk 80 clk 80 clk 32 clk 13 clk 38 clk 59 clk 120 clk 64 clk 85 clk 798 808 818 828 838 0 10 20 30 40 50 60 70 80 90
13 clk
- 93 -
CXD2464R
LCX012BL SVGA 640 x 480
MODE3/2/1 : H/H/L MODE B/A : L/L MODE021 : L DWN : H VP : LLLHLLHH (LSB) MBK2/1/0/B/A : H/H/L/L/L FRP1/0 : H/H VPOL : L VGAV : H PC98 : H VSYNC HSYNC HD HDN 588 (BLK) VST VCK FRP HST ENB
12
600
1
10
20
31
- 94 -
CLP1 CLP2 PCG PRG CLR FRP FLDO BLK IRACT ORACT XHS
CXD2464R
XVS Note) When DWN is Low, VST is inversed. The 1H and 1V cycle FRP and FLDO polarity are not specified. The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
LCX012BL SVGA 640 x 480
RGT : H PLLP : LHHLLHHHHHL (LSB) HP : HHLHHHLL (LSB) HSTP : LLLH (LSB) PCGP : LHLLH (LSB) PRGP : LHHLH (LSB) CLPP : LL (LSB) HPOL : L HDNPOL : H CLPPOL : H PCGPOL : H PRGPOL : H HR : H HST : H PCG : H DSP : H 782 MCK HSYNC (BLK) HD HDN CLP1 CLP2 13 clk HST HCK1 HCK2 13 clk 38 clk 13 clk 45 clk 120 clk 96 clk 51 clk 792 802 812 822 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Loop Counter : 832 clk MCK f : 40.00MHz (25.00ns) 140 150 160 179
- 95 -
CLR ENB VCK PRG PCG FRP BLK RSTR RCK RSTW WCK IRACT ORACT XHS 32 clk 34 clk
80 clk 80 clk 32 clk
56 clk 40 clk
128 clk 128 clk
CXD2464R
Note) When RGT is Low, HCK1 and 2 have the same polarity. The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins.
CXD2464R
Application Circuit
S/H driver IC CXA2112R (when CXA2111R is not used)
LCD signal processing IC CXD2112R
CXA2112R (when CXA2111R is not used)
100k
100k LCD panel
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
XFRP
SHPA
CLP1
SHPB
VSS2
CLP2/FLDO
TST14
SHPC
SHPD
PRG
DWN
PCG
FRP
49 INV 50 XVS 51 XHS
52 IRACT 53 ORACT 54 RSTR 55 VSS3 Line buffer PD485505 56 VDD1 57 RCK 58 RSTW 59 WCK 60 SCTR Serial I/F 61 SCLK 62 SDAT 63 HDN CXD2464R
MODE1 22 MODE2 21 MODE3 20 XCLR 19 TST13 18
HSYNC VSYNC
TST11 TST12
TST10
VCK
ENB 32 CLR 31 BLK 30 HCK2 29 HCK1 28 HST 27 XRGT 26 RGT 25 VDD0 24 VSS1 23
VST
HD
TST2
TST1
TST0
TST5
TST6
TST4
TST3
TST7
TST8
TST9
VSS0
64 CKI1
CKI2 17
10k 1 /16V
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
+5V Sync signal input PLL IC
0.1
47 /16V
Q
Q
CXD2112R PLL IC: Sony CXA3106Q (built-in phase comparator, frequency divider) is recommended.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 96 -
CXD2464R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 0.2 48 49 10.0 0.1 33 32
A 64 1 0.5 16 0.13 M + 0.2 1.5 - 0.1 17 (0.22) + 0.08 0.18 - 0.03
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g
- 97 -
0.5 0.2
(11.0)

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