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74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs
September 1991 Revised November 1999
74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs
General Description
The ABT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Current sinking capability is 64 mA on both the A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver. Transmit (active HIGH) enables data from A Ports to B Ports; Receive (active LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition.
Features
s Bidirectional non-inverting buffers s A and B output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching, noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch-free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Disable time is less than enable time to avoid bus contention
Ordering Code:
Order Number 74ABT245CSC 74ABT245CSJ 74ABT245CMSA 74ABT245CMTC 74ABT245CPC Package Number M20B M20D MSA20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names OE T/R A0-A7 B0-B7 Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS010945
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74ABT245
Logic Symbol
Truth Table
Inputs OE L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Output T/R L H X Bus B Data to Bus A Bus A Data to Bus B HIGH Z State
Logic Diagram
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74ABT245
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA) -500 mA 10V -0.5V to 5.5V -0.5V to VCC -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input 50 mV/ns 20 mV/ns -40C to +85C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current 2.5 2.0 0.55 1 1 IBVI IBVIT IIL Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current 7 100 -1 -1 VID IIH + IOZH IIL + I OZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Input Leakage Test 4.75 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A A V Min Min Min Min Max Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA (OE, T/R) IOH = -3 mA (An, Bn) IOH = -32 mA (An, Bn) IOL = 64 mA (A n, Bn) VIN = 2.7V (OE, T/R) VIN = VCC (OE, T/R) VIN = 7.0V (OE, T/R) VIN = 5.5V (An, Bn) VIN = 0.5V (OE, T/R) VIN = 0.0V (OE, T/R) IID = 1.9 A (OE, T/R) All Other Pins Grounded Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current -100 10 -10 -275 50 100 50 30 50 A A mA A A A mA A mA mA A mA/ MHz Max 0 - 5.5V VOUT = 2.7V (An, Bn); OE = 2.0V 0 - 5.5V VOUT = 0.5V (An, Bn); OE = 2.0V Max Max 0.0 Max Max Max VOUT = 0.0V (An, Bn) VOUT = V CC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW OE = V CC, T/R = GND or VCC; All Other GND or VCC Additional I CC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC No Load 2.5 2.5 50 0.1 VI = V CC - 2.1V OE, T/R V I = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND. Max Outputs Open OE = GND, T/R = GND or VCC One Bit Toggling, 50% Duty Cycle
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74ABT245
DC Electrical Characteristics
(SOIC package) Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage -1.3 2.7 2.0 Min Typ 0.7 -1.0 3.1 1.7 0.9 0.6 Max 1.0 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF, RL = 500 TA = 25C (Note 3) TA = 25C (Note 3) TA = 25C (Note 5) TA = 25C (Note 4) TA = 25C (Note 4)
Note 3: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 4: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ILD), 0V to threshold (VIHD ). Guaranteed, but not tested. Note 5: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package) TA = +25C Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Outputs Output Enable Time Output Disable Time 1.0 1.0 1.5 1.5 1.0 1.0 VCC = +5V CL = 50 pF Typ 2.1 2.4 3.2 3.7 3.6 3.3 Max 3.6 3.6 6.0 6.0 6.1 5.6 TA = -55C to +125C VCC = 4.5V-5.5V CL = 50 pF Min 1.0 1.0 1.0 2.0 1.7 1.7 Max 4.8 4.8 6.7 7.5 7.4 6.5 TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Min 1.0 1.0 1.5 1.5 1.0 1.0 Max 3.6 3.6 6.0 6.0 6.1 5.6 ns ns ns Units
Extended AC Electrical Characteristics
(SOIC package) -40C to +85C VCC = 4.5V-5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 6) Min fTOGGLE tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Max Toggle Frequency Propagation Delay Data to Outputs Output Enable Time 1.5 1.5 1.5 1.5 1.0 1.0 Typ 100 5.0 5.0 6.5 6.5 6.5 5.6 1.5 1.5 2.5 2.5 (Note 9) 6.0 6.0 7.5 7.5 2.5 2.5 2.5 2.5 (Note 9) 8.5 8.5 9.5 11.0 Max Min TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 1 Output Switching (Note 7) Max Min TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 8 Outputs Switching (Note 8) Max MHz ns ns ns Units
Note 6: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 7: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 8: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 9: The 3-STATE delays are dominated by the RC network (500, 250 pF) on the output and have been excluded from the datasheet.
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74ABT245
Skew
(SOIC package) TA = -40C to +85C VCC = 4.5V-5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 12) Max tOSHL (Note 10) tOSLH (Note 10) tPS (Note 14) tOST (Note 10) tPV (Note 11) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH-HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 1.3 1.0 2.0 2.0 2.0 TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 8 Outputs Switching (Note 13) Max 2.3 1.8 3.5 3.5 3.5 ns ns ns ns ns Units
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (t OSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST). The specification is guaranteed but not tested. Note 11: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 13: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Conditions Symbol CIN CI/O (Note 15) Parameter Input Capacitance I/O Capacitance Typ 5.0 11.0 Units pF pF TA = 25C V CC = 0V (OE, T/R) V CC = 5.0V (An, Bn)
Note 15: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74ABT245
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
Amplitude 3.0V
Rep. Rate 1 MHz
tW 500 ns
tr 2.5 ns
tf 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M20B
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74ABT245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74ABT245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20
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74ABT245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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