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| DATA SHEET MOS INTEGRATED CIRCUIT m PD784020, 784021 16/8-BIT SINGLE-CHIP MICROCOMPUTER The mPD784021 is a product of the mPD784026 sub-series in the 78K/IV series. It contains various peripheral hardware such as RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance CPU. The mPD784021 is a ROM-less product of the mPD784025 or mPD784026. The mPD784020 differs from the mPD784021 only in its RAM size: 512 bytes are allocated for the mPD784020, while 2048 bytes are allocated for the mPD784021. For specific functions and other detailed information, consult the following user's manual. This manual is required reading for design work. mPD784026 Sub-Series User's Manual, Hardware : U10898E 78K/IV Series User's Manual, Instruction : U10905E FEATURES * 78K/IV series * Pin-compatible with the mPD78234 sub-series * Minimum instruction execution time: 160 ns (at 25 MHz) * PWM outputs: 2 * Standby function HALT/STOP/IDLE mode * Number of I/O ports: 46 * Timer/counters: 16-bit timer/counter 3 units 16-bit timer 1 unit * Serial interface: 3 channels UART/IOE (3-wire serial I/O) :2 channels CSI (3-wire serial I/O, SBI) : 1 channel * * * * * Clock frequency division function Watchdog timer : 1 channel A/D converter D/A converter : 8-bit resolution 8 channels : 8-bit resolution 2 channels Supply voltage : VDD = 2.7 to 5.5 V APPLICATIONS LBP, automatic-focusing camera, PPC, printer, electronic typewriter, air conditioner, electronic musical instruments, cellular telephone, etc. This manual describes the mPD784021 unless otherwise specified. The information in this document is subject to change without notice. Document No. U11514EJ1V0DS00 (1st edition) (Previous No. IP-3234) Date Published July 1996 P Printed in Japan The mark H shows major revised points. (c) 1990 1996 m PD784020, 784021 ORDERING INFORMATION Part number H H H Package 80-pin plastic QFP (14 14 mm) 80-pin plastic QFP (14 14 mm) 80-pin plastic TQFP (fine pitch) (12 12 mm) Internal ROM (bytes) None None None Internal RAM (bytes) 512 2048 2048 mPD784020GC-3B9 mPD784021GC-3B9 mPD784021GK-BE9 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM : Product under mass production : Product under development : Product under planning Standard Products Development PD784038Y sub-series Product containing for an I2C bus interface circuit PD784038 sub-series 80-pin, 8-bit A/D, 8-bit D/A ROM: 48K/64K/96K/128K PD784026 sub-series 80-pin, 8-bit A/D, 8-bit D/A ROM: none/48K/64K PD784216Y sub-series Product containing for two I2C bus interface circuits PD784216 sub-series 100-pin, 8-bit A/D, 8-bit D/A ROM: 96K/128K PD784054 80-pin, 10-bit A/D ROM: 32K PD784046 sub-series sub-set PD784046 sub-series 80-pin, 10-bit A/D ROM: 32K/64K ASSP Development PD784915 sub-series VTR servo, 100-pin, built-in analog amplifier ROM: 48K/62K PD784908 sub-series 100-pin, built-in IEBusTM ROM: 96K/128K PD784943 sub-series 80-pin, for CD-ROM ROM: 56K 2 m PD784020, 784021 FUNCTIONS Product Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space I/O ports Total Input Input/output Output Additional function pinsNote ROM RAM 113 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) 160 ns/320 ns/640 ns/1280 ns (at 25 MHz) None 512 bytes Program and data: 1M byte 46 8 34 4 2048 bytes mPD784020 mPD784021 Pins with pull- 32 up resistor LED direct drive outputs Transistor direct drive 8 8 4 bits 2, or 8 bits 1 Timer/counter 0: (16 bits) Timer register 1 Capture register 1 Compare register 2 Timer register 1 Capture register 1 Capture/compare register 1 Compare register 1 Timer register 1 Capture register 1 Capture/compare register 1 Compare register 1 Timer register 1 Compare register 1 Pulse output capability Y Toggle output Y PWM/PPG output Y One-shot pulse output Pulse output capability Y Real-time output (4 bits 2) Real-time output ports Timer/counter Timer/counter 1: (8/16 bits) Timer/counter 2: (8/16 bits) Pulse output capability Y Toggle output Y PWM/PPG output Timer 3 (8/16 bits) PWM outputs Serial interface A/D converter D/A converter Watchdog timer Standby Interrupt Source Software Nonmaskable Maskable : 12-bit resolution 2 channels UART/IOE (3-wire serial I/O) : 2 channels (incorporating baud rate generator) CSI (3-wire serial I/O, SBI) : 1 channel 8-bit resolution 8 channels 8-bit resolution 2 channels 1 channel HALT/STOP/IDLE mode 23 (16 internal, 7 external (sampling clock variable input: 1)) + BRK instruction BRK instruction 1 internal, 1 external 15 internal, 6 external Y 4-level programmable priority Y 3 operation statuses: vectored interrupt, macro service, context switching Supply voltage Package VDD = 2.7 to 5.5 V 80-pin plastic QFP (14 14 mm) 80-pin plastic TQFP (fine pitch) (12 12 mm): for the mPD784021 only H H Note Additional function pins are included in the I/O pins. 3 m PD784020, 784021 CONTENTS 1. 2. 3. 4. 5. 6. DIFFERENCES BETWEEN mPD784026 SUB-SERIES ........................................................... MAIN DIFFERENCES BETWEEN mPD784026 AND mPD78234 SUB-SERIES ..................... PIN CONFIGURATION (TOP VIEW) ........................................................................................ SYSTEM CONFIGURATION EXAMPLE (PPC) ....................................................................... BLOCK DIAGRAM ..................................................................................................................... LIST OF PIN FUNCTIONS ........................................................................................................ 6.1 6.2 6.3 PORT PINS ...................................................................................................................................... NON-PORT PINS ............................................................................................................................ I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS ................................................. 6 7 8 10 11 12 12 13 15 7. CPU ARCHITECTURE .............................................................................................................. 7.1 7.2 MEMORY SPACE ........................................................................................................................... CPU REGISTERS ............................................................................................................................ 7.2.1 7.2.2 7.2.3 General-Purpose Registers .......................................................................................... Control Registers ........................................................................................................... Special Function Registers (SFRs) ............................................................................. 18 18 21 21 22 23 8. PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 PORTS ............................................................................................................................................. CLOCK GENERATOR .................................................................................................................... REAL-TIME OUTPUT PORT .......................................................................................................... TIMERS/COUNTERS ...................................................................................................................... PWM OUTPUT (PWM0, PWM1) ..................................................................................................... A/D CONVERTER ........................................................................................................................... D/A CONVERTER ........................................................................................................................... SERIAL INTERFACE ...................................................................................................................... 8.8.1 8.8.2 8.9 8.10 Asynchronous Serial Interface/Three-Wire Serial I/O (UART/IOE) ......................... Synchronous Serial Interface (CSI) ............................................................................. 28 28 29 31 32 34 35 36 37 38 40 41 42 EDGE DETECTION FUNCTION ..................................................................................................... WATCHDOG TIMER ....................................................................................................................... 9. INTERRUPT FUNCTION ........................................................................................................... 9.1 9.2 9.3 9.4 9.5 INTERRUPT SOURCE .................................................................................................................... VECTORED INTERRUPT ............................................................................................................... CONTEXT SWITCHING .................................................................................................................. MACRO SERVICE ........................................................................................................................... EXAMPLES OF MACRO SERVICE APPLICATIONS .................................................................. 43 43 45 46 46 47 4 m PD784020, 784021 10. LOCAL BUS INTERFACE ......................................................................................................... 10.1 10.2 10.3 10.4 10.5 MEMORY EXPANSION .................................................................................................................. MEMORY SPACE ........................................................................................................................... PROGRAMMABLE WAIT ............................................................................................................... PSEUDO-STATIC RAM REFRESH FUNCTION ........................................................................... BUS HOLD FUNCTION .................................................................................................................. 49 49 50 51 51 51 11. STANDBY FUNCTION .............................................................................................................. 12. RESET FUNCTION .................................................................................................................... 13. INSTRUCTION SET ................................................................................................................... 14. ELECTRICAL CHARACTERISTICS ......................................................................................... 15. PACKAGE DRAWINGS ............................................................................................................ 16. RECOMMENDED SOLDERING CONDITIONS ........................................................................ APPENDIX A APPENDIX B DEVELOPMENT TOOLS ........................................................................................ RELATED DOCUMENTS ....................................................................................... 52 53 54 59 80 82 83 85 H H 5 m PD784020, 784021 H 1. DIFFERENCES BETWEEN m PD784026 SUB-SERIES The only difference between the mPD784020, mPD784021, mPD784025, and mPD784026 is their capacity of internal memory, port functions, and part of their packages. The mPD78P4026 is produced by replacing the masked ROM in the mPD784025 or mPD784026 with 64K-byte onetime PROM or EPROM. Table 1-1 shows the differences between these products. Table 1-1 Differences between the mPD784026 Sub-Series Product Item Internal ROM mPD784020 None mPD784021 mPD784025 48K bytes (masked ROM) mPD784026 64K bytes (masked ROM) mPD78P4026 64K bytes (one-time PROM or EPROM) Internal RAM P40-P47 512 bytes 2048 bytes Can be switched to a general-purpose port or address/data bus, by using software Can be switched to a general-purpose port or address bus in units of 2 bits, by using software Functions only as an address/data bus P50-P57 P60-P63 Functions only as an address bus Can be switched to an output-only port or address bus in units of 2 bits, by using software Functions only as the RD or WR pin 80-pin plastic QFP (14 14 mm) 80-pin plastic QFP (14 14 mm) 80-pin plastic TQFP (fine pitch) (12 12 mm) P64, P65 Functions as the RD or WR pin when the local bus interface is used. Functions as a general-purpose port in other cases. 80-pin plastic QFP (14 14 mm) 80-pin plastic QFP (14 14 mm) 80-pin ceramic WQFN (14 14 mm) Package 6 m PD784020, 784021 2. MAIN DIFFERENCES BETWEEN m PD784026 AND mPD78234 SUB-SERIES Series Item Number of basic instructions (mnemonics) Minimum instruction execution time Memory space (program/data) Timer/counter 113 mPD784026 sub-series 65 mPD78234 sub-series 160 ns (at 25 MHz) 1M byte in total 16-bit timer/counter 1 8/16-bit timer/counter 2 8/16-bit timer 1 Available Available UART/IOE (3-wire serial I/O) 2 channels CSI (3-wire serial I/O, SBI) 1 channel Available 4 levels 3 modes (HALT, STOP, IDLE) Selectable from fXX/2, fXX/4, fXX/8, or fXX/16 Unavailable 333 ns (at 12 MHz) 64K bytes/1M byte 16-bit timer/counter 1 8-bit timer/counter 2 8-bit timer 1 Unavailable Unavailable UART 1 channel CSI (3-wire serial I/O, SBI) 1 channel Unavailable 2 levels 2 modes (HALT, STOP) Fixed to fXX/2 To specify ROM-less mode (always in the high level for the mPD78233 or mPD78237) Unavailable Clock output function Watchdog timer Serial interface Interrupt Context switching Priority Standby function Operation clock switching Pin functions MODE pin TEST pin Pin for testing the device Low level during ordinary use 80-pin plastic QFP (14 14 mm) 80-pin plastic TQFP (fine pitch) (12 12 mm): for the mPD784021 only 80-pin ceramic WQFN (14 14 mm): for the mPD78P4026 only Package 80-pin plastic QFP (14 14 mm) 94-pin plastic QFP (20 20 mm) 84-pin plastic QFJ (1150 1150 mil) 94-pin ceramic WQFN (20 20 mm): for the mPD78P238 only 7 m PD784020, 784021 3. PIN CONFIGURATION (TOP VIEW) * 80-pin plastic QFP (14 14 mm) H H mPD784020GC-3B9, mPD784021GC-3B9 * 80-pin plastic TQFP (fine pitch) (12 12 mm) mPD784021GK-BE9 P25/INTP4/ASCK/SCK1 P31/TxD/SO1 P23/INTP2/CI P30/RxD/SI1 P22/INTP1 P24/INTP3 P26/INTP5 P21/INTP0 P77/ANI7 P76/ANI6 AVREF2 ANO1 ANO0 P32/SCK0 P33/SO0/SB0 P34/ TO0 P35/ TO1 P36/ TO2 P37/ TO3 RESET VDD X2 X1 VSS P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AVDD AVSS P75/ANI5 P20/NMI P27/SI0 AVREF3 AVREF1 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD P17 P16 P15 P14/TXD2/SO2 P13/RXD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 TESTNote VSS ASTB AD0 AD1 AD2 P66/WAIT/HLDRQ WR RD P63/A19 P62/A18 P61/A17 P60/A16 A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 Note Connect the TEST pin to VSS directly. 8 AD3 m PD784020, 784021 P00-P07 P10-P17 P20-P27 P30-P37 P70-P77 TO0-TO3 CI RxD, RxD2 TxD, TxD2 SCK0-SCK2 ASCK, ASCK2 SI0-SI2 SO0-SO2 SB0 PWM0, PWM1 NMI INTP0-INTP5 AD0-AD7 : Port 0 : Port 1 : Port 2 : Port 3 : Port 7 : Timer output : Clock input : Receive data : Transmit data : Serial clock : Asynchronous serial clock : Serial input : Serial output : Serial bus : Pulse width modulation output : Non-maskable interrupt : Interrupt from peripherals : Address/data bus A8-A19 RD WR WAIT HLDRQ HLDAK ASTB REFRQ RESET X1, X2 ANI0-ANI7 : Address bus : Read strobe : Write strobe : Wait : Hold request : Hold acknowledge : Address strobe : Refresh request : Reset : Crystal : Analog input P60-P63, P66, P67 : Port 6 ANO0, ANO1 : Analog output AVREF1-AVREF3 : Reference voltage AVDD AVSS VDD VSS TEST : Analog power supply : Analog ground : Power supply : Ground : Test 9 m PD784020, 784021 4. SYSTEM CONFIGURATION EXAMPLE (PPC) PD784021 Serial communication RxD TxD P11 P15 P16 P17 SCK1 SI1 SO1 Sensing paper Sensing paper feed Sensing paper ejection Sensing the position of the scanner station Operator panel PD27C1001A OE CE A8-A16 O0-O7 A0-A7 RD A17 A8-A16 PD74HC573 P04 P06 AD0-AD7 P07 ASTB High-voltage control circuit Drum, toner, and charge for transfer Latch Fusing heater control circuit Fusing roller Sensing paper transport Temperature of the fusing heater INTP0 ANI0 P66 Lamp regulator Lamp for lighting the original Lamp for discharging PWM0 Brightness of the lamp ANI1 P00-P03 (DC stepping motor) M Main motor SL Lever for adjusting the tone of the copy P33 ANI2 SL P34 Driver SL Lever for compensating the tone of the copy ANI3 P35 SL P36 Reset circuit SL RESET P37 Solenoid Clutch for stopping the scanner station Clutch for forwarding the scanner station Clutch for the resist shutter Clutch for manual feeding Clutch for cassette feeding 10 m PD784020, 784021 5. BLOCK DIAGRAM RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 NMI INTP0-INTP5 Programmable interrupt controller UART/IOE2 Baud-rate generator UART/IOE1 Baud-rate generator INTP3 TO0 TO1 Timer/counter 0 (16 bits) INTP0 Timer/counter 1 (16 bits) SCK0 Clocked serial interface 78K /IV CPU core SO0/SB0 SI0 INTP1 INTP2/CI TO2 TO3 Timer/counter 2 (16 bits) ASTB AD0-AD7 A8-A15 Bus interface A16-A19 RD WR WAIT/HLDRQ REFRQ/HLDAK P00-P07 P10-P17 P20-P27 P30-P37 P60-P63 Port 6 P60, P67 P70-P77 RESET TEST X1 X2 VDD VSS Timer 3 (16 bits) P00-P03 Real-time output port P04-P07 PWM0 PWM PWM1 ANO0 ANO1 AVREF2 AVREF3 RAM Port 1 Port 2 Port 3 D /A converter Port 0 ANI0-ANI7 AVDD AVREF1 AVSS INTP5 Watchdog timer A /D converter Port 7 System control Remark The internal ROM or RAM capacity differs for each product. 11 m PD784020, 784021 6. LIST OF PIN FUNCTIONS 6.1 PORT PINS Pin P00-P07 I/O I/O Dual-function -- Port 0 (P0): Y 8-bit I/O port Y Functions as a real-time output port (4 bits 2). Y Inputs and outputs can be specified bit by bit. Y The use of the pull-up resistors can be specified by software for the pins in the input mode together. Y Can drive a transistor. P10 P11 P12 P13 P14 P15-P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34-P37 P60-P63 P66 P67 I/O I/O Input NMI INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 SI0 RxD/SI1 TxD/SO1 SCK0 SO0/SB0 TO0-TO3 A16-A19 WAIT/HLDRQ Y Inputs and outputs can be specified bit by bit for pins P66 and P67. REFRQ/HLDAK Y The use of the pull-up resistors can be specified by software for the pins in the input mode together. Port 7 (P7): Y 8-bit I/O port Y Inputs and outputs can be specified bit by bit. Y The use of the pull-up resistors can be specified by software for pins P22 to P27 (in units of 6 bits). Y The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by CSIM1. Port 3 (P3): Y 8-bit I/O port Y Inputs and outputs can be specified bit by bit. Y The use of the pull-up resistors can be specified by software for the pins in the input mode together. Port 6 (P6): Y P60 to P63 are an output-only port. I/O PWM0 PWM1 ASCK2/SCK2 RxD2/SI2 TxD2/SO2 -- Port 1 (P1): Y 8-bit I/O port Y Inputs and outputs can be specified bit by bit. Y The use of the pull-up resistors can be specified by software for the pins in the input mode together. Y Can drive LED. Port 2 (P2): Y 8-bit input-only port Y P20 does not function as a general-purpose port (nonmaskable interrupt). However, the input level can be checked by an interrupt service routine. Function P70-P77 I/O ANI0-ANI7 12 m PD784020, 784021 6.2 NON-PORT PINS (1/2) Pin TO0-TO3 CI RXD RXD2 TXD TXD2 ASCK ASCK2 SB0 SI0 SI1 SI2 SO0 SO1 SO2 SCK0 SCK1 SCK2 NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 AD0-AD7 A8-A15 A16-A19 RD WR WAIT REFRQ HLDRQ HLDAK ASTB I/O Output Output Output Output Input Output Input Output Output P60-P63 -- -- P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ -- Input I/O Output I/O Input Input Output I/O Output Input Input Dual-function P34-P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P33/SO0 P27 P30/RXD P13/RXD2 P33/SB0 P31/TXD P14/TXD2 P32 P25/INTP4/ASCK P12/ASCK2 P20 P21 P22 P23/CI P24 P25/ASCK/SCK1 P26 -- -- Timer output Input of a count clock for timer/counter 2 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data I/O (SBI) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock I/O (3-wire serial I/O0, SBI) Serial clock I/O (3-wire serial I/O1) Serial clock I/O (3-wire serial I/O2) External interrupt request -- Y Input of a count clock for timer/counter 1 Y Capture/trigger signal for CR11 or CR12 Y Input of a count clock for timer/counter 2 Y Capture/trigger signal for CR22 Y Input of a count clock for timer/counter 2 Y Capture/trigger signal for CR21 Y Input of a count clock for timer/counter 0 Y Capture/trigger signal for CR02 -- Input of a conversion start trigger for A/D converter Time multiplexing address/data bus (for connecting external memory) High-order address bus (for connecting external memory) High-order address bus during address expansion (for connecting external memory) Strobe signal output for reading the contents of external memory Strobe signal output for writing on external memory Wait signal insertion Refresh pulse output to external pseudo static memory Input of bus hold request Output of bus hold response Latch timing output of time multiplexing address (A0-A7) (for connecting external memory) Function 13 m PD784020, 784021 6.2 NON-PORT PINS (2/2) Pin RESET X1 X2 ANI0-ANI7 ANO0, ANO1 AVREF1 AVREF2, AVREF3 AVDD AVSS VDD VSS TEST I/O Input Input -- Input Output -- P70-P77 -- -- Dual-function -- -- Chip reset Crystal input for system clock oscillation (A clock pulse can also be input to the X1 pin.) Analog voltage inputs for the A/D converter Analog voltage inputs for the D/A converter Application of A/D converter reference voltage Application of D/A converter reference voltage Positive power supply for the A/D converter Ground for the A/D converter Positive power supply Ground Directly connect to VSS. (The TEST pin is for the IC test.) Function 14 m PD784020, 784021 6.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS Table 6-1 describes the types of I/O circuits for pins and the handling of unused pins. Fig. 6-1 shows the configuration of these various types of I/O circuits. Table 6-1 Types of I/O Circuits for Pins and Handling of Unused Pins (1/2) Pin P00-P07 P10/PWM0 P11/PWM1 P12/ASCK2/SCK2 P13/RxD2/SI2 P14/TxD2/SO2 P15-P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 I/O circuit type 5-A I/O I/O Recommended connection method for unused pins Input state : To be connected to VDD Output state: To be left open 8-A 5-A 2 Input To be connected to VDD or VSS 2-A To be connected to VDD 8-A I/O Input state : To be connected to VDD Output state: To be left open P26/INTP5 P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0 P33/SO0/SB0 P34/TO0-P37/TO3 AD0-AD7 A8-A15 P60/A16-P63/A19 RD WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0-P77/ANI7 2-A Input To be connected to VDD 5-A I/O Input state : To be connected to VDD Output state: To be left open 8-A 10-A 5-A OutputNote To be left open I/O Input state : To be connected to VDD Output state: To be left open 20 Input state : To be connected to VDD or VSS Output state: To be left open ANO0, ANO1 ASTB 12 4 Output To be left open Note These pins function as output-only pins depending on the internal circuit, though their I/O type is 5-A. 15 m PD784020, 784021 Table 6-1 Types of I/O Circuits for Pins and Handling of Unused Pins (2/2) Pin RESET TEST AVREF1-AVREF3 AVSS AVDD I/O circuit type 2 1 -- I/O Input Recommended connection method for unused pins -- To be connected to VSS directly To be connected to VSS To be connected to VDD Caution When the I/O mode of an I/O dual-function pin is unpredictable, connect the pin to VDD through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when I/O is switched by software). Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product. (Some circuits are not included.) 16 m PD784020, 784021 Fig. 6-1 I/O Circuits for Pins Type 1 VDD P IN N Type 2-A VDD P Pull-up enable IN Type 2 IN Schmitt trigger input with hysteresis characteristics Type 5-A Schmitt trigger input with hysteresis characteristics Type 4 VDD Pull-up enable Data VDD Data P VDD P IN/OUT P OUT Output disable N Output disable Input enable N Push-pull output which can output high impedance (both the positive and negative channels are off.) Type 8-A VDD Pull-up enable Data Type 12 P VDD P IN/OUT Analog output voltage P OUT N Output disable N Type 10-A VDD Type 20 Data VDD P IN/OUT Pull-up enable VDD Data Open drain Output disable P P Output disable N IN/OUT N Comparator + - VREF (Threshold voltage) Input enable P N 17 m PD784020, 784021 7. CPU ARCHITECTURE 7.1 MEMORY SPACE A 1M-byte memory space can be accessed. By using a LOCATION instruction, the mode for mapping internal data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be executed after a reset, and can be used only once. (1) When the LOCATION 0 instruction is executed Internal data areas are mapped to 0FD00H-0FFFFH for themPD784020 and 0F700H-0FFFFH for the mPD784021. (2) When the LOCATION 0FH instruction is executed Internal data areas are mapped to FFD00H-FFFFFH for themPD784020 and FF700H-FFFFFH for themPD784021. 18 Fig. 7-1 mPD784020 Memory MapH H When the LOCATION 0 instruction is executed FFFFFH 0FEFFH FFEFFH General-purpose registers (128 bytes) Internal RAM (512 bytes) FFE80H FFE7FH FFD00H FFCFFH FFE2FH FFE06H FFD00H External memory (960K bytes) 0FE80H 0FE7FH 0FE2FH Macro service control 0 F E 0 6 H word area (42 bytes) Data area (512 bytes) 0FD00H When the LOCATION 0FH F F F F F H instruction is executed FFFDFH Special function registers (SFRs) FFFD0H (256 bytes) FFF00H FFEFFH 10000H 0 F F F F H Special function registers (SFRs) 0FFDFH 0FFD0H (256 bytes) 0FF00H 0FEFFH Internal RAM (512 bytes) 0FD00H 0FCFFH External memory (1,047,808 bytes) External memory (64,768 bytes) 00FFFH 00800H 007FFH 00080H 0007FH 00040H 0003FH 00000H Note 00FFFH CALLF entry area (2K bytes) 00800H 007FFH CALLT table area (64 bytes) Vector table area (64 bytes) 00080H 0007FH 10000H 0FFFFH Note 00000H 00000H m PD784020, 784021 Note Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset. 19 20 Fig. 7-2 mPD784021 Memory Map 0FEFFH External memory (960K bytes) 0FE80H 0FE7FH FFE80H FF700H FFE7FH FF6FFH FFE2FH FFE06H FFD00H FFCFFH Program/data area (1,536 bytes) FF700H External memory (1,046,272 bytes) 0FE2FH Macro service control 0 F E 0 6 H word area (42 bytes) Data area (512 bytes) 0FD00H 0FCFFH 0F700H General-purpose registers (128 bytes) When the LOCATION 0FH F F F F F H instruction is executed FFFDFH Special function registers (SFRs) FFFD0H (256 bytes) FFF00H FFEFFH FFEFFH Internal RAM (2,048 bytes) External memory (63,232 bytes) 00FFFH CALLF entry area (2K bytes) 00800H 007FFH 00080H 0007FH 00040H 0003FH 00000H CALLT table area (64 bytes) Vector table area (64 bytes) 00800H 10000H 007FFH 0FFFFH 00080H 0007FH Note Note When the LOCATION 0 instruction is executed FFFFFH 10000H 0 F F F F H Special function registers (SFRs) 0FFDFH 0FFD0H (256 bytes) 0FF00H 0FEFFH 0FD00H 0FCFFH Internal RAM (2,048 bytes) 0F700H 0F6FFH 00FFFH 00000H 00000H m PD784020, 784021 Note Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset. m PD784020, 784021 7.2 7.2.1 CPU REGISTERS General-Purpose Registers A set of general-purpose registers consists of sixteen general-purpose 8-bit registers. Two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers. Eight banks of this register set are provided. The user can switch between banks by software or the context switching function. General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto internal RAM. Fig. 7-3 General-Purpose Register Format A (R1) AX (RP0) B (R3) BC (RP1) R5 RP2 R7 RP3 V VVP (RG4) U T W R9 VP (RP4) X (R0) C (R2) R4 R6 R8 R11 R10 UUP (RG5) UP (RP5) D (R13) E (R12) TDE (RG6) DE (RP6) H (R15) L (R14) WHL (RG7) HL (RP7) The character strings enclosed in parentheses represent absolute names. 8 banks Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers, respectively. However, this function must be used only when using programs for the 78K/III series. 21 m PD784020, 784021 7.2.2 Control Registers (1) Program counter (PC) This register is a 20-bit program counter. The program counter is automatically updated by program execution. Fig. 7-4 Format of Program Counter (PC) 19 PC 0 (2) Program Status Word (PSW) This register holds the CPU state. The program status word is automatically updated by program execution. Fig. 7-5 Format of Program Status Word (PSW) 15 PSWH PSW 7 PSWL S 6 Z 5 RSSNote 4 AC 3 IE 2 P/V 1 0 0 CY UF 14 RBS2 13 RBS1 12 RBS0 11 10 9 8 Note This flag is used to maintain compatibility with the 78K/III series. This flag must be set to 0 when programs for the 78K/III series are being used. (3) Stack pointer (SP) This register is a 24-bit pointer for holding the start address of the stack. The high-order 4 bits must be set to 0. Fig. 7-6 Format of Stack Pointer (SP) 23 PC 0 0 0 0 20 0 22 m PD784020, 784021 7.2.3 Special Function Registers (SFRs) H The special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H and 0FFFFHNote. Note Applicable when the LOCATION 0 instruction is executed. FFF00H-FFFFFH when the LOCATION 0FH instruction is executed. Caution Never attempt to access addresses in this area where no SFR is allocated. Otherwise, the mPD784021 may be placed in the deadlock state. The deadlock state can be cleared only by a reset. Table 7-1 lists the special function registers (SFRs). The titles of the table columns are explained below. * Abbreviation ................... Symbol used to represent a built-in SFR. The abbreviations listed in the table are reserved words for the NEC assembler (RA78K4). The C compiler (CC78K4) allows the abbreviations to be used as sfr variables of bit type with the #pragma sfr command. * R/W ................................. Indicates whether each SFR allows read and/or write operations. R/W : Allows both read and write operations. R W : Allows read operations only. : Allows write operations only. * Manipulatable bits .......... Indicates the maximum number of bits that can be manipulated whenever an SFR is manipulated. An SFR that supports 16-bit manipulation can be described in the sfr operand. For address specification, an even-numbered address must be specified. An SFR that supports 1-bit manipulation can be described in a bit manipulation instruction. * When reset ..................... Indicates the state of each register when RESET is applied. 23 m PD784020, 784021 Table 7-1 Special Function Registers (SFRs) (1/4) Manipulatable bits AddressNote 0FF00H 0FF01H 0FF02H 0FF03H 0FF06H 0FF07H 0FF0EH 0FF0FH 0FF10H 0FF12H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF20H 0FF21H 0FF23H 0FF26H 0FF27H 0FF2EH 0FF30H 0FF31H 0FF32H 0FF33H Port 0 buffer register H Compare register (timer/counter 0) Capture/compare register (timer/counter 0) Compare register L (timer/counter 1) Compare register H (timer/counter 1) Capture/compare register L (timer/counter 1) Capture/compare register H (timer/counter 1) Compare register L (timer/counter 2) Compare register H (timer/counter 2) Capture/compare register L (timer/counter 2) Capture/compare register H (timer/counter 2) Compare register L (timer 3) Compare register H (timer 3) Port 0 mode register Port 1 mode register Port 3 mode register Port 6 mode register Port 7 mode register Real-time output port control register Capture/compare control register 0 Timer output control register Capture/compare control register 1 Capture/compare control register 2 Special function register (SFR) name Port 0 Port 1 Port 2 Port 3 Port 6 Port 7 Abbreviation P0 P1 P2 P3 P6 P7 Port 0 buffer register L P0L P0H CR00 CR01 CR10 CR10W - CR11 CR11W - CR20 CR20W - CR21 CR21W - CR30 CR30W - PM0 PM1 PM3 PM6 PM7 RTPC CRC0 TOC CRC1 CRC2 R R/W R/W 1 bit R/W l l l l l l l l When reset 8 bits 16 bits l l l l l l l l - - - - - - - - l l l Undefined 00H Undefined - - - - - - - - - - - - l l l l l l - - l - l l - l l - l l - l l - l l l l l l l l l l - - - - - - - - - - FFH 00H 10H 00H - l - - 10H Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 24 m PD784020, 784021 Table 7-1 Special Function Registers (SFRs) (2/4) AddressNote 0FF36H 0FF38H 0FF39H 0FF3AH 0FF3BH 0FF41H 0FF43H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF5CH 0FF5DH 0FF5EH 0FF5FH 0FF60H 0FF61H 0FF62H 0FF68H 0FF6AH 0FF70H 0FF71H 0FF72H 0FF74H 0FF7DH 0FF80H 0FF82H Manipulatable bits Special function register (SFR) name Capture register (timer/counter 0) Capture register L (timer/counter 1) Capture register H (timer/counter 1) Capture register L (timer/counter 2) Capture register H (timer/counter 2) Port 1 mode control register Port 3 mode control register Register for optional pull-up resistor Timer register 0 Abbreviation CR02 CR12 CR12W - CR22 CR22W - PMC1 PMC3 PUO TM0 R R/W R/W 1 bit R - - - - - l l l When reset 8 bits 16 bits - l l l 0000H - l l - l l l - - - l 00H - - - - l 0000H Timer register 1 TM1 - TM1W - - l - l l Timer register 2 TM2 - TM2W - - - l l Timer register 3 TM3 - TM3W - - R/W - l - l l l l l l l l l l l Prescaler mode register 0 Timer control register 0 Prescaler mode register 1 Timer control register 1 D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register A/D converter mode register A/D conversion result register PWM control register PWM prescaler register PWM modulo register 0 PWM modulo register 1 One-shot pulse output control register Serial bus interface control register Synchronous serial interface mode register PRM0 TMC0 PRM1 TMC1 DACS0 DACS1 DAM ADM ADCR PWMC PWPR PWM0 PWM1 OSPC SBIC CSIM - - - - - - - - - - - l l 11H 00H 11H 00H - l - - l l 03H 00H Undefined 05H 00H Undefined R R/W - l - - - l l l - - l l l - - - 00H Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 25 m PD784020, 784021 Table 7-1 Special Function Registers (SFRs) (3/4) Manipulatable bits AddressNote 1 0FF84H 0FF85H 0FF86H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH Special function register (SFR) name Synchronous serial interface mode register 1 Synchronous serial interface mode register 2 Serial shift register Asynchronous serial interface mode register Asynchronous serial interface mode register 2 Asynchronous serial interface status register Asynchronous serial interface status register 2 Serial receive buffer: UART0 Serial transmission shift register: UART0 Serial shift register: IOE1 0FF8DH Serial receive buffer: UART2 Serial transmission shift register: UART2 Serial shift register: IOE2 0FF90H 0FF91H 0FFA0H 0FFA1H 0FFA4H 0FFA8H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFC0H 0FFC2H 0FFC4H 0FFC5H 0FFC6H 0FFC7H 0FFC8H Baud rate generator control register Baud rate generator control register 2 External interrupt mode register 0 External interrupt mode register 1 Sampling clock selection register In-service priority register Interrupt mode control register Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1L Standby control register Watchdog timer mode register Memory expansion mode register Hold mode register Clock output mode register Programmable wait control register 1 Programmable wait control register 2 Abbreviation CSIM1 CSIM2 SIO ASIM ASIM2 ASIS ASIS2 RXB TXS SIO1 RXB2 TXS2 SIO2 BRGC BRGC2 INTM0 INTM1 SCS0 ISPR IMC MK0L MK0 MK0H MK1L STBC WDM MM HLDM CLOM PWC1 PWC2 R R/W W R/W R W R/W R R/W 1 bit R/W l l When reset 8 bits 16 bits l l l l l l l l l l l l l l l l l l l l l l l lNote 2 lNote 2 l l l l - - - - - - - - - - - - - - - - - - - - l 00H - l l l l - - - - - - - - l l Undefined 00H - l l l l l 80H FFFFH - - - - - - - l FFH 30H 00H 20H 00H - - l l l - - AAH AAAAH - Notes 1. Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 2. A write operation can be performed only with special instructions MOV STBC,#byte and MOV WDM,#byte. Other instructions cannot perform a write operation. 26 m PD784020, 784021 Table 7-1 Special Function Registers (SFRs) (4/4) Manipulatable bits AddressNote 0FFCCH 0FFCDH 0FFCFH 0FFD0H0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTC00) Interrupt control register (INTC01) Interrupt control register (INTC10) Interrupt control register (INTC11) Interrupt control register (INTC20) Interrupt control register (INTC21) Interrupt control register (INTC30) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTAD) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTCSI1) 0FFF0H 0FFF1H 0FFF2H 0FFF3H Interrupt control register (INTST) Interrupt control register (INTCSI) Interrupt control register (INTSER2) Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF4H Interrupt control register (INTST2) PIC0 PIC1 PIC2 PIC3 CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 PIC4 PIC5 ADIC SERIC SRIC CSIIC1 STIC CSIIC SERIC2 SRIC2 CSIIC2 STIC2 l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l Special function register (SFR) name Refresh mode register Refresh area specification register Oscillation settling time specification register External SFR area Abbreviation RFM RFA OSTS - R/W 1 bit R/W l l When reset 8 bits 16 bits l l l l - - - - 00H - l - - - - - - - - - - - - - - - - - - - - - - - - 43H Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 27 m PD784020, 784021 8. PERIPHERAL HARDWARE FUNCTIONS 8.1 PORTS The ports shown in Fig. 8-1 are provided to enable the application of wide-ranging control. Table 8-1 lists the functions of the ports. For the inputs to port 0 to port 6, a built-in pull-up resistor can be specified by software. Fig. 8-1 Port Configuration P00 Port 0 P07 P10 Port 1 P17 P20-P27 8 Port 2 P30 Port 3 P37 P60 P63 P66 P67 P70 Port 6 Port 7 P77 28 m PD784020, 784021 Table 8-1 Port Functions Port name Port 0 Pin P00-P07 Function * Bit-by-bit input/output setting supported * Operable as 4-bit real-time outputs (P00-P03, P04-P07) * Capable of driving transistors * Bit-by-bit input/output setting supported * Capable of driving LEDs * Input port * Bit-by-bit input/output setting supported Pull-up specification by software Specified as a batch for all pins placed in input mode. Port 1 P10-P17 Specified as a batch for all pins placed in input mode. Specified for the 6 bits (P22-P27) as a batch. Specified as a batch for all pins placed in input mode. Specified as a batch for all pins placed in input mode. -- Port 2 Port 3 P20-P27 P30-P37 Port 6 P60-P63 P66, P67 * Output-only port * Bit-by-bit input/output setting supported * Bit-by-bit input/output setting supported Port 7 P70-P77 8.2 CLOCK GENERATOR A circuit for generating the clock signal required for operation is provided. The clock generator includes a frequency divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed operation is not necessary. Fig. 8-2 Block Diagram of Clock Generator X1 Oscillator X2 fXX 1/2 1/2 1/2 1/2 Selector fCLK CPU Peripheral circuits fXX/2 UART/IOE INTP0 noise eliminator Oscillation settling timer Remark fXX : Oscillator frequency or external clock input fCLK: Internal operating frequency 29 m PD784020, 784021 Fig. 8-3 Examples of Using Oscillator (1) Crystal/ceramic oscillation PD784021 VSS X1 X2 H (2) External clock * When EXTC bit of OSTS = 1 PD784021 X1 * When EXTC bit of OSTS = 0 PD784021 X1 PD74HC04, etc. X2 Open X2 Caution When using the clock generator, to avoid problems caused by influences such as stray capacitance, run all wiring within the area indicated by the dotted lines according to the following rules: * * * * Minimize the wiring length. Wires must never cross other signal lines. Wires must never run near a line carrying a large varying current. The grounding point of the capacitor of the oscillator circuit must always be at the same potential as VSS. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator circuit. 30 m PD784020, 784021 8.3 REAL-TIME OUTPUT PORT The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. Thus, pulse output that is free of jitter can be obtained. Therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors) where an arbitrary pattern is output at arbitrary intervals. As shown in Fig. 8-4, the real-time output port is built around port 0 and the port 0 buffer register (P0H, P0L). Fig. 8-4 Block Diagram of Real-Time Output Port Internal bus 8 Real-time output port control register (RTPC) INTP0 (externally) INTC10 (from timer/counter 1) INTC11 (from timer/counter 1) 4 Buffer register P0H 4 8 P0L Output trigger control circuit 4 4 Output latch (P0) P07 P00 31 m PD784020, 784021 8.4 TIMERS/COUNTERS Three timer/counter units and one timer unit are incorporated. Moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units. Table 8-2 Timer/Counter Operation Name Item Count pulse width 8 bits 16 bits Operating mode Interval timer External event counter One-shot timer Function Timer output Toggle output PWM/PPG output One-shot pulse outputNote Real-time output Pulse width measurement Number of interrupt requests Timer/counter 0 - l Timer/counter 1 l l Timer/counter 2 l l Timer 3 l l H 2ch l 2ch l 2ch l l 1ch - - - - - - - - 1 - 2ch l l l - - - - - l 2ch l l - - 2 inputs 2 - 1 input 2 1 input 2 Note The one-shot pulse output function makes the level of a pulse output active by software, and makes the level of a pulse output inactive by hardware (interrupt request signal). Note that this function differs from the one-shot timer function of timer/counter 2. 32 m PD784020, 784021 Fig. 8-5 Timer/Counter Block Diagram Timer/counter 0 Clear information H Software trigger Selector fxx/8 Prescaler Timer register 0 (TM0) OVF Pulse output control Compare register (CR00) Match Match TO0 Compare register (CR01) TO1 INTP3 Edge detection Capture register (CR02) INTP3 INTC00 INTC01 Timer/counter 1 Clear information Selector fxx/8 Prescaler Event input Timer register 1 (TM1/TM1M) OVF Match Compare register (CR10/CR10W) INTC10 To real-time output port INTP0 Edge detection Capture/compare register (CR11/CR11W) Match INTC11 INTP0 Capture register (CR12/CR12W) Timer/counter 2 Clear information Selector fxx/8 Prescaler Timer register 2 (TM2/TM2W) OVF Pulse output control INTP2/C1 Edge detection Compare register (CR20/CR20W) Match TO2 INTP2 Capture/compare register (CR21/CR21W) Match TO3 INTP1 Edge detection Capture register (CR22/CR22W) INTC20 INTC21 INTP1 Timer 3 fxx/8 Prescaler Timer register 3 (TM3/TM3W) Clear Compare register (CR30/CR30W) Match CSI INTC30 Remark OVF: Overflow flag 33 m PD784020, 784021 8.5 PWM OUTPUT (PWM0, PWM1) Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 48.8 kHz (fCLK = 12.5 MHz) are incorporated. Low or high active level can be selected for the PWM output channels, independently of each other. This output is best suited to DC motor speed control. Fig. 8-6 Block Diagram of PWM Output Unit Internal bus 16 PWM modulo register PWMn 15 8 87 4 Reload control 43 0 8 PWM control register (PWMC) fCLK Prescaler 8-bit down-counter Pulse control circuit 4-bit counter Output control PWMn (output pin) 1/256 Remark n = 0, 1 34 m PD784020, 784021 8.6 A/D CONVERTER An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0-ANI7) is incorporated. The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved. (The conversion time is about 10 ms at fCLK = 12.5 MHz.) A/D conversion can be started in any of the following modes: * Hardware start : Conversion is started by means of trigger input (INTP5). * Software start : Conversion is started by means of bit setting the A/D converter mode register (ADM). After conversion has started, one of the following modes can be selected: * Scan mode : Multiple analog inputs are selected sequentially to obtain conversion data from all pins. * Select mode : A single analog input is selected at all times to enable conversion data to be obtained continuously. ADM is used to specify the above modes, as well as the termination of conversion. When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature, the results of conversion can be continuously transferred to memory by the macro service. Fig. 8-7 Block Diagram of A/D Converter ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Input selector Sample-and-hold circuit Series resistor string AVREF1 Voltage comparator R/2 R Successive conversion register (SAR) Edge detector Conversion trigger INTAD INTP5 Control circuit Tap selector R/2 AVSS Trigger enable 8 A/ D converter mode register (ADM) A/ D conversion result register (ADCR) 8 8 Internal bus 35 m PD784020, 784021 8.7 D/A CONVERTER Two digital/analog (D/A) converter channels of voltage output type, having a resolution of 8 bits, are incorporated. A resistor string system is used for conversion. By writing the value to be subject to D/A conversion in the 8-bit D/A conversion value setting register (DACSn: n = 0, 1), the resulting analog value is output on ANOn (n = 0, 1). The range of the output voltages is determined by the voltages applied to the AVREF2 and AVREF3 pins. Because of its high output impedance, no current can be obtained from an output pin. When the load impedance is low, insert a buffer amplifier between the load and the converter. The impedance of the ANOn pin goes high while the RESET signal is low. DACSn is set to 0 after a reset is released. Fig. 8-8 Block Diagram of D/A Converter AVREF2 R Tap selector R ANOn R R AVREF3 RESET DACSn DACEn 8 8 Internal bus Remark n = 0, 1 36 m PD784020, 784021 8.8 SERIAL INTERFACE Three independent serial interface channels are incorporated. * Asynchronous serial interface (UART)/three-wire serial I/O (IOE) 2 * Synchronous serial interface (CSI) 1 * Three-wire serial I/O (IOE) * Serial bus interface (SBI) So, communication with points external to the system and local communication within the system can be performed at the same time. (See Fig. 8-9.) Fig. 8-9 Example Serial Interfaces (a) UART + SBI PD4711A (UART) PD784021 (master) (SBI) VDD PD75402A (slave) RxD TxD Port SB0 SCK0 SB0 SCK RS-232-C driver/ receiver PD75328 (slave) PD4711A (UART) SB0 SCK RxD2 TxD2 Port LCD RS-232-C driver/ receiver (b) UART + Three-wire serial I/O PD4711A (UART) PD784021 (master) [Three-wire serial I/O] RxD TxD Port SO0 SI0 SCK0 INTPm Port Note PD75108 (slave) SI SO SCK Port INT RS-232-C driver/ receiver PD78014 (slave) SO1 SI1 SCK1 INTPn Port Note SI SO SCK Port INT Note Handshake line 37 m PD784020, 784021 8.8.1 Asynchronous Serial Interface/Three-Wire Serial I/O (UART/IOE) Two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire serial I/O mode can be selected. (1) Asynchronous serial interface mode In this mode, 1-byte data is transferred after a start bit. A baud rate generator is incorporated to enable communication at a wide range of baud rates. Moreover, the frequency of a clock signal applied to the ASCK pin can be divided to define a baud rate. With the baud rate generator, the baud rate conforming to the MIDI standard (31.25 kbps) can be obtained. Fig. 8-10 Block Diagram of Asynchronous Serial Interface Mode Internal bus Receive buffer RXB, RXB2 RxD, RxD2 Receive shift register Transmission shift register TXS, TXS2 TxD, TxD2 INTSR, INTSR2 INTSER, INTSER2 Reception control parity check Transmission control parity bit addition INTST, INTST2 Baud rate generator 1/2m fXX/2 ASCK, ASCK2 Selector 1/2 n+1 1/2m Remark fXX: Oscillator frequency or external clock input n = 0 to 11 m = 16 to 30 38 m PD784020, 784021 (2) Three-wire serial I/O mode In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK) and the two serial data lines (SI and SO). In general, a handshake line is required to check the state of communication. Fig. 8-11 Block Diagram of Three-Wire Serial I/O Mode Internal bus Direction control circuit SIO1, SIO2 SI1, SI2 Shift register Output latch SO1, SO2 SCK1, SCK2 Serial clock counter Interrupt signal generator INTCSI1, INTCSI2 Serial clock control circuit Remark fXX: Oscillator frequency or external clock input n = 0 to 11 m = 1, 16 to 30 Selector 1/m 1/2n+1 fXX/2 39 m PD784020, 784021 8.8.2 Synchronous Serial Interface (CSI) With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. Fig. 8-12 Block Diagram of Synchronous Serial Interface Internal bus Direction control circuit Set Selector Clear SI0 SO0/SB0 SIO Shift register Output latch N-ch open-drain output enabled (when SB0 or SBI mode is used) Busy/ acknowledge detection circuit Bus release/ command/ acknowledge detection circuit SCK0 Serial clock counter Interrupt signal generation circuit INTCSI TM 3 output/2 Serial clock control circuit Selector fCLK/8 fCLK/32 Remark fCLK: Internal system clock frequency (system clock frequency/2) 40 m PD784020, 784021 (1) Three-wire serial I/O mode This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK0) and serial data lines (SI0 and SO0). In general, a handshake line is required to check the state of communication. (2) SBI mode The SBI mode allows communication with more than one device via two lines: the serial clock (SCK0) and serial bus (SB0). The SBI mode is the standard NEC serial interface. A master device outputs an address through the SB0 pin to select a slave device with which communication is to be performed. After a target device is selected, commands and data are transmitted between the master device and slave device. 8.9 EDGE DETECTION FUNCTION The interrupt input pins (NMI, INTP0-INTP5) are used to apply not only interrupt requests but also trigger signals for the built-in circuits. As these pins are triggered by an edge (rising or falling) of an input signal, a function for edge detection is incorporated. Moreover, a noise suppression function is provided to prevent erroneous edge detection caused by noise. Pin NMI INTP0-INTP3 INTP4, INTP5 Detectable edge Rising edge or falling edge Rising edge or falling edge, or both edges Noise suppression method Analog delay Clock samplingNote Analog delay Note INTP0 is used for sampling clock selection. 41 m PD784020, 784021 8.10 WATCHDOG TIMER A watchdog timer is incorporated for CPU runaway detection. The watchdog timer, if not cleared by software within a specified interval, generates a nonmaskable interrupt. Furthermore, once watchdog timer operation is enabled, it cannot be disabled by software. The user can specify whether priority is placed on an interrupt based on the watchdog timer or on an interrupt based on the NMI pin. H Fig. 8-13 Block Diagram of Watchdog Timer fCLK Timer fCLK/221 fCLK/220 Selector fCLK/219 fCLK/217 INTWDT Clear signal 42 m PD784020, 784021 9. INTERRUPT FUNCTION Table 9-1 lists the interrupt request handling modes. These modes are selected by software. Table 9-1 Interrupt Request Handling Modes Handling mode Vectored interrupt Handled by Software Handling Branches to a handling routine for execution (arbitrary handling). Automatically selects a register bank, and branches to a handling routine for execution (arbitrary handling). PC and PSW contents The PC and PSW contents are pushed to and popped from the stack. The PC and PSW contents are saved to and read from a fixed area in the register bank. Maintained Context switching Macro service Firmware Performs operations such as memory-to-I/Odevice data transfer (fixed handling). 9.1 INTERRUPT SOURCE An interrupt can be issued from any one of the interrupt sources listed in Table 9-2: execution of a BRK instruction, an operand error, or any of the 23 other interrupt sources. Four levels of interrupt handling priority can be set. Priority levels can be set to nest control during interrupt handling or to concurrently generate interrupt requests. Nested macro services, however, are performed without suspension. When interrupt requests having the same priority level are generated, they are handled according to the default priority (fixed). (See Table 9-2.) 43 m PD784020, 784021 Table 9-2 Interrupt Sources Type Default priority - Name BRK instruction Operand error Source Trigger Instruction execution When the MOV STBC,#byte or MOV WDM,#byte instruction is executed, exclusive OR of the byte operand and byte does not produce FFH. Detection of edge input on the pin Watchdog timer overflow Detection of edge input on the pin (TM1/TM1W capture trigger) Detection of edge input on the pin (TM2/TM2W capture trigger) Detection of edge input on the pin (TM2/TM2W event counter input) Detection of edge input on the pin (TM0 capture trigger) TM0-CR00 match signal issued TM0-CR01 match signal issued TM1-CR10 match signal issued (in 8-bit operation mode) TM1W-CR10W match signal issued (in 16-bit operation mode) TM1-CR11 match signal issued (in 8-bit operation mode) TM1W-CR11W match signal issued (in 16-bit operation mode) TM2-CR20 match signal issued (in 8-bit operation mode) TM2W-CR20W match signal issued (in 16-bit operation mode) TM2-CR21 match signal issued (in 8-bit operation mode) TM2W-CR21W match signal issued (in 16-bit operation mode) TM3-CR30 match signal issued (in 8-bit operation mode) TM3W-CR30W match signal issued (in 16-bit operation mode) Detection of edge input on the pin Detection of edge input on the pin A/D converter processing completed (ADCR transfer) ASI0 reception error ASI0 reception completed or CSI1 transfer completed Internal/ external - Macro service - Software Nonmaskable - NMI WDT External Internal External - H Maskable 0 (highest) 1 2 3 4 5 6 INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 Enabled Internal Enabled 7 INTC11 8 INTC20 9 INTC21 10 INTC30 11 12 13 14 15 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 External Enabled Internal Enabled - Enabled 16 17 18 19 INTST INTCSI INTSER2 INTSR2 INTCSI2 ASI0 transmission completed CSI0 transfer completed ASI2 reception error ASI2 reception completed or CSI2 transfer completed - Enabled 20 (lowest) INTST2 ASI2 transmission completed Remark ASI: Asynchronous serial interface CSI: Synchronous serial interface 44 m PD784020, 784021 9.2 VECTORED INTERRUPT When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt source is used as the branch address. Interrupt handling by the CPU consists of the following operations : * When a branch occurs : Push the CPU status (PC and PSW contents) to the stack. * When control is returned: Pop the CPU status (PC and PSW contents) from the stack. To return control from the handling routine to the main routine, use the RETI instruction. The branch destination addresses must be within the range of 0 to FFFFH. Table 9-3 Vector Table Address Interrupt source BRK instruction Operand error NMI WDT INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC20 INTC21 INTC30 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 INTST INTCSI INTSER2 INTSR2 INTCSI2 INTST2 Vector table address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 45 m PD784020, 784021 9.3 CONTEXT SWITCHING When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register bank. The branch address must be within the range of 0 to FFFFH. Fig. 9-1 Context Switching Caused by an Interrupt Request 0000B 7 Transfer PC15-0 Register bank n (n = 0-7) A B X C R4 R6 VP UP D H E L Register bank (0-7) PC19-16 Save (Bits 8 to 11 of temporary register) 2 6 Exchange R5 R7 5 Save V U Temporary register 1 T W Save PSW Switching between register banks (RBS0-RBS2 n) RSS 0 4 IE 0 3 9.4 MACRO SERVICE The macro service function enables data transfer between memory and special function registers (SFRs) without requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same transfer cycle to directly transfer data without having to perform data fetch. Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible. Fig. 9-2 Macro Service Read CPU Memory Write Macro service controller Write SFR Read Internal bus 46 m PD784020, 784021 9.5 EXAMPLES OF MACRO SERVICE APPLICATIONS (1) Serial interface transmission Transmission data storage buffer (memory) Data n Data n-1 Data 2 Data 1 Internal bus TxD Transmission shift register TXS (SFR) Transmission control INTST Each time a macro service request (INTST) is generated, the next transmission data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS (that is, once the transmission data storage buffer becomes empty), a vectored interrupt request (INTST) is generated. (2) Serial interface reception Reception data storage buffer (memory) Data n Data n-1 Data 2 Data 1 Internal bus Reception buffer RXB (SFR) RxD Reception shift register Reception control INTSR Each time a macro service request (INTSR) is generated, reception data is transferred from RXB to memory. When data n (last byte) has been transferred to memory (that is, once the reception data storage buffer becomes full), a vectored interrupt request (INTSR) is generated. 47 m PD784020, 784021 (3) Real-time output port INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used to independently control two stepping motors. They can also be applied to PWM and DC motor control. Output pattern profile (memory) Pn Pn-1 Output timing profile (memory) Tn Tn-1 P2 P1 T2 T1 Internal bus Internal bus Match (SFR) P0L INTC10 Output latch P00-P03 TM1 CR10 (SFR) Each time a macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer register (P0L) and compare register (CR10), respectively. When the contents of timer register 1 (TM1) and CR10 match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When Tn (last byte) is transferred to CR10, a vectored interrupt request (INTC10) is generated. For INTC11, the same operation as that performed for INTC10 is performed. 48 m PD784020, 784021 10. LOCAL BUS INTERFACE The local bus interface enables the connection of external memory and I/O devices (memory-mapped I/O). It supports a 1M-byte memory space. (See Fig. 10-1.) Fig. 10-1 Example of Local Bus Interface PD784021 A16-A19 RD WR REFRQ Decoder Pseudo SRAM PROM PD27C1001A Kanji character generator PD24C1000 AD0-AD7 Data bus Data bus ASTB Latch Address bus A8-A15 Gate array for I/O expansion including Centronics interface circuit, etc. 10.1 MEMORY EXPANSION By adding external memory, program memory or data memory can be expanded, 64K bytes at a time, to approximately 1M byte (three steps). 49 m PD784020, 784021 10.2 MEMORY SPACE The 1M-byte memory space is divided into eight spaces, each having a logical address. Each of these spaces can be controlled using the programmable wait and pseudo-static RAM refresh functions. Fig. 10-2 Memory Space FFFFFH 512K bytes 80000H 7FFFFH 256K bytes 40000H 3FFFFH 128K bytes 20000H 1FFFFH 64K bytes 10000H 0FFFFH 16K bytes 0C000H 0BFFFH 16K bytes 08000H 07FFFH 16K bytes 04000H 03FFFH 16K bytes 00000H 50 m PD784020, 784021 10.3 PROGRAMMABLE WAIT When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even when memory devices having different access times are connected. In addition, an address wait function that extends the ASTB signal active period is provided to produce a longer address decode time. (This function is set for the entire space.) 10.4 PSEUDO-STATIC RAM REFRESH FUNCTION Refresh is performed as follows: * Pulse refresh : A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular intervals. When the memory space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the REFRQ pin as the memory is being accessed. This can prevent the refresh cycle from suspending normal memory access. * Power-down self-refresh : In standby mode, a low-level signal is output on the REFRQ pin to maintain the contents of pseudo-static RAM. 10.5 BUS HOLD FUNCTION A bus hold function is provided to facilitate connection to devices such as a DMA controller. Suppose that a bus hold request signal (HLDRQ) is received from an external bus master. In this case, upon the completion of the bus cycle being performed, the address bus, address/data bus, ASTB, RD, and WR pins are placed in the high-impedance state, and the bus hold acknowledge signal (HLDAK) is made active to release the bus for the external bus master. While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled. 51 m PD784020, 784021 11. STANDBY FUNCTION The standby function allows the power consumption of the chip to be reduced. The following standby modes are supported: * HALT mode : The CPU operation clock is stopped. By occassionally inserting the HALT mode during normal operation, the overall average power consumption can be reduced. * IDLE mode : The entire system is stopped, with the exception of the oscillator circuit. This mode consumes only very little more power than STOP mode, but normal program operation can be restored in almost as little time as that required to restore normal program operation from HALT mode. * STOP mode : The oscillator is stopped. All operations in the chip stop, such that only leakage current flows. These modes can be selected by software. A macro service can be initiated in HALT mode. Fig. 11-1 Standby Mode Status Transition Macro service request Program operation Int Wait for oscillation settling 1 e ot ttling tion se Oscilla ses p time ela End of one operation End of macro service Macro service er 1 ut No inp re ice rv se ro ac M S R et IN ESE IDL TP T E 4, in IN pu TP t 5 inp TP IN NM I, NM I, STOP (standby) IDLE (standby) Request for masked interrupt HALT (standby) Notes 1. INTP4 and INTP5 are applied when not masked. 2. Only when the interrupt request is not masked Remark NMI is enabled only by external input. The watchdog timer cannot be used to release one of the standby modes (STOP or IDLE mode). 52 En d P TO ut t S inp Se ET S RE 5 TP IN 4, of on e op er at qu es t ion te N t es qu t re u pt inp ru T LT SE HA RE Set ut N ot e2 m PD784020, 784021 12. RESET FUNCTION Applying a low-level signal to the RESET pin initializes the internal hardware (reset status). When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC): * Eight low-order bits of the PC : Contents of location at address 0000H * Intermediate eight bits of the PC : Contents of location at address 0001H * Four high-order bits of the PC : 0 The PC contents are used as a branch destination address. Program execution starts from that address. Therefore, a reset start can be performed from an arbitrary address. The contents of each register can be set by software, as required. The RESET input circuit contains a noise eliminator to prevent malfunctions caused by noise. This noise eliminator is an analog delay sampling circuit. Fig. 12-1 Accepting a Reset Delay Delay Delay Initialize PC Execute instruction at reset start address RESET (input) Internal reset signal Start reset End reset For power-on reset, the RESET signal must be held active until the oscillation settling time (approximately 40 ms) has elapsed. Fig. 12-2 Power-On Reset Execute instruction at reset start address Oscillation settling time Delay Initialize PC VDD RESET (input) Internal reset signal End reset 53 m PD784020, 784021 13. INSTRUCTION SET (1) 8-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where A is described as r.) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 13-1 Instructions Implemented by 8-Bit Addressing 2nd operand #byte A r r' saddr saddr' sfr !addr16 !!addr24 mem [saddrp] [%saddrg] r3 PSWL PSWH MOV [WHL+] [WHL-] n NoneNote 2 1st operand A (MOV) ADD Note 1 (MOV) (XCH) MOV XCH (MOV)Note 6 MOV (XCH)Note 6 (XCH) (MOV) (XCH) MOV XCH (MOV) (XCH) (ADD)Note 1 ROR Note 3 MULU DIVUW INC DEC (ADD)Note 1 (ADD) Note 1 (ADD)Notes 1, 6 (ADD) Note 1 ADD Note 1 ADD Note 1 r MOV ADD Note 1 (MOV) (XCH) MOV XCH MOV XCH ADD Note 1 MOV XCH ADD Note 1 MOV XCH (ADD)Note 1 ADD Note 1 saddr MOV (MOV)Note 6 MOV MOV XCH ADD Note 1 INC DEC DBNZ PUSH POP CHKL CHKLA ADD Note 1 (ADD)Note 1 ADD Note 1 sfr MOV MOV MOV ADDNote 1 (ADD)Note 1 ADD Note 1 !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 MOV (MOV) ADD Note 1 MOV ADD Note 1 MOV ROR4 ROL4 r3 PSWL PSWH B, C STBC, WDM [TDE+] [TDE-] MOV MOV DBNZ MOV (MOV) (ADD)Note 1 MOVMNote 4 MOVBKNote 5 Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. There is no second operand, or the second operand is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. When saddr is saddr2 with this combination, an instruction with a short code exists. 54 m PD784020, 784021 (2) 16-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where AX is described as rp.) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 13-2 Instructions Implemented by 16-Bit Addressing NoneNote 2 2nd operand #word AX rp rp' saddrp saddrp' strp !addr16 !!addr24 mem [saddrp] [%saddrg] [WHL+] byte n 1st operand AX (MOVW) (MOVW) (MOVW) (XCHW) (MOVW)Note 3 MOVW (MOVW) XCHW MOVW XCHW (MOVW) (XCHW) ADDW Note 1 (XCHW) (XCHW) Note 3 (XCHW) (ADD)Note 1 (ADDW) Note 1 (ADDW)Notes 1,3 (ADDW) Note 1 rp MOVW (MOVW) MOVW XCHW MOVW XCHW MOVW XCHW MOVW SHRW SHLW MULWNote 4 INCW DECW INCW DECW ADDW Note 1 (XCHW) (ADDW)Note 1 ADDW Note 1 ADDWNote 1 ADDW Note 1 saddrp MOVW (MOVW)Note 3 MOVW MOVW ADDWNote 1 sfrp MOVW MOVW MOVW ADDW Note 1 (ADDW)Note 1 ADDW Note 1 XCHW PUSH POP MOVTBLW ADDW Note 1 (ADDW)Note 1 ADDW Note 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW MOVW (MOVW) MOVW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] byte (MOVW) SACW MACW MACSW Notes 1. SUBW and CMPW are the same as ADDW. 2. There is no second operand, or the second operand is not an operand address. 3. When saddrp is saddrp2 with this combination, an instruction with a short code exists. 4. MULUW and DIVUX are the same as MULW. 55 m PD784020, 784021 (3) 24-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where WHL is described as rg.) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 13-3 Instructions Implemented by 24-Bit Addressing 2nd operand 1st operand WHL (MOVG) (ADDG) (SUBG) rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) #imm24 WHL rg rg' (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg !!addr24 mem1 [%saddrg] SP MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] SP NoneNote Note There is no second operand, or the second operand is not an operand address. 56 m PD784020, 784021 (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 13-4 Bit Manipulation Instructions Implemented by Addressing 2nd operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit 1st operand CY !addr16.bit !!addr24.bit MOV1 AND1 OR1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BF BT BTCLR BFSET /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 OR1 NOT1 SET1 CLR1 NoneNote Note There is no second operand, or the second operand is not an operand address. 57 m PD784020, 784021 (5) Call/return instructions and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 13-5 Call/Return and Branch Instructions Implemented by Addressing Instruction address operand Basic instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None BCNote BR CALL BR CALL BR RETCS RETCSB CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLF BRKCS BRK RET RETI RETB Composite instruction BF BT BTCLR BFSET DBNZ Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT EI, DI, SWRS 58 m PD784020, 784021 14. ELECTRICAL CHARACTERISTICS H The electrical characteristics described in this chapter apply to the products which are improved versions of the mPD784020 and mPD784021 (other than K-rank products). For K-rank products yet to be improved (K-rank products), please consult with our sales offices. ABSOLUTE MAXIMUM RATINGS (TA = 25 C) Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage Output voltage Low-level output current VI VO IOL Each pin Total of all output pins High-level output current IOH Each pin Total of all output pins A/D converter reference input voltage D/A converter reference input voltage AVREF1 AVREF2 AVREF3 Operating ambient temperature Storage temperature TA Tstg Conditions Rating -0.5 to +7.0 AVSS to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 15 150 -10 -100 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA V V V C C Caution Absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. Be sure to use the product within the rated values. 59 m PD784020, 784021 OPERATING CONDITIONS * Operating ambient temperature (TA): -40 to +85 C * Rising and falling time (tr, tf) (for pins not especially specified): 0 to 200 ms * Power supply voltage and clock cycle time: See Fig. 14-1. Fig. 14-1 Relationship between Power Supply Voltage and Clock Cycle Time 10000 4000 Clock cycle time tCYK [ns] 1000 Operation guarantee range 125 100 80 10 0 1 2 3 4 5 6 7 Power supply voltage [V] CAPACITANCE (TA = 25 C, VDD = VSS = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz Conditions Min. Typ. Max. 10 10 10 Unit pF pF pF 0 V on pins other than measured pins 60 m PD784020, 784021 OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = 4.5 to 5.5 V, VSS = 0 V) Resonator Ceramic resonator or crystal Recommended circuit Parameter Oscillator frequency (fXX) Min. 4 Max. 25 Unit MHz VSS X1 X2 C1 C2 External clock X1 input frequency (fX) 4 25 MHz X1 X2 X1 input rising and falling times (tXR, tXF) 0 10 ns HCMOS Inverter X1 input high-level and lowlevel widths (tWXH, tWXL) 10 125 ns Caution When using the system clock generator, run wires in the portion surrounded by dotted lines according to the following rules to avoid effects such as stray capacitance: * * * * Minimize the wiring. Never cause the wires to cross other signal lines. Never cause the wires to run near a line carrying a large varying current. Cause the grounding point of the capacitor of the oscillator circuit to have the same potential as VSS. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator. 61 m PD784020, 784021 OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V, VSS = 0 V) Resonator Ceramic resonator or crystal Recommended circuit Parameter Oscillator frequency (fXX) Min. 4 Max. 16 Unit MHz VSS X1 X2 C1 C2 External clock X1 input frequency (fX) 4 16 MHz X1 X2 X1 input rising and falling times (tXR, tXF) HCMOS Inverter 0 10 ns X1 input high-level and lowlevel widths (tWXH, tWXL) 10 125 ns Caution When using the system clock generator, run wires in the portion surrounded by dotted lines according to the following rules to avoid effects such as stray capacitance: * * * * Minimize the wiring. Never cause the wires to cross other signal lines. Never cause the wires to run near a line carrying a large varying current. Cause the grounding point of the capacitor of the oscillator circuit to have the same potential as VSS. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator. 62 m PD784020, 784021 DC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2) Parameter Low-level input voltage Symbol VIL1 Conditions Pins other than those described in Notes 1, 2, 3, and 4 Pins described in Notes 1, 2, 3, and 4 VDD = +5.0 V 10 % Pins described in Notes 2, 3, and 4 High-level input voltage VIH1 VIH2 VIH3 Pins other than those described in Note 1 Pins described in Note 1 VDD = +5.0 V 10 % Pins described in Notes 2, 3, and 4 Low-level output voltage VOL1 VOL2 IOL = 2 mA VDD = +5.0 V 10 % IOL = 8 mA Pins described in Notes 2 and 5 High-level output voltage VOH1 VOH2 IOH = -2 mA VDD = +5.0 V 10 % IOH = -5 mA Pins described in Note 4 X1 low-level input current X1 high-level input current IIL IIH 0 V VI VIL2 VIH2 VI VDD -30 +30 VDD - 1.0 2.0 V V 0.4 1.0 V V 0.7VDD 0.8VDD 2.2 VDD + 0.3 VDD + 0.3 VDD + 0.3 V V V Min. -0.3 Typ. Max. 0.3VDD Unit V VIL2 VIL3 -0.3 -0.3 0.2VDD +0.8 V V mA mA Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P13/RxD2/SI2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P30/RxD/SI1, P32/SCK0, P33/SO0/SB0, and TEST 2. AD0 to AD7 and A8 to A15 3. P60/A16 to P63/A19, RD, WR, P66/WAIT/HLDRQ, and P67/REFRQ/HLDAK 4. P00 to P07 5. P10 to P17 63 m PD784020, 784021 DC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2) Parameter Input leakage current Symbol ILI 0 V VI VDD Except for the X1 pin when EXTC = 0 0 V VI VDD Analog input pins Output leakage current VDD supply current ILO IDD1 0 V VO VDD Operating mode fXX = 25 MHz fXX = 16 MHz VDD = 2.7 to 5.5 V IDD2 HALT mode fXX = 25 MHz fXX = 16 MHz VDD = 2.7 to 5.5 V IDD3 IDLE mode (EXTC = 0) fXX = 25 MHz fXX = 16 MHz VDD = 2.7 to 5.5 V Pull-up resistance RL VI = 0 V VDD = +5.0 V 10 % VI = 0 V VDD = 2.7 to 4.5 V 15 160 kW 15 100 kW 12 8 mA mA 22 8 30 12 mA mA 40 12 10 60 25 3 Conditions Min. Typ. Max. 10 Unit mA mA mA mA mA 64 m PD784020, 784021 AC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2) Parameter Address setup time Symbol tSAST Conditions VDD = +5.0 V 10 % Min. (0.5 + a) T - 11 (0.5 + a) T - 15 ASTB high-level width tWSTH VDD = +5.0 V 10 % (0.5 + a) T - 17 (0.5 + a) T - 40 Address hold time (referred to ASTBO) Address hold time (referred to RD*) Address AE RDO delay time tDAR VDD = +5.0 V 10 % (1 + a) T - 5 (1 + a) T - 10 Address float time (referred to RDO) Address AE data input time tDAID VDD = +5.0 V 10 % (2.5 + a + n) T - 37 (2.5 + a + n) T - 52 ASTBO AE data input time tDSTID VDD = +5.0 V 10 % (2 + n) T - 40 (2 + n) T - 60 RDO AE data input time tDRID VDD = +5.0 V 10 % (1.5 + n) T - 50 (1.5 + n) T - 70 ASTBO AE RDO delay time Data hold time (referred to RD*) RD* AE address active time tDRA Upon program read Upon data read VDD = +5.0 V 10 % VDD = +5.0 V 10 % 0.5T - 2 0.5T - 12 1.5T - 2 1.5T - 12 RD* AE ASTB* delay time RD low-level width tDRST tWRL VDD = +5.0 V 10 % 0.5T - 9 (1.5 + n) T - 30 (1.5 + n) T - 40 Address hold time (referred to WR*) Address AE WRO delay time tDAW VDD = +5.0 V 10 % (1 + a) T - 5 (1 + a) T - 10 ASTBO AE data output delay time tDSTOD VDD = +5.0 V 10 % 0.5T + 15 0.5T + 20 ASTBO AE data output time ASTBO AE WRO output delay time tDWOD tDSTW 0.5T - 9 0.5T - 11 ns ns ns ns ns ns tHWA 0.5T - 14 ns ns ns ns ns ns ns ns tDSTR tHRID 0.5T - 9 0 ns ns ns ns ns ns ns ns tFRA 0 ns ns ns tHRA tHSTLA VDD = +5.0 V 10 % 0.5T - 24 0.5T - 34 0.5T - 14 Max. Unit ns ns ns ns ns ns ns Remark T: TCYK (system clock cycle time) a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n * 0) 65 m PD784020, 784021 (1) Read/write operation (2/2) Parameter Data setup time (referred to WR*) Data hold time (referred to WR*)Note WR* AE ASTB* delay time WR low-level width tDWST tWWL VDD = +5.0 V 10 % tHWOD VDD = +5.0 V 10 % Symbol tSODW Conditions VDD = +5.0 V 10 % Min. (1.5 + n) T - 30 (1.5 + n) T - 40 0.5T - 5 0.5T - 14 0.5T - 9 (1.5 + n) T - 30 (1.5 + n) T - 40 Max. Unit ns ns ns ns ns ns ns Note The hold time includes the time for holding VOH1 and VOL1 on the load conditions of CL = 50 pF and RL = 4.7 kW. Remark T: TCYK (system clock cycle time) n: number of wait cycles (n * 0) (2) Bus hold timing Parameter HLDRQ* AE float delay time HLDRQ* AE HLDAK* delay time Symbol tFHQC tDHQHHAH VDD = +5.0 V 10 % Conditions Min. Max. (6 + a + n) T + 50 (7 + a + n) T + 30 (7 + a + n) T + 40 Float AE HLDAK* delay time HLDRQO AE HLDAKO delay time tDCFHA tDHQLHAL VDD = +5.0 V 10 % 1T + 30 2T + 40 2T + 60 HLDAKO AE active delay time tDHAC VDD = +5.0 V 10 % 1T - 20 1T - 30 Unit ns ns ns ns ns ns ns ns Remark T: TCYK (system clock cycle time) a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n * 0) 66 m PD784020, 784021 (3) External wait timing Parameter Address AE WAITO input time Symbol tDAWT Conditions VDD = +5.0 V 10 % Min. Max. (2 + a) T - 40 (2 + a) T - 60 ASTBO AE WAITO input time tDSTWT VDD = +5.0 V 10 % 1.5T - 40 1.5T - 60 ASTBO AE WAIT hold time tHSTWTH VDD = +5.0 V 10 % (0.5 + n) T + 5 (0.5 + n) T + 10 ASTBO AE WAIT* delay time tDSTWTH VDD = +5.0 V 10 % (1.5 + n) T - 40 (1.5 + n) T - 60 RDO AE WAITO input time tDRWTL VDD = +5.0 V 10 % T - 50 T - 70 RDO AE WAITO hold time tHRWT VDD = +5.0 V 10 % nT + 5 nT + 10 RDO AE WAIT* delay time tDRWTH VDD = +5.0 V 10 % (1 + n) T - 40 (1 + n) T - 60 WAIT* AE data input time tDWTID VDD = +5.0 V 10 % 0.5T - 5 0.5T - 10 WAIT* AE WR* delay time WAIT* AE RD* delay time WRO AE WAITO input time tDWTW tDWTR tDWWTL VDD = +5.0 V 10 % 0.5T 0.5T T - 50 T - 75 WRO AE WAIT hold time tHWWT VDD = +5.0 V 10 % nT + 5 nT + 10 WRO AE WAIT* delay time tDWWTH VDD = +5.0 V 10 % (1 + n) T - 40 (1 + n) T - 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remark T: TCYK (system clock cycle time) a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n * 0) (4) Refresh timing Parameter Random read/write cycle time REFRQ low-level pulse width Symbol tRC tWRFQL VDD = +5.0 V 10 % Conditions Min. 3T 1.5T - 25 1.5T - 30 ASTBO AE REFRQ delay time RD* AE REFRQ delay time WR* AE REFRQ delay time REFRQ* AE ASTB delay time REFRQ high-level pulse width tDSTRFQ tDRRFQ tDWRFQ tDRFQST tWRFQH VDD = +5.0 V 10 % 0.5T - 9 1.5T - 9 1.5T - 9 0.5T - 9 1.5T - 25 1.5T - 30 Max. Unit ns ns ns ns ns ns ns ns ns Remark T: TCYK (system clock cycle time) 67 m PD784020, 784021 SERIAL OPERATION (CSI) Parameter Serial clock cycle time (SCK0) Output Serial clock low-level width (SCK0) Output Serial clock high-level width (SCK0) Output SI0, SB0 setup time (referred to SCK0*) SI0, SB0 hold time (referred to SCK0*) SO0, SB0 output delay time (referred to SCK0O) tDSBSK2 tDSBSK1 CMOS push-pull output (three-wire serial I/O mode) Open-drain output (SBI mode), RL = 1 kW SO0, SB0 output hold time (referred to SCK0*) SB0 high hold time (referred to SCK0*) SB0 low setup time (referred to SCK0O) SB0 low-level width SB0 high-level width tWSBL tWSBH 4 4 tCYX tCYX tSSBSK 4 tCYX tHSBSK2 SBI mode 4 tCYX tHSBSK1 During data transfer 0.5TCYSK0 - 40 ns 0 400 ns 0 150 ns tHSSK0 80 ns tSSSK0 tWSKH0 Input VDD = +5.0 V 10 % tWSKL0 Input VDD = +5.0 V 10 % Symbol tCYSK0 Input Conditions VDD = +5.0 V 10 % Min. 500 1000 T 210 460 0.5T - 40 210 460 0.5T - 40 80 Max. Unit ns ns ns ns ns ns ns ns ns ns Remarks 1. The values listed in the above table are obtained when fXX = 25 MHz and CL = 100 pF. 2. tCYX = 1/fXX 3. T: Serial clock frequency specified using software. The minimum value is 16/fXX. 68 m PD784020, 784021 SERIAL OPERATION (IOE1, IOE2) Parameter Serial clock cycle time (SCK1, SCK2) Output Serial clock low-level width (SCK1, SCK2) Output Serial clock high-level width (SCK1, SCK2) Output SI1, SI2 setup time (referred to SCK1, SCK2*) SI1, SI2 hold time (referred to SCK1, SCK2*) SO1, SO2 output delay time (referred to SCK1, SCK2O) SO1, SO2 output hold time (referred to SCK1, SCK2*) tHSOSK During data transfer 0.5TCYSK1 - 40 ns tDSOSK 0 50 ns tHSSK1 40 ns tSSSK1 Internal clock divided by 16 tWSKH1 Input Internal clock divided by 16 VDD = +5.0 V 10 % tWSKL1 Input Internal clock divided by 16 VDD = +5.0 V 10 % Symbol tCYSK1 Input Conditions VDD = +5.0 V 10 % Min. 250 500 T 85 210 0.5T - 40 85 210 0.5T - 40 40 Max. Unit ns ns ns ns ns ns ns ns ns ns Remarks 1. The values listed in the above table are obtained when CL = 100 pF. 2. T: Serial clock frequency specified using software. The minimum value is 16/fXX. SERIAL OPERATION (UART, UART2) Parameter ASCK clock input cycle time Symbol tCYASK Conditions VDD = +5.0 V 10 % Min. 125 250 ASCK clock low-level width tWASKL VDD = +5.0 V 10 % 52.5 85 ASCK clock high-level width tWASKH VDD = +5.0 V 10 % 52.5 85 Max. Unit ns ns ns ns ns ns 69 m PD784020, 784021 OTHER OPERATIONS Parameter NMI low-level width NMI high-level width INTP0 low-level width INTP0 high-level width INTP1-INTP3 and CI lowlevel width INTP1-INTP3 and CI highlevel width INTP4 and INTP5 low-level width INTP4 and INTP5 high-level width RESET low-level width RESET high-level width Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L Conditions Min. 10 10 3tCYSMP + 10 3tCYSMP + 10 3tCYCPU + 10 Max. Unit ms ms ns ns ns tWIT1H 3tCYCPU + 10 ns tWIT2L 10 ms ms ms ms tWIT2H 10 tWRSL tWRSH 10 10 Remark tCYSMP: sampling clock specified using software tCYCPU: CPU operating clock specified using CPU software A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = 3.4 to 5.5 V, +3.4 V AVREF1 AVDD, VSS = AVSS = 0 V) Parameter Resolution Total errorNote VDD = AVDD = +5.0 V 10 % +3.4 V AVREF1 AVDD +2.7 V VDD = AVDD +3.3 V +2.5 V AVREF1 AVDD Linearity calibrationNote Quantization error Conversion time tCONV tCYK 500 ns, FR = 1 tCYK 500 ns, FR = 0 Sampling time tSAMP tCYK 500 ns, FR = 1 tCYK 500 ns, FR = 0 Analog input voltage Analog input impedance AVREF1 current AVDD supply current VIAN RAN AIREF1 AIDD1 AIDD2 fXX = 25 MHz STOP mode, CS = 0 120 180 24 36 -0.3 1000 0.5 2.0 1.5 5.0 20 AVREF1 + 0.3 0.6 1/2 % LSB tCYK tCYK tCYK tCYK V MW mA mA 1.0 % Symbol Conditions Min. 8 1.2 1.0 Typ. Max. Unit bit % % mA Note Quantization error is excluded. The error is represented in percent with respect to a full-scale value. Remark tCYK: system clock cycle time 70 m PD784020, 784021 D/A CONVERTER CHARACTERISTICS (TA = -40 to +85 C, AVREF2 = VDD = AVDD = 2.7 to 5.5 V, AVREF3 = VSS = AVSS = 0 V) Parameter Resolution Total errorNote Load condition: 4 MW, 30 pF VDD = 4.5 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD AVREF2 = 0.75VDD AVREF3 = 0.25VDD Load condition: 2 MW, 30 pF VDD = 4.5 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD AVREF2 = 0.75VDD AVREF3 = 0.25VDD Settling time Output resistance Analog reference voltage RO AVREF2 AVREF3 Reference supply input current AIREF2 AIREF3 Load condition: 2 MW, 30 pF Note Symbol Conditions Min. 8 Typ. Max. Unit bit VDD = 4.5 to 5.5 V 0.4 0.6 0.6 % % % 0.8 % VDD = 4.5 to 5.5 V 0.6 0.8 0.8 % % % 1.0 % 10 20 0.75VDD 0 0 -5 VDD 0.25VDD 5 0 ms kW V V mA mA Note DACS0, DACS1 = 7FH 71 m PD784020, 784021 DATA RETENTION CHARACTERISTICS (TA = -40 to +85 C) Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR = 2.5 to 5.5 VNote 1 VDDDR = 2.5 V Note 1 VDD rising time VDD falling time VDD retention time (referred to STOP mode setting) STOP release signal input time Oscillation settling time tDREL tWAIT Crystal Ceramic resonator Low-level input voltage High-level input voltage VIL VIH Specified pinsNote 2 0 30 5 0 0.9VDDDR 0.1VDDDR VDDDR ms ms ms V V tRVD tFVD tHVD 200 200 0 Conditions Min. 2.5 10 2 Typ. Max. 5.5 50 10 Unit V mA mA ms ms ms Notes 1. When the input voltage for the pins described in Note 2 satisfies the VIL and VIH conditions in the above table 2. Pins RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, and P33/SO0/SB0 AC Timing Test Points VDD - 1 V 0.8VDD or 2.2 V Test points 0.8 V 0.8VDD or 2.2 V 0.8 V 0.45 V 72 m PD784020, 784021 Timing Waveform (1) Read operation tWSTH ASTB tSAST tHSTLA A8-A19 tDAID tHRA tDSTID tDRST AD0-AD7 tDSTR tDAR RD tFRA tDRID tHRID tDRA tWRL (2) Write operation tWSTH ASTB tSAST tHSTLA A8-A19 tHWA AD0-AD7 tDSTW tDAW WR tDWOD tDSODW tHWOD tDSTOD tDWST tWWL 73 m PD784020, 784021 Hold Timing ASTB, A8-A19, AD0-AD7, RD, WR tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC External WAIT Signal Input Timing (1) Read operation ASTB tDSTWTH tHSTWTH tDSTWT A8-A19 AD0-AD7 tDAWT RD tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID (2) Write operation ASTB tDSTWTH tHSTWTH tDSTWT A8-A19 AD0-AD7 tDAWT WR tDWWTL WAIT tHWWT tDWWTH tDWTW 74 m PD784020, 784021 Timing Waveform for Refresh (1) Random read/write cycle tRC ASTB WR tRC RD tRC tRC tRC (2) When a refresh is performed simultaneously with a memory access ASTB RD, WR tDSTRFQ tDRFQST tWRFQH REFRQ tWRFQL (3) Refresh after reading ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL (4) Refresh after writing ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL 75 m PD784020, 784021 Serial Operation (CSI) (1) Three-wire serial I/O mode tWSKL0 SCK tSSSK0 tHSSK0 tWSKH0 tCYSK0 SI tDSBSK1 SO tHSBSK1 Input data Output data (2) SBI mode Y Bus release signal transfer SCK tHSBSK2 SB0 tWSBL tWSBH tSSBSK Y Command signal transfer tWSKL0 SCK tHSBSK2 SB0 tSSBSK tCYSK0 tDSBSK2 tSSSK0 tHSSK0 tHSBSK1 tWSKH0 Input/Output data 76 m PD784020, 784021 Serial Operation (IOE1, IOE2) tWSKL1 SCK tCYSK1 SI tDSOSK SO tHSOSK tSSSK1 tHSSK1 tWSKH1 Input data Output data Serial Operation (UART, UART2) tWASKH tWASKL ASCK, ASCK2 0.8VDD 0.8 V tCYASK 77 m PD784020, 784021 Interrupt Input Timing tWNIH 0.8VDD 0.8 V tWNIL NMI tWIT0H 0.8VDD INTP0 0.8 V tWIT0L tWIT1H 0.8VDD 0.8 V tWIT1L CI, INTP1-INTP3 tWIT2H 0.8VDD INTP4, INTP5 0.8 V tWIT2L Reset Input Timing tWRSH 0.8VDD RESET 0.8 V tWRSL 78 m PD784020, 784021 External Clock Timing tWXH 0.8VDD X1 0.8 V tXR tXF tWXL tCYX Data Retention Timing Set STOP mode. VDD tHVD tFVD VDDDR tRVD tDREL tWAIT RESET 0.8VDD 0.8 V NMI (Released by a falling edge) 0.8VDD 0.8 V 0.8VDD NMI (Released by a rising edge) 0.8 V 79 m PD784020, 784021 15. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end CD S Q R 80 1 21 20 F G H P I M J K M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX. INCHES 0.6770.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. S80GC-65-3B9-4 Remark The shape and material of the ES version are the same as those of the corresponding mass-produced products. 80 m PD784020, 784021 80 PIN PLASTIC TQFP (FINE PITCH) ( A B 12) H 60 61 41 40 detail of lead end C D S Q 80 21 1 20 F G H I M J K P N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.05 0.050.05 55 1.27 MAX. INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.041 0.0020.002 55 0.050 MAX. P80GK-50-BE9-4 Remark The shape and material of the ES version are the same as those of the corresponding mass-produced products. M R 81 m PD784020, 784021 H 16. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the mPD784021. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 16-1 Soldering Conditions for Surface-Mount Devices (1) mPD784020GC-3B9 : 80-pin plastic QFP (14 14 mm) mPD784021GC-3B9 : 80-pin plastic QFP (14 14 mm) Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 1/2C Reflow time: 30 seconds or less (at 210 1/2C or more) Maximum allowable number of reflow processes: 3 Peak package's surface temperature: 215 1/2C Reflow time: 40 seconds or less (at 210 1/2C or more) Maximum allowable number of reflow processes: 3 Solder temperature: 260 1/2C or less Flow time: 10 seconds or less Number of flow process: 1 Preheating temperature: 120 1/2C max. (measured on the package surface) Terminal temperature: 300 1/2C or less Flow time: 3 seconds or less (for each side of device) Symbol IR35-00-3 VPS VP15-00-3 Wave soldering WS60-00-1 Partial heating method - (2) mPD784021GK-BE9: 80-pin plastic TQFP (fine pitch) (12 12 mm) Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 1/2C Reflow time: 30 seconds or less (at 210 1/2C or more) Maximum allowable number of reflow processes: 2 Exposure limitNote: 7 days (10 hours of pre-baking is required at 125 1/2C afterward.) Partial heating method - Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: Temperature of 25 1/2C and maximum relative humidity at 65 % or less Caution Do not apply more than a single process at once, except for "Partial heating method." 82 m PD784020, 784021 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for system development using the mPD784021. Language Processing Software RA78K4Note 1 CC78K4Note 1 CC78K4-LNote 1 Assembler package for all 78K/IV series models C compiler package for all 78K/IV series models C compiler library source file for all 78K/IV series models PROM Write Tools PG-1500 PA-78P4026GC PA-78P4038GK PA-78P4026KK PG-1500 controllerNote 2 PROM programmer Programmer adaptor, connects to PG-1500 Control program for PG-1500 Debugging Tools IE-784000-R IE-784000-R-BK IE-784026-R-EM1 IE-784000-R-EM IE-70000-98-IF-B IE-70000-98N-IF IE-70000-PC-IF-B IE-78000-R-SV3 EP-78230GC-R EP-78054GK-R EV-9200GC-80 In-circuit emulator for all mPD784026 sub-series models Break board for all 78K/IV series models Emulation board for evaluating mPD784026 sub-series models Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine Interface adapter and cable when a PC-9800 series notebook is used as the host machine Interface adapter when the IBM PC/ATTM is used as the host machine Interface adapter and cable when the EWS is used as the host machine Emulation probe for 80-pin plastic QFP (14 14 mm) for all mPD784026 sub-series Emulation probe for 80-pin plastic TQFP (fine pitch) (12 12 mm) for all mPD784021 Socket for mounting on target system board made for 80-pin plastic QFP (14 14 mm) Adapter for mounting on target system board made for 80-pin plastic TQFP (fine pitch) (12 12 mm) Tool used to remove the mPD78P4026KK-T from the EV-9200GC-80 System simulator for all 78K/IV series models Integrated debugger for IE-784000-R Device file for all mPD784026 sub-series models EV-9500GK-80 EV-9900 SM78K4Note 3 ID78K4Note 3 DF784026Note 4 Real-time OS RX78K/IVNote 4 MX78K4Note 2 Real-time OS for 78K/IV series models OS for all 78K/IV series models Remark The RA78K4, CC78K4, SM78K4, and ID78K4 are used with the DF784026. 83 m PD784020, 784021 Notes 1. * Based on PC-9800 series (MS-DOSTM) * Based on IBM PC/AT and compatibles (PC DOSTM, WindowsTM, MS-DOS, and IBM DOSTM) * Based on HP9000 series 700TM (HP-UXTM) * Based on SPARCstationTM (SunOSTM) * Based on NEWSTM (NEWS-OSTM) 2. * Based on PC-9800 series (MS-DOS) * Based on IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, and IBM DOS) 3. * Based on PC-9800 series (MS-DOS + Windows) * Based on IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, and IBM DOS) * Based on HP9000 series 700 (HP-UX) * Based on SPARCstation (SunOS) 4. * Based on PC-9800 series (MS-DOS) * Based on IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, and IBM DOS) * Based on HP9000 series 700 (HP-UX) * Based on SPARCstation (SunOS) 84 m PD784020, 784021 APPENDIX B RELATED DOCUMENTS Documents Related to Devices Document No. Document name Japanese English This manual IP-3230 IP3231 U10898E -- -- mPD784020, 784021 Data Sheet mPD784025, 784026 Data Sheet mPD78P4026 Data Sheet mPD784026 Sub-Series User's Manual, Hardware mPD784026 Sub-Series Special Function Registers mPD784026 Sub-Series Application Note, Hardware Basic 78K/IV Series User's Manual, Instruction 78K/IV Series Instruction Summary Sheet 78K/IV Series Instruction Set 78K/IV Series Application Note, Software Basic U11514J To be released soon To be released soon U10898J U10593J U10573J U10905J U10594J U10595J U10095J IEU-1386 -- -- -- Documents Related to Development Tools (User's Manual) Document No. Document name Japanese RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation Language CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Base PG-1500 Controller IBM PC Series (PC DOS) Base IE-784000-R IE-784026-R-EM1 EP-78230 EP-78054GK-R SM78K4 System Simulator Windows Base SM78K Series System Simulator Reference External Parts User Open Interface Specifications Reference EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-777 EEU-651 EEU-704 EEU-5008 EEU-5004 EEU-5017 EEU-985 EEU-932 U10093J U10092J English EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 -- EEU-1335 EEU-1291 U10540E EEU-1534 EEU-1528 EEU-1515 EEU-1468 U10093E U10092E ID78K4 Integrated Debugger U10440J U10440E Caution The above documents may be revised without notice. Use the latest versions when you design application systems. 85 m PD784020, 784021 Documents Related to Software to Be Incorporated into the Product (User's Manual) Document No. Document name Japanese 78K/IV Series Real-Time OS Basic Installation Debugger OS for 78K/IV Series MX78K4 U10603J U10604J U10364J To be created English -- -- -- -- Other Documents Document No. Document name Japanese IC PACKAGE MANUAL SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Device Guide for Products Related to Micro-Computer: Other Companies C10535J IEI-620 C10983J MEM-539 MEI-603 MEI-604 C10943X C10535E IEI-1209 C10983E -- MEI-1202 -- English Caution The above documents may be revised without notice. Use the latest versions when you design application systems. 86 m PD784020, 784021 [MEMO] 87 m PD784020, 784021 Cautions on CMOS Devices Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. 88 m PD784020, 784021 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 3 89 m PD784020, 784021 Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94. 11 90 |
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