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| DATA SHEET MOS INTEGRATED CIRCUIT PD78323,78324 16/8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD78324 is a 16/8-bit single-chip microcontroller that incorporates a high-performance 16-bit CPU. The PD78324 is one of 78K/III series. The internal capacity is significantly increased compared with the conventional PD78322. A realtime pulse unit for realtime pulse control required in motor control, an A/D converter, a ROM, and a RAM have been integrated into one chip. The PD78324 incorporates 32K-byte mask ROM and 1024-byte RAM. The PD78323 is a ROM-less version of the PD78324. Also, It is provided the PD78P324 as an on-chip PROM product. Detailed information about product features and specifications can be found in the following document. PD78322 User's Manual : IEU-1248 FEATURES * Internal 16-bit architecture and external 8-bit data bus * High-speed processing by pipeline control and instruction prefetch * Minimum instruction execution time: 250 ns (with 16 MHz external clock in operation) * Instruction set suitable for control operations (PD78312 upward compatible) * Multiply/divide instructions (16 bits x 16 bits, 32 bits / 16 bits) * Bit manipulation instruction * String instruction, etc. * On-chip high-function interrupt controller * 3-level priority specifiable * 3-type interrupt processing mode selectable (Vectored interrupt function, context switching function, and macro service function) * Variety of peripheral hardware * Realtime pulse unit * 8-channel, 10-bit A/D converter * Watchdog timer * Powerful serial interface (with an on-chip dedicated baud rate generator) * UART * SBI (NEC Standard Serial Bus Interface) * 3-wire serial I/O ***** 1 channel ***** 1 channel APPLICATIONS * Motor control devices Unless there are any particular diferences, the PD78324 is described as the representative model in this document. The information in this document is subject to change without notice. Document No. U10456EJ4V0DS00 (4th edition) (Previous No. IC-2870) Date Published November 1995 P Printed in Japan The mark shows major revised points. (c) 1991 PD78323, 78324 ORDERING INFORMATION Part Number Package 74-pin 68-pin 74-pin 68-pin plastic plastic plastic plastic QFP (20 x 20 mm) QFJ ( 950 mil) QFP (20 x 20 mm) QFJ ( 950 mil) On-chip ROM None None Mask ROM Mask ROM PD78323GJ-5BJ PD78323LP PD78324GJ-x x x-5BJ PD78324LP-x x x Remark x x x Indicates ROM code number. 2 PD78323, 78324 PIN CONFIGURATION * 74-pin plastic QFP (20 x 20 mm) PD78323GJ-5BJ PD78324GJ-xxx-5BJ P07/RTP7 P06/RTP6 P05/RTP5 P04/RTP4 P03/RTP3 P02/RTP2 P01/RTP1 P93/TMD P42/AD2 P41/AD1 P40/AD0 P92/TAS P91/WR P90/RD ASTB VSS 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 NC P56/A14 P57/A15 VDD AVSS P70/AN0 P71/AN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 P00/RTP0 WDTO VSS NC X1 X2 RESET P85/TO11 P84/TO10 P83/TO03 P82/TO02 P81/TO01 P80/TO00 NC P34/SCK P33/SI/SB1 P32/SO/SB0 P31/RXD P30/TXD NC P27/INTP6/TI P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P25/INTP4 P26/INTP5 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 Caution The NC pin should be connected to VSS for noise control (can also be left open). P20/NMI AVREF AVDD VDD NC NC EA 3 PD78323, 78324 * 68-pin plastic QFJ ( PD78323LP PD78324LP-xxx 950 mil) P27/INTP6/TI P26/INTP5 P25/INTP4 P24/INTP3 P23/INTP2 P22/INTP1 P21/INTP0 P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 P72/AN2 P20/NMI AVREF AVDD VSS P30/TXD P31/RXD P32/SO/SB0 P33/SI/SB1 P34/SCK P80/TO00 P81/TO01 P82/TO02 P83/TO03 P84/TO10 P85/TO11 RESET X2 X1 VSS WDTO RTP0/P00 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P71/AN1 P70/AN0 AVSS VDD P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P92/TAS P93/TMD P91/WR P90/RD ASTB P40/AD0 P41/AD1 RTP1/P01 RTP2/P02 RTP3/P03 RTP4/P04 RTP5/P05 RTP6/P06 RTP7/P07 4 P42/AD2 VSS EA PD78323, 78324 P00 to P07 P20 to P27 P30 to P34 P40 to P47 P50 to P57 P70 to P77 P80 to P85 P90 to P93 NMI INTP0 to INTP6 RTP0 to RTP7 TI TXD RXD SB0/SO SB1/SI SCK TO00 to TO03 TO10 to TO11 : : : : : : : : : : : : : : : : : : : Port0 Port2 Port3 Port4 Port5 Port7 Port8 Port9 Nonmaskable Interrupt Interrupt From Peripherals Realtime Port Timer Input Transmit Data Receive Data Serial Bus/Serial Output Serial Bus/Serial Input Serial Clock Timer Output RESET X1, X2 WDTO EA TMD TAS WR RD ASTB AD0 to AD7 A8 to A15 AN0 to AN7 AVREF AVSS AVDD VDD VSS NC : : : : : : : : : : : : : : : : : : Reset Crystal Watchdog Timer Output External Access Turbo Mode Turbo Access Strobe Write Strobe Read Strobe Address Strobe Address/Data Bus Address Bus Analog Input Analog Reference Voltage Analog VSS Analog VDD Power Supply Ground Non-connection 5 PD78323, 78324 GENERAL DESCRIPTION OF FUNCTIONS Basic instructions Minimum instruction execution time 111 250 ns (with 16 MHz external clock in operation) * ROM : 32K bytes (PD78324) None (PD78323) * RAM : 1K bytes 64K bytes 8 bits x 16 x 8 banks (memory mapping) * Input port : 16 (dual-function as analog input: 8) * Input/output port : 39 (PD78324) 21 (PD78323) * * * * * * 18/16-bit free running timer x 1 16-bit timer/event counter x 1 16-bit compare register x 6 18-bit capture register x 4 18-bit capture/compare register x 2 Realtime output port x 8 Internal memory Memory space General registers I/O line Real-time pulse unit Serial communication interface A/D converter Serial interface with a dedicated baud rate generator * UART : 1 channel * SBI (NEC Serial Bus Interface) : 1 channel 10-bit resolution (8 analog inputs) * External : 8, internal : 14 (dual-function as external : 2) * 3 processing modes (vectored interrupt function, context switching function, and macro service function) Internal : 1 STOP mode/HALT mode 16-bit transfer/operation instruction, multiplication/division instruction (16 x 16, 32 / 16), bit manipulation instruction, string instruction, etc. On-chip watchdog timer * 68-pin plastic QFJ ( 950 mil) * 74-pin plastic QFP (20 x 20 mm) Interrupt Test factor Standby Instruction set Others Package 6 PD78323, 78324 DIFFERENCES BETWEEN PD78324 AND 78323 Product Name Item Internal ROM Input I/O line Input /output PD78324 32K bytes 16 (dual-function as analog input: 8) 39 Specifiable as I/O as an 8-bit unit. Functions as multiplexed address/data buses (AD0 to AD7) in the external memory expansion mode. Specifiable as I/O bit-wise. Functions as address bus (A8 to A15) in the external memory expansion mode. Specifiable as I/O bit-wise. In the external memory expansion mode, P90 and P91 function as RD strobe signal output and WR strobe signal output, respectively. In the external memory high-speed fetch mode, P92 P93 function as TAS output and TMD output respectively. Port 4 I/O mode is set as an 8-bit unit . Port 5 I/O mode is set bit-wise. PD78323 None 21 Port 4 (P40 to P47) Functions always as multiplexed address/data buses. Port 5 (P50 to P57) Functions always as address bus. Port 9 (P90 to P93) Always P90 and P91 function as RD strobe and WR strobe signal output, respectively. Memory expansion mode register (MM) Port 5 mode register (PM5) In the PD78324 emulation mode, turbo acces acces manager (PD71P301)Note PA and PB pins are controlled as port 4 and port 5 emulation pins. Note Maintenance product 7 8 EXU Main RAM (P20) NMI PROGRAMMABLE INTERRUPT CONTROLLER GENERAL REGISTERS 128 bytes & DATA MEMORY 128 bytes X2 RESET ALU ROM 32K bytes Note BLOCK DIAGRAM ROM/RAM BCU X1 INTP0-INTP5 (P21-P26) ASTB SYSTEM CONTROL & BUS CONTROL & PREFETCH CONTROL RD (P90) WR (P91) TAS (P92) TMD (P93) EA A8-A15 (P50-P57) AD0-AD7 (P40-P47) (P80) TO00 (P81) TO01 (P82) TO02 (P83) TO03 (P84) TO10 (P85) TO11 (P27) TI/INTP6 Peripheral RAM 768 bytes TIMER/COUNTER UNIT (REALTIME PULSE UNIT) MICRO SEQUENCE CONTROL MICRO ROM. (P34) SCK (P32) SO/SB0 (P33) SI/SB1 (P30) TXD (P31) RXD SERIAL INTERFACE (SBI) (UART) A/D CONVERTER (10 BIT) VDD VSS WDT PORT P90-P93 P80-P85 P70-P77 P50-P57 P40-P47 P30-P34 P20-P27 P00-P07 (REALTIME PORT) AN0-AN7 (P70-P77) AVDD AVSS AVREF WDTO PD78323, 78324 Note The PD78323 does not incorporate ROM. PD78323, 78324 CONTENTS 1. LIST OF PIN FUNCTIONS ..................................................................................................................... 11 1.1 1.2 1.3 PORT PINS ...................................................................................................................................................... 11 PINS OTHER THAN PORTS .......................................................................................................................... 12 PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ................... 14 2. CPU ARCHITECTURE ............................................................................................................................ 16 2.1 2.2 MEMORY SPACE ............................................................................................................................................ 16 PROCESSOR REGISTERS ............................................................................................................................ 19 2.2.1 2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.3.3 Control Registers ........................................................................................................................... 20 General Registers ........................................................................................................................... 22 Special Function Registers (SFR) ................................................................................................ 24 General Register Addressing ....................................................................................................... 29 Short Direct Addressing ................................................................................................................ 29 Special Function Register (SFR) Addressing ............................................................................ 29 DATA MEMORY ADDRESSING ..................................................................................................................... 29 3. BLOCK FUNCTIONS .............................................................................................................................. 30 3.1 3.2 3.3 3.4 3.5 3.6 3.7 BUS CONTROL UNIT (BCU) .......................................................................................................................... 30 EXECUTION UNIT (EXU) ................................................................................................................................ 30 ROM/RAM ........................................................................................................................................................ 30 INTERRUPT CONTROLLER .......................................................................................................................... 30 PORT FUNCTIONS ......................................................................................................................................... 31 CLOCK GENERATOR .................................................................................................................................... 32 REALTIME PULSE UNIT (RPU) ..................................................................................................................... 34 3.7.1 3.7.2 3.8 3.9 Configuration .................................................................................................................................. 34 Realtime Output Function ............................................................................................................. 36 A/D CONVERTER ........................................................................................................................................... 37 SERIAL INTERFACE ...................................................................................................................................... 37 3.10 WATCHDOG TIMER ....................................................................................................................................... 40 4. INTERRUPT FUNCTIONS ...................................................................................................................... 41 4.1 4.2 4.3 OVERVIEW ...................................................................................................................................................... 41 MACRO SERVICE ........................................................................................................................................... 42 CONTEXT SWITCHING FUNCTION .............................................................................................................. 44 4.3.1 4.3.2 Context Switching Function at Interrupt Request ..................................................................... 44 Context Switching Function by BRKCS Instruction ................................................................. 45 5. 6. 7. 8. 9. STANDBY FUNCTIONS ......................................................................................................................... 46 EXTERNAL DEVICE EXPANSION FUNCTION .................................................................................... 47 OPERATION AFTER RESET ................................................................................................................. 48 INSTRUCTION SET ................................................................................................................................ 49 ELECTRICAL SPECIFICATIONS .......................................................................................................... 63 9 PD78323, 78324 10. PACKAGE DRAWINGS .......................................................................................................................... 74 11. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 76 APPENDIX A. LIST OF 78K/III SERIES PRODUCTS ................................................................................ 77 APPENDIX B. TOOLS .................................................................................................................................... 79 B.1 B.2 DEVELOPMENT TOOLS ................................................................................................................................ 79 EVALUATION TOOLS .................................................................................................................................... 83 B.3 EMBEDDED SOFTWARE ................................................................................................................................ 83 10 PD78323, 78324 1. LIST OF PIN FUNCTIONS 1.1 PORT PINS DualFunction Pin Pin Name I/O Port 0 8-bit input/output port Input/output can be specified bit-wise Also serves as a realtime output port. Function P00 to P07 Input/ output RTP0 to RTP7 NMI INTP0 INTP1 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 Input/ output Port 4 8-bit input/output port Input/output can be specified in 8-bit unit. Port 5 8-bit input/output port Input/output can be specified bit-wise Port 7 Dedicated port for 8-bit input Input/ output Port 3 5-bit input/output port Input/output can be specified bit-wise Input Port 2 Dedicated port for 8-bit input INTP2 INTP3 INTP4 INTP5 INTP6/TI TXD RXD SO/SB0 SI/SB1 SCK AD0 to AD7 P40 to P47 P50 to P57 Input/ output A8 to A15 P70 to P77 P80 P81 P82 P83 P84 P85 P90 P91 P92 P93 Input AN0 to AN7 TO00 TO01 Input/ output Port 8 6-bit input/output port Input/output can be specified bit-wise TO02 TO03 TO10 TO11 RD Input/ output Port 9 4-bit input/output port Input/output can be specified bit-wise WR TAS TMD 11 PD78323, 78324 1.2 PINS OTHER THAN PORTS (1/2) DualFunction Pin P00 to P07 Pin Name I/O Function Realtime output port which generates pulses in synchronization with the trigger signal transmitted from the realtime pulse unit (RPU). Nonmaskable interrupot request input capable of specifying the effective at the rising or falling edge by a mode register. RTP0 to RTP7 Output NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 TI TXD RXD SO SI SB0 SB1 SCK Input P20 P21 P22 P23 Input External interrupt request input capable of specifying the effective edgy by a mode register. P24 P25 P26 P27/TI Input Output Input Output Input Input /output Input /output Input /output Output External count clock input to timer 1 (TM1) Serial data output of asynchronous serial interface (UART) Serial data input of asynchronous serial interface (UART) Serial data output of clock synchronous serial interface in 3-wire mode Serial data input of clock synchronous serial interface in 3-wire mode Serial data output of clock synchronous serial interface in SBI mode P27/INTP6 P30 P31 P32/SB0 P33/SB1 P32/SO P33/SI Serial clock input/output of clock synchronous serial interface P34 AD0 to AD7 A8 to A15 TO00 TO01 TO02 Multiplexed address/data bus for external memory expansion Address bus for external memory expansion P40 to P47 P50 to P57 P80 P81 P82 Output TO03 TO10 TO11 RD WR Output TAS TMD WDTO Output Pulse output from the realtime pulse unit P83 P84 P85 Strobe signal output generated for external memory read operation Strobe signal output generated for external memory write operation Control signal output generated for access to turbo access manager PD71P301Note Signal output indicating that the watchdog timer has generated a nonmascable interrupt. Timing signal output generated for externally latching the address information output from pins AD0 to AD7 in order to access the external memory. P90 P91 P92 P93 -- -- ASTB Output Note Maintenance product 12 PD78323, 78324 1.2 PINS OTHER THAN PORTS (2/2) DualFunction Pin Pin Name I/O Function In the PD78324, EA pin is normally connected to VDD. Connecting EA pin to VSS sets the ROM-less mode and accesses the external memory. In the PD78323, this pin should be fixed to "0" (low level). The EA pin level cannot be changed during operation. A/D converter analog input. A/D converter reference voltage input. A/D converter analog power supply A/D converter GND System reset input Crystal connect pin for sysem clock oscillation. When an external clock is supplied, the clock is input to X1 and the inverted clock is input to X2. (X2 can also be left open.) Positive power supply GND pin Not internally connected. Connected to VSS (GND) (can also be left open). EA Input -- -- -- -- -- -- -- -- -- -- -- AN0 to AN7 AVREF AVDD AVSS RESET X1 X2 VDD VSS NC Input Input -- -- Input Input -- -- -- -- 13 PD78323, 78324 1.3 PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The pin input/output circuits, partly simplified, are shown in Table 1-1 and Figure 1-1. Table 1-1. I/O Circuit Types of Pins and Their Recommended Connection Methods when Unused Input/Output Circuit Type 5 Pin Recommended Connection Method Input mode : Individually connected to VDD or VSS via resistor Output mode: Leave open P00/RTP0 to P07/RTP7 P20/NMI P21/INTP0 to P26/INTP5 P27/INTP6/TI P30/TXD P31/RXD P32/SO/SB0 P33/SI/SB1 P34/SCK P40/AD0 to P47/AD7 P50/A8 to P57/A15 P70/AN0 to P77/AN7 P80/TO00 to P83/TO03 P84/TO10, P85/TO11 P90/RD P91/WR P92/TAS P93/TMD WDTO ASTB EA RESET AVREF, AVSS AVDD NC 2 Connected to VSS 5 8 Input mode : Individually connected to VDD or VSS via resistor Output mode: Leave open 5 9 5 Input mode : Individually connected to VDD or VSS via resistor Output mode: Leave open 5 Connected to VSS 3 4 1 2 -- -- -- Leav open -- -- Connected to VSS Connected to VDD Connected to VSS (can also be left open) 14 PD78323, 78324 Figure 1-1. Pin Input/Output Circuits Type 1 Type 5 VDD VDD data P-ch IN/OUT P-ch IN N-ch input enable output disable N-ch Type 2 Type 8 VDD data P-ch IN output disable N-ch IN/OUT Schmitt-trigger input having hysteresis characteristics. Type 3 VDD Comparator IN P-ch N-ch + - Type 9 P-ch OUT N-ch VREF (Threshold Voltage) input enable Type 4 VDD data P-ch OUT output disable N-ch Push-pull output which can become high-impedance output (with both P-ch and N-ch set to off) 15 PD78323, 78324 2. CPU ARCHITECTURE 2.1 MEMORY SPACE In the PD78324 a maximum of 64K bytes of memory can be addressed (see Figure 2-1). Program fetches can be performed within the area from 0000H to FDFFH. However, when external memory expansion is implemented in the area from FE00H to FFFFH (main RAM and special function register area), program fetches can also be performed on this area. In this case, a program fetch is performed on the external memory, not on the main RAM or special function registers. (1) Vector table area Interrupt request from the peripheral hardware, reset input, external interrupt request and interrupt branch address by break instruction are stored in the 0000H to 003FH 64-byte area. Generation of an interrupt request sets the even address content of each table in the lower 8 bits of the program counter (PC) and the odd address content in the higher 8 bits. Interrupt Source RESET NMI WDT TMF0 EXF0 EXF1 EXF2 EXF3 EXF4/CCFX0 EXF5/CCFX1 EXF6/TI CMF00 CMF01 CMF02 CMF03 CMF10 CMF11 SRF STF CSIIF ADF Operation code BRK Vector Table Address 0000H 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0024H 0026H 0028H 002AH 003CH 003EH (RESET pin input) ........................................... (NMI pin input) ................................................ (Watchdog timer) ............................................ (Realtime pulse unit) ....................................... (INTP0 pin input) ............................................. (INTP1 pin input) ............................................. (INTP2 pin input) ............................................. (INTP3 pin input) ............................................. (INTP4 pin input/realtime pulse unit) ............. (INTP5 pin input/realtime pulse unit) ............. (INTP6/TI pin input) ........................................ (Realtime pulse unit) ....................................... (Realtime pulse unit) ....................................... (Realtime pulse unit) ....................................... (Realtime pulse unit) ....................................... (Realtime pulse unit) ....................................... (Realtime pulse unit) ....................................... (Serial receive complete) ................................ (Serial send complete) .................................... (Clock synchronous serial interface) .............. (A/D converter) ................................................ trap ................................................................... (Break instruction) ........................................... If bit 1 (TPF) of CPU control word (CCW) is set to 1, the 8002H to 803FH external memory area is used as an interrupt vector table in place of 0002H to 003FH. 16 PD78323, 78324 (2) CALLT table area 32 tables of call addresses of 1-byte call instruction (CALLT) can be stored in the 0040H to 007FH 64-byte area. If bit 1 (TPF) of CPU control word (CCW) is set to 1, the 8040H to 807FH external memory area is used as a CALLT instruction table in place of 0040H to 007FH. (3) CALLF entry area The 0800H to 0FFFH area can be directly subroutine-called by 2-byte call instruction (CALLF). (4) On-chip RAM area A 1024-byte RAM is built in FB00H to FEFFH. This area is composed of the following 2 RAMs. * Peripheral RAM : FB00H to FDFFH (768 bytes) * Main RAM : FE00H to FEFFH (256 bytes) The main RAM can be accessed at high speed. In the main RAM area, the macro service control word and general register group composed of 8 register banks are mapped onto the 36 bytes from FE06H to FE2BH and the 128 bytes from FE80H to FEFFH, respectively. (5) Special function register (SFR) area Registers having specially assigned functions, such as on-chip peripheral hardware mode registers and control registers, are mapped in the FF00H to FFFFH area. Addresses without mapped registers cannot be accessed. (6) External memory area The PD78324 can add external memories (ROM, RAM) to the 32K-byte (8000H to FFFFH) area. The PD78323 can connect external memories (ROM, RAM) to the 64K-byte (0000H to FFFFH) area. Each external memory can be accessed using P40/AD0 to P47/AD7 (multiplexed address/data bus), P50/A8 to P57/A15 (address bus) and RD, WR and ASTB signals. The external access area is mapped in the FFD0H to FFDFH 16-byte area of the special function register (SFR). In this way, the external memory can be accessed by SFR addressing. Dedicated pins (TAS and TMD pins) are provided to connect turbo access manager (PD71P301)Note. If the PD71P301 is used, the program processing speed equal to that of the on-chip ROM can be obtained. Note Maintenance product 17 18 Figure 2-1. Memory Map EA = L * PD78323 * PD78324 ROM-Less Mode EA = H ( PD78324) FFFFH FF00H FEFFH Special Function Register (SFR) (256 x 8) FEFFH FE80H Main RAM (256 x 8) FE00H Data Memory FDFFH Peripheral RAM (768 x 8) FB00H FAFFH Memory Space (64K x 8) Program Memory Data Memory FB00H FE2BH FE06H General Register (128 x 8) Macro Service Control (36 x 8) Data Area (1024 x 8) 7FFFH External MemoryNote (31488 x 8) Program Area 1000H 0FFFH 0800H 07FFH 0080H 007FH CALLF Instruction Table Area (64 x 8) 0040H 003FH Vector Table Area (64 x 8) 0000H 0000H 0000H 0FFFH CALLF Instruction Entry Area (2048 x 8) Program Area External Memory (64256 x 8) 8000H 7FFFH Program Memory Data Memory Internal ROM (32768 x 8) PD78323, 78324 Note Accessed in external memory expansion mode. Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the address that specifies the operand must be an even value. PD78323, 78324 2.2 PROCESSOR REGISTERS The processor registers consist mainly of three groups. They are general registers consisting of 8 banks of sixteen 8bit registers, control registers consisting of one 8-bit register and three 16-bit registers, and special function registers such as peripheral hardware I/O mode registers. Figure 2-2. Register Configuration Control Registers 15 PC 0 PSW SP 7 CCW General Registers 7 0 7 0 0 R1 R3 R5 R7 R9 R 11 R 13 R 15 Special Function Registers 7 SFR 255 SFR 253 SFR 251 SFR 249 07 R0 R2 R4 R6 R8 R 10 R 12 R 14 0 SFR 254 SFR 252 SFR 250 SFR 248 SFR 1 SFR 0 Remark The CCWs of the control registers are mapped in the special function register (SFR) area. 19 PD78323, 78324 2.2.1 Control Register The control registers carry out dedicated functions such as control of the program sequence, status and stack memory, and modification of operand addressing. They consist of three 16-bit registers and one 8-bit register. (1) Program counter (PC) This is a 16-bit register which holds the address information of the next program to be executed. It is normally incremented according to the number of bytes of the instruction to be fetched. If an instruction with data branch is executed, immediate data and the register content are set. RESET input sets and branches the data of 0000H and 0001H reset vector tables in the PC. (2) Program status word (PSW) This is a 16-bit register consisting of various flags which are set or reset by the result of instruction execution. Read/ write access is carried out in units of the higher 8 bits (PSWH) or lower 8 bits (PSWL). Each flag can be operated using the bit operation instruction. If an interrupt request is made or BRK instruction is executed, data is automatically saved in the stack and is recovered by RETI or RETB instruction. All bits are reset to 0 by RESET input. Figure 2-3. PSW Format (a) Interrupt priority level transition flag (LT) 7 PSWH UF 7 PSWL S 6 5 4 3 0 3 IE 2 0 2 P/V 1 0 1 LT 0 0 0 CY RBS2 RBS1 RBS0 6 Z 5 RSS 4 AC This flag is used to control the interrupt priority. For normal operation of the interrupt control circuit, this bit must not be operated by a program. (b) Carry flag (CY) If a carry is generated out of bit 7 or 15 as a result of the execution of an operation instruction or a borrow is generated into bit 7 or 15, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested by the conditional branch instruction. When a bit control instruction is executed, this flag functions as a bit accumulator. (c) Zero flag (Z) When the operation result is zero, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested by the conditional branch instruction. (d) Sign flag (S) When MSB of the operation result is "1", this flag is set to 1. When the MSB is "0", this flag is reset to 0. This flag can be tested by the conditional branch instruction. (e) Parity/overflow flag (P/V) Only when an overflow or underflow occurs as two's complement during execution of an arithmetic operation instruction, this flag is set to 1. In all other cases, it is reset to 0 (overflow flag operation). If the bit number of the operation result set to 1 is even during execution of an logic operation instruction, this flag is set to 1. If the bit number is odd, this flag is reset to 0 (parity flag operation). This flag can be tested by the conditional branch instruction. 20 PD78323, 78324 (f) Auxiliary carry flag (AC) If a carry is generated out of bit 3 as a result of operation or a borrow is generated into bit 3, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested by the conditional branch instruction. (g) Register set select flag (RSS) This flag is used to specify general registers X, A, C and B. As shown in Table 2-1, the RSS value determines the relationship between the functional register and the absolute register. Thus, another register set (X, A, C, B) can be used by switching the RSS flag. (h) Interrupt request enable flag (IE) This flag is used to indicate interrupt request enable/disable. This flag is set to 1 by execution of EI instruction and is reset to 0 byexecution of DI instruction or acceptance of an interrupt. (i) Register bank select flag (RBS0 to RBS2) This is a 3-bit flag to select one of eight register banks (RBANK0 to RBANK7). (j) User flag (UF) This flag is set or reset in the user program and can be used for program control. (3) Stack pointer (SP) This is a 16-bit register which holds the first address of the stack area (LIFO format) of the memory. It is operated by a dedicated instruction. SP is decremented before write (save) operation into the stack memory and is incremented after read (return) operation from the stack memory. Since SP becomes indeterminate by RESET input, it must be set before subroutine call. 21 PD78323, 78324 (4) CPU control word (CCW) This is an 8-bit register consisting of CPU control related flags. It is mapped in the special function register area and can be controlled by the software. All bits are reset to 0 by RESET input. Figure 2-4. CCW Format 7 0 6 0 5 0 4 0 3 0 2 0 1 TPF 0 0 CCW * Table position flag (TPF) This flag is used to specify the interrupt vector table area and the memory area used as CALLT instruction table area. As TPF has been reset to 0 after application of RESET input, the 0000H to 007FH address is used as each table area. The 8002H to 807FH address of the external memory area in place of 0002H to 007FH address can be used as each table area by setting TPF to 1 using the software. The vector tables of the BRK instruction, operation code trap interrupt and reset input are fixed to 003EH, 003CH and 0000H, respectively, and they are not affected by TPF. 2.2.2 General Registers These are 128-byte registers mapped in the special area (FE80H to FEFFH) of the internal RAM space. They consist of eight register banks. The general register in the bank consists of sixteen 8-bit registers. Figure 2-5. General Register Memory Location 8-Bit Processing FEFFH RBNK0 RBNK1 RBNK2 RBNK3 RBNK4 RBNK5 RBNK6 FE80H RBNK7 7 R15 R13 R11 R9 R7 R5 R3 R1 07 R14 R12 R10 R8 R6 R4 R2 R0 0 16-Bit Processing (FH) (DH) (BH) (9H) (7H) (5H) (3H) (1H) RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0 (EH) (CH) (AH) (8H) (6H) (4H) (2H) (0H) 15 0 22 PD78323, 78324 The sixteen 8-bit registers can function as eight 16-bit register pairs (RP0 to RP7) as well. As shown in Table 2-1, the sixteen 8-bit registers are characterized by functional names. The X register functions as the lower half of the 16-bit accumulator, the A register functions as the upper half of the 8-bit or 16-bit accumulator, the B and C registers function as a counter, and DE, HL, VP and UP function as address register pairs. In particular the VP register is function as a base register and the UP register is as a user stack pointer. The unique function register charges as shown in Table 2-1 according to the value of the register set select flag (RSS) in the PSW. Thus, if the program is described by the functional name, another register set of X, A, C and B can be used by means of the RSS flag. The PD78324 can carry out processed data addressing operations, implied addressing by functional names with importance attached to the unique function of each register and register addressing by absolute names with a view to fast processing with a small number of data transfers or creating highly descriptive programs. Table 2-1. General Register Configuration Absolute Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 VPL VPH UPL UPH E D L H Functional Name RSS = 0 RSS = 1 X A C B X A C B VPL VPH UPL UPH E D L H Absolute Name RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 VP UP DE HL Functional Name RSS = 0 RSS = 1 AX BC AX BC VP UP DE HL 23 PD78323, 78324 2.2.3 Special Function Registers (SFR) These registers are provided with special functions. They include various peripheral hardware mode registers and control registers (CCW). The special function registers are assigned in the FF00H to FFFFH 256-byte space. Short direct memory addressing is applied to the FF00H to FF1FH 32-byte area for processing with a short word length. The bit manipulation, arithmetic and transfer instructions can be executed in all areas. The FFD0H to FFDFH 16-byte area is externally accessible by SFR addressing. Thus, the external memory can be accessed and the external device bit manipulation can be carried out by an instruction having a short word length. Table 2-2 lists the special function registers (SFR). The items in the table have the following meanings. * Symbol................. Indicates the address of the built-in special function register. Can be described in the instruction operand column. * R/W.......................Indicates if the corresponding special function register can read or write. R/W : Read/write enable R : Read only enable (register bit test enable) W * Manipulable bit unit : Write only enable ....................... Indicates the applicable operation bit unit for the corresponding special function register. 16-bit manipulable SFR can be described in operand sfrp. When specified by an address, an even address is described. 1-bit manipulable SFR can be described by the bit operation instruction. * On reset ............... Indicates the state of each register when RESET is input. Cautions 1. Addresses for which no special function registers have been assigned cannot be accessed in the FF00H to FFFFH area. 2. Do not write to the read only register. If data is written, the internal circuit may malfunction. 24 PD78323, 78324 Table 2-2. List of Special Function Registers (1/4) Manipulable Bit Unit Address FF00H FF02H FF03H FF04H FF05H FF07H FF08H FF09H FF0AH FF0BH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF20H FF23H FF25H FF28H FF29H FF2AH FF2BH FF2CH Timer register 1 FF2DH FF30H FF31H FF32H FF33H FF34H FF35H Capture register X0 (higher 16 bits) Note Special Function Register (SFR) Name Port 0 Port 2 Port 3 Port 4 Port 5 Port 7 Port 8 Port 9 Free running counter (lower 16 bits) Note Capture register X0 (lower 16 bits) Note Symbol P0 P2 P3 P4 P5 P7 P8 R/W 1 bit R/W R 8 bits 16 bits -- -- On Reset q -- q q q q q q q q -- -- -- -- -- -- -- -- -- -- -- -- -- q R/W q q -- -- -- Undefined R R/W -- q q -- -- P9 TM0LW q q 0000H CTX0LW -- CT01LW R -- -- -- CT02LW -- -- CT03LW -- -- CCX0LW -- R/W CC01LW PM0 PM3 PM5 PM8 PM9 TM0UW -- -- TM1 -- -- CTX0UW R -- -- CT01UW -- -- CT02UW -- -- -- -- -- -- -- -- -- -- W -- -- -- -- -- -- -- -- Capture register 01 (lower 16 bits) Note q q Undefined Capture register 02 (lower 16 bits) Note Capture register 03 (lower 16 bits) Note Capture/compoare register X0 (lower 16 bits) Note q q Capture/compoare register 01 (lower 16 bits) Note q -- -- -- -- -- FFH x x x1 1111B FFH x x 11 1111B x x x x 1111B Port 0 mode register Port 3 mode register Port 5 mode register Port 8 mode register Port 9 mode register Free runnting counter (higher 16 bits) Note q q q q q -- q 0000H q q Capture register 01 (higher 16 bits) Note q q Undefined Capture register 02 (higher 16 bits) Note Note Upper or lower half of 18-bit register. 25 PD78323, 78324 Table 2-2. List of Special Function Registers (2/4) Manipulable Bit Unit Address FF36H FF37H FF38H FF39H FF3AH FF3BH FF40H FF41H FF43H FF48H FF4CH Baud rate generator FF4DH FF60H FF61H FF62H FF68H FF6AH Realtime output port register Realtime output port reset register Port read control register A/D converter mode register A/D conversion result register ADCR (for 16-bit access) A/D conversion result register FF6BH FF70H FF71H FF72H FF73H FF74H FF75H FF76H FF77H FF7CH FF7DH FF7EH Compare register 11 FF7FH Clock synchronous serial FF80H FF82H FF86H interface mode register Serial bus interface control register Serial I/O shift register CSIM SBIC SIO CM11 -- -- Compare register 10 CM10 R/W -- -- -- -- Compare register 03 CM03 Compare register 02 CM02 Compare register 01 CM01 -- -- -- -- -- -- -- Undefined -- -- -- -- -- ADCRH (for upper 8-bit access) -- Compare register 00 CM00 R/W -- -- -- -- -- R -- -- -- BRG RTP RTPR PRDC ADM Special Function Register (SFR) Name Capture register 03 (higher 16 bits) Note Symbol R/W 1 bit -- 8 bits -- -- -- -- -- -- 16 bits On Reset CT03UW R q -- -- Capture/compoare register X0 (higher 16 bits) Note CCX0UW -- R/W -- -- PMC0 RTPS PMC3 W PMC8 W R/W -- CC01UW q Undefined Capture/compoare register 01 (higher 16 bits) Note q -- -- -- -- 00H x x x0 0000B x x 00 0000B Port 0 mode control register Realtime output port reset register Port 3 mode control register Port 8 mode control register q q q q -- -- q -- -- -- -- q Undefined -- -- -- -- 00H q R/W q q q q q q q q q -- q q q q q q q q q q q q -- 00H -- -- Undefined Note Upper or lower half of 18-bit register. 26 PD78323, 78324 Table 2-2. List of Special Function Registers (3/4) Manipulable Bit Unit Address Special Function Register (SFR) Name Asynchronous serial interface FF88H ASIM mode register Asynchronous serial interface FF8AH status register FF8CH FF8EH FFB0H FFB1H FFB2H FFB8H FFB9H FFBFH FFC0H FFC1H FFC2H FFC4H FFC6H FFC9H FFD0H to External acces area FFDFH FFE0H FFE1H FFE2H FFE3H FFE4H FFE5H FFE6H FFE7H FFE8H FFE9H FFEAH FFEBH FFECH FFEDH FFEEH FFEFH Interrupt request flag rgister 0L Interrupt request flag rgister 0H Interrupt request flag rgister 1L -- Interrupt mask flag rgister 0L Interrupt mask flag rgister 0H Interrupt mask flag rgister 1L -- Priority specify bufer register 0L Priority specify bufer register 0H Priority specify bufer register 1L -- Interrupt processing mode specify register 0L Interrupt processing mode specify register 0H Interrupt processing mode specify register 1L -- Symbol R/W 1 bit R/W 8 bits 16 bits -- On Reset q q q q q q q q q q q q q q q q q q q q q q -- 80H ASIS R :UART :UART RXB TXS TMC BRGM PRM R/W TOC0 TOC1 RPUM STBC CCW WDM MM PWC FCC R/WNote R/W R/WNote W -- -- 00H Serial receive buffer Serial send shift register Timer control register Baud rate generator mode register Prescalar mode register Timer output control register 0 Timer output control register 1 RPU mode register Standby control register CPU control word Watchdog timer mode register Memory expansion mode register -- -- Undefined -- -- -- -- -- -- -- -- -- -- -- -- -- -- 22H 00H Undefined 00H 0000 x 000B 00H q q q q q q q q q q q q q Programmable weight control register Fetch cycle control register IF0L IF0H IF1L -- MK0L IF0 q q q 00H IF1 q -- q -- MK0 MK0H MK1L MK1 -- PB0L PB0 PB0H PB1L PB1 -- ISM0L ISM0 ISM0H ISM1L ISM1 -- q R/W q q q -- q q -- q q FFH x x x x x 111B -- q q q -- q q q -- q q 00H -- q q q -- q q q -- q 00H q -- Note Write enable in case of special instructions. 27 PD78323, 78324 Table 2-2. List of Special Function Registers (4/4) Manipulable Bit Unit Address FFF0H FFF1H FFF2H FFF3H FFF4H FFF5H FFF8H FFF9H Special Function Register (SFR) Name Context switching enable register 0L Context switching enable register 0H Context switching enable register 1L -- External interupt mode register 0 External interupt mode register 1 In-service priority register Priority specify register Symbol CSE0L CSE0 CSE0H CSE1L CSE1 -- INTM0 INTM1 ISPR PRSL R R/W R/W R/W 1 bit 8 bits 16 bits On Reset q q q -- q q q -- q 00H q -- -- -- 00H -- -- q q -- q q q q q 2.3 DATA MEMORY ADDRESSING In the PD78324, the internal RAM space (FB00H to FEFFH) and the special function register area (FF00H to FFFFH) are mapped in the FB00H to FFFFH area. In the FE20H to FF1FH space of the data memory, short direct addressing enables direct addressing by 1-byte data in an instruction word. Figure 2-6. Data Memory Addressing Space FFFFH FF1FH FF00H FEFFH FE80H FE20H Main RAM FE00H FDFFH Peripheral RAM FB00H Direct Addressing Register Indirect Addressing Based Addressing Paste Indexed Addressing Paste Indexed Addressing (Provided with Displacement) Special Function Register (SFR) General Register SFR Addressing Register Addressing Short Direct Addressing External Memory 7FFFH Internal ROMNote 0000H Note When EA = L, and with the PD78323, this is external memory. Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the address that specifies the operand must be an even value. 28 PD78323, 78324 2.3.1 General Register Addressing The general registers consist of eight register banks, each consisting of sixteen 8-bit registers or eight 16-bit registers. General register addressing is carried out using the register specify field of 3 or 4 bits supplied from an instruction word, the register bank select flag (RBS0 to RBS2) and the register set select flag (RSS) in the PSW. 2.3.2 Short Direct Addressing Short direct addressing which enables direct address specification by 1-byte data in an instruction work is applied to the FE20H to FF1FH space. The short direct memory is accessed as 8-bit or 16-bit data. When accessing the memory as 16bit data, specification of even data for 1-byte address specify data will cause 2-byte data specified by continuous addresses of even and odd addresses to be accessed. (Do not specify odd number for address specify data.) 2.3.3 Special Function Register (SFR) Addressing This addressing is applied to operations for the special function register (SFR) mapped in the SFR area of FF00H to FFFFH. Addressing is performed by 1-byte data in the instruction word corresponding to the lower 8 bits of the special function register address. For 16-bit access of 16-bit operational SFR, 2-byte data specified by continuous even and odd addresses is accessed as is the case with short direct addressing. 29 PD78323, 78324 3. BLOCK FUNCTIONS 3.1 BUS CONTROL UNIT (BCU) In the BCU, the necessary bus cycle is started according to the physical address obtained by the execution unit (EXU). If no bus cycle startup request is made from the EXU, a prefetch address is generated and instruction prefetch is carried out. The prefetched instruction code is fetched into the instruction queue. 3.2 EXECUTION UNIT (EXU) In the EXU, address calculation, arithmetic logical operation and data transfer are controlled by microprograms. A 256byte RAM is built in the EXU. The 256-byte RAM in the EXU is accessible by the relevant instruction faster than peripheral RAM (768 bytes). 3.3 ROM/RAM This block consists of a 32K-byte ROM and a 768-byte RAM. However, the PD78323 does not incorporate ROM. ROM access can be disabled by EA pin. 3.4 INTERRUPT CONTROLLER Various interrupt requests (NMI, INTP0 to INTP6) generated either externally or from the peripheral hardware are processed by the context switch, vectored interrupt or macro service function. The 3-level interrupt priority is also specified. 30 PD78323, 78324 3.5 PORT FUNCTIONS Table 3-1 lists the digital input/output ports. Each port can carry out many control operations including 8 and other bit data input/output operations. Table 3-1. Port Functions and Features Port Name Function Feature Specifiable bit-wise for input/output. Also specifiable for realtime output port. Remarks Serves as RTP0 to RTP7 and pins. Serves as NMI, INTP0 to INTP5, INTP6/TI and pins. Serves as TXD, RXD, SO/SB0, SI/SB1, SCK and pins. Port 0 8-bit input/outpput Port 2 8-bit input Input port pin. Functions as an external interrupt input. Port 3 5-bit input/output Specifiable bit-wise for port pins or control pins. Port 4 8-bit input/output Specifiable in 8-bit units for input or output. Functions as the multiplexed address/data bus (AD0 to AD7) in the external memory expansion mode. Specifiable bit-wise for input or output. Functions as the address bus (A8 to A15) in the external memory expansion mode. Pins which are not used as the address bus can be used as a port. Input port pin. Also functions as analog input to the A/D converter. -------- Port 5 8-bit input/output -------- Port 7 8-bit input Serves as AN0 to AN7 and pins. Functions as TO00 to TO03, TO10 to TO11 and pins. Port 8 6-bit input/output Specifiable bit-wise for the port pin or control pin. Port 9 4-bit input/output Specifiable bit-wise for input/output. P90 and P91 function as RD output and WR output, respectively, in the external memory expansion mode. P92 and P93 function as TAS output and TMD output, respectively, in the high-speed fetch mode. -------- 31 PD78323, 78324 3.6 CLOCK GENERATOR The clock generator generates and controls internal system clocks (CLK) supplied to the CPU. It is configured as shown in Figure 3-1. Figure 3-1. Block Diagram of Clock Generator X1 Divider System Clock Generator X2 fXX or fX 1/2 fCLK Internal System Clock (CLK) STOP Mode Remarks 1. 2. 3. fXX : Crystal oscillator frequency fX : External clock frequency fCLK : Internal system clock frequency The system clock oscillator oscillates by a crystal resonator connected to X1 and X2 pins. It stops oscillating when set to the standby mode (STOP). External clocks can be input to the system clock oscillator. In such cases, input a clock signal to the X1 pin and input the reverse phase of the clock signal to the X2 pin. The X2 pin can also be left open. Caution When using external clocks, do not set the STBC STP bit. The divider generates internal system clocks (fCLK) by dividing a system clock oscillator output (fxx for crystal oscillation and fx for external clocks) into two parts. 32 PD78323, 78324 Figure 3-2. Externally-Mounted System Clock Generator (a) Crystal oscillator PD78324 X2 X1 VSS (b) External clock (i) When the inverted phase of an external clock to be input to the X1 pin is input to the X2 pin PD78324 External Clock X1 (ii) When X2 pin is left open PD78324 External Clock X1 X2 Open X2 Cautions 1. When the system clock oscillator is used, the following points should be noted concerning wiring within broken lines shown in Figure 3-2, in order to prevent the effects of wiring capacitance, etc. * Keep the wiring as short as possible. * Do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows. * Ensure that oscillator capacitor connection points are always at the same potential as VSS. Do not ground in a ground pattern in which a high current flows. * Do not take a signal from the oscillator. 2. When an external clock is input to the X1 pin and the X2 pin is left open, ensure that no loads such as wiring capacitance are connected to the X2 pin. 33 PD78323, 78324 3.7 REALTIME PULSE UNIT (RPU) This unit can measure pulse intervals and frequencies, and generate programmable pulse outputs. It consists mainly of two timers. To flexibly cope with many applications, the configuration of registers connected to the timers can be changed using programs. To meet various applications, toggle output (6 max.) or set/ reset output (4 max.) can be selected as timer output. 3.7.1 Configuration The realtime pulse unit is configured mainly of timer 0 (TM0) which functions as a 16-bit or 18-bit free running timer and timer 1 (TM1) which functions as a 16-bit timer/event counter shown in Figure 3-3. 34 Figure 3-3. Realtime Pulse Unit Configuration TM0 2 10 11 fCLK/4 fCLK/8 15 17 OVF INTCM00 T COMPARE REG. CM00 COMPARE REG. CM01 COMPARE REG. CM02 COMPARE REG. CM03 R S T R S T R S T INTP0 INTP1 INTP2 INTP3 INTCCX0 INTP5 CAPTURE REG. CT01 CAPTURE REG. CT02 CAPTURE REG. CT03 INTCC01 Match MODE0 MODE1 TO03 TO02 Match COMPARE REG. CM10 COMPARE REG. CM11 T R S T INTCM10 INTCM11 Match TO11 TO10 TO01 TO00 INTOV (CLEAR CONTROL) INTP6/TI fCLK/16 16-BIT TIMER/EVENT COUNTER INTP0 (OPPOSITE EDGE) OVF TM1 0 16/18-BIT FREE RUNNING TIMER INTCM01 INTCM02 INTCM03 CAPTURE/COMPARE REG. CC01 PD78323, 78324 INTP0 INTP4 CAPTURE REG. CTX0 CAPTURE/COMPARE REG. CCX0 Match INTP0 INTCCX0 35 PD78323, 78324 3.7.2 Realtime Output Function The realtime output port can set/reset port outputs bit-wise in synchronization with the trigger signal transmitted from the RPU (Realtime Pulse Unit). It enables to generate multi-channel synchronous pulses easily. Figure 3-4. Realtime Output Port WRPORT PMC0n = 0 P0n Output Latch WRRTPR INTCM03 RTPn R RTPRn WRPTP PMC0n = 1 Internal Bus D Q P0n WRRTPS RTPSn INTCCX0 RD S PM0n = 0 PM0n = 1 36 PD78323, 78324 3.8 A/D CONVERTER The PD78324 incorporates a high-speed, high-resolution 10-bit analog/digital (A/D) converter. This A/D converter is equipped with eight analog inputs (AN0 to AN7) and A/D conversion result register (ADCR) which holds the conversion results. Upon termination of conversion, the interrupt which can start the macro service is generated. Figure 3-5. A/D Converter Block Diagram Sample & Hold Circuit AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AVREF Input Circuit D/A Converter AVSS Comparator ADM (8) 8 Internal Bus SAR (10) 10 10 ADCR (10) 10 Internal Bus 3.9 SERIAL INTERFACE The PD78324 is equipped with the following two independent channels for the serial interface function. Asynchronous serial interface Clock synchronous serial interface * 3-wire serial I/O mode * Serial bus interface mode (SBI mode) Since the PD78324 incorporates a baud rate generator, it can set any serial transfer rate irrespective of the operating frequency. The baud rate generator functions for the 2-channel serial interface. The serial transfer rate can be selected from 75 bps to 19.2 Kbps by setting the mode register. 37 Selector 38 Figure 3-6. Asynchronous Serial Interface Block Diagram Internal Bus ASIM RXB Receive Buffer REX PS1 PS0 CL SL SCK BRG BRGM ASIS RXD Shift Register PE FE OVE TXS Shift Register 1 2 Match TXD Receive Control Parity Check Clear INTSER INTSR Send Control Parity Addition fCLK/8 INTST 1 16 1 16 Send/Receive Baud Rate Generator Output PD78323, 78324 fCLK/4 Baud Rate Generator Figure 3-7. Block Diagram of Clock Synchronous Serial Interface Internal Bus 8 CSIM MOD2 CTXE CRXE WUP MOD1 CLS1 CLS0 MOD0 8 SBIC RELT CMDT RELD CMDD ACKT ACKE ACKD BSYE SET CLEAR SI/SB1 Shift Register SIO D Q SO Latch SO/SB0 Busy/ Acknowledge Detector N-ch Open Drain Output Enable Bus Release/ Command/Acknowledge Detector Interrupt Signal Generation Controller SCK Serial Clock Counter INTCSI Baud Rate Generator Output fCLK/8 fCLK/32 PD78323, 78324 Serial Clock Controller MPX CLS1 CLS0 39 PD78323, 78324 3.10 WATCHDOG TIMER The watchdog timer is used to prevent program overrun and deadlock. Normal operation of the program or system can be confirmed by checking that no watchdog timer interrupt has been generated. Thus, an instruction to clear the watchdog timer (timer start) is set into each program module. If the watchdog timer clear instruction is not cleared within the time period set into the watchdog timer and the watchdog timer overflows, a watchdog timer interrupt is generated, and a low level is generated to WDTO pin, thereby notifying of an error in the program. The watchdog timer can also be used to maintain the oscillation stabilizing time of the oscillator after the stop mode has been released. Figure 3-8 shows the watchdog timer configuration. Figure 3-8. Watchdog Timer Configuration fCLK/28 fCLK/210 fCLK/212 Timer (5 Bits) Clear WDT CLR WDT STOP INTWDT WDTO Watchdog Timer (8 Bits) Overflow Oscillation Stabilizing Time Controller 40 PD78323, 78324 4. INTERRUPT FUNCTIONS 4.1 OVERVIEW In the PD78324, various interrupt requests generated externally or from the on-chip peripheral hardware are handled in the following three processing modes. Interrupt Request Handled by Vectored Interrupt Processing Handled by Context Switching Handled by Macro Service Interrupt requests are classified into the following three groups. * Nonmaskable interrupt requests * Maskable interrupt requests * Interrupt requests by software Figure 4-1 shows the maskable interrupt request processing modes. Table 4-1 gives a listing of interrupt factors which can be processed. Figure 4-1. Interrupt Request Processing Modes x x MK = 1 (Interrupt Masked) Vectored Interrupt and Macro Service Reserved x x MK = 0 (Interrupt Unmasked) x x ISM = 0 (Vectored Interrupt Processing Mode) DI Vectored Interrupt Processing Reserved EI x x CSE = 0 Vectored Interrupt Processing Executed x x CSE = 1 Context Switching Executed x x ISM = 1 (Macro Service Processing Mode) Macro Service Processing Executed 41 PD78323, 78324 Table 4-1. List of Interrupt Factors Interrupt Request Type Software --- Nonmaskable --- --- 0 1 2 3 4 5 6 7 Maskable 8 9 10 11 12 13 14 15 16 17 --- Reset --- --- INTCM00 INTCM01 INTCM02 INTCM03 INTCM10 INTCM11 INTSR INTST INTCSI INTAD INTSERNote RESET CM00 match signal CM01 match signal CM02 match signal CM03 match signal CM10 match signal CM11 match signal Serial receive terminate interrupt Serial send terminate interrupt Serial send/receive interrupt A/D conversion terminate interrupt Default Priority --- Request Signal --- --- NMI INTWDT INTOV INTP0 INTP1 INTP2 INTP3 INTP4/INTCCX0 INTP5/INTCC01 INTP6/TI Interrupt Factor Function BRK instruction Operation code trap NMI pin input Watchdog timer Timer 0 overflow INTP0 pin input INTP1 pin input INTP2 pin input INTP3 pin input INTP4 pin input/CCX0 match signal INTP5 pin input/CC01 match signal Generator Unit --- --- (External interrupt) (WDT) (RPU) (External) (External) (External) (RPU/exteranl) (RPU/exteranl) (RPU/exteranl) (Exteranl) (RPU) Macro Service --- --- --- --- Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H INTP6 pin input/TI input Available (RPU) (RPU) (RPU) (RPU) (RPU) (UART) (UART) (CSI) (A/D) (UART) --- --- --- 0018H 001AH 001CH 001EH 0020H 0024H 0026H 0028H 002AH ---Note 0000H Serial receive error signal Reset input Note This is a test factor. A vectored interrupt is not generated. 42 PD78323, 78324 4.2 MACRO SERVICE The macro service function is executed at the interrupt request to carry out data operation and data transfer in hardware terms between the special function register area and the memory space. Upon startup of the macro service, the CPU stops program execution temporarily. 1-byte/2-byte data operation and transfer are automatically carried out between the special function register (SFR) and the memory. Upon termination of the macro service, the interrupt request flag is reset to 0 and the CPU restarts program execution. When the CPU carries out the macro service operations as many as set into the macro service counter (MSC), a vectored interrupt request is generated. Figure 4-2. Macro Service Processing Sequence Example Macro Service Processing Interrupt Request Generated Macro service execution ; Data Transfer, and Realtime Output Port Control ; Macro Service Counter (MSC) Decrement (by 1) MSC MSC-1 Yes MSC = 0? No ISMxx 0 Interrupt request flag 0 Vectored Interrupt Request Occurred Next Instruction Executed 43 PD78323, 78324 4.3 CONTEXT SWITCHING FUNCTION This is the function to first select the specified register bank in hardware terms by generating an interrupt request or executing BRKCS instruction, to branch the selected register bank to the vector address prestored in the register bank, and also to stack the current PC and PSW contents into the register bank. 4.3.1 Context Switching Function at Interrupt Request The context switching function start is enabled by setting the x xCSE bit preset at each interrupt request to 1. If an unmasked interrupt request for which the context switching function has been enabled is generated in the EI state, the register bank which is specified by the lower 3 bits of the lower address (even address) of the corresponding interrupt vector table address is selected. The vector address prestored in the selected register bank is transferred to the PC, the PC and PSW contents are saved into the register bank, and the operation is branched to the interrupt processing routine. Return is by means of executing the RETCS instruction. Figure 4-3. Context Switching at Interrupt Request RBANK n A PC Exchange Save B R5 R7 VP UP D H E L X C R4 R6 Register Banks (0 to 7) PSW 44 PD78323, 78324 4.3.2 Context Switching Function by BRKCS Instruction The context switching function can be started by executing BRKCS instruction. The context switched register bank is specified by the lower 3-bit immediate data of the 2nd operation code of BRKCS instruction. When BRKCS instruction is executed, the register bank specified by the 3-bit immediate data is selected, the vector address prestored in the register bank is set and branched to the PC, and the PC and PSW contents are saved into the register bank. Return is by means of executing the RETCSB instruction. Figure 4-4. Context Switching by Execution of BRKCS Instruction OP CODE (BRKCS) OP CODE N2 N1 N0 Register Bank Specification 000 RBANK0 111 RBANK7 RBANK n A PC Exchange Save B R5 R7 (n = 0 - 7) X C R4 R6 VP UP Register Banks (0 to 7) PSW D H E L 45 PD78323, 78324 5. STANDBY FUNCTIONS The PD78324 has the standby function to decrease the power consumption of the system. The following two modes are available for execution of the standby function. * HALT mode........ Mode for halting the CPU operation clock. The total power consumption of the system can be decreased by intermittent operation in combination with the normal operating mode. * STOP mode....... Mode for stopping the whole system by stopping the oscillator. Considerably low power consumption with leak current only can be set. Each mode is set by the software. Figure 5-1 shows standby mode (STOP/HALT mode) transition. Figure 5-1. Standby Status Transition lea se Normal Status RE Re SE SE T HA T t Re RE Se LT lea OP se t se ST NM I d ke as m pt d Un rru te te ra In ene G HALT STOP 46 PD78323, 78324 6. EXTERNAL DEVICE EXPANSION FUNCTION The PD78324 can expand external devices (data memory, program memory peripheral device) for areas (8000H to FAFFH) except the internal ROM and RAM areas. Table 6-1 and 6-2 show the pin used for external device access and the pin function setting procedure. Table 6-1. Pin Function Setting (PD78324) Memory Expansion Mode Register MM0 to MM2 Port mode 1 1 Expansion mode 0 00H AD0 to AD7 1 Except 00H MM7 0 Fetch Cycle Control Register 00H Pin Function Remarks P40 to P47 P50 to P57 P90 P91 P92 P93 EA Pin General port Setting prohibited General port Set to A8 to A15 in steps RD WR TAS TMD External device connection mode PD71P301 connection mode P50 to P57 pins according to the externally expanded memory size. The memory can be expanded in steps from 256 bytes to about 32K bytes. The pins which are not used as the address bus can be used as the general-purpose input/output port. Table 6-2. Port and Address Setting for Port 5 (PD78324) P57 Port Port Port A15 P56 Port Port Port A14 P55 Port Port A13 A13 P54 Port Port A12 A12 P53 Port A11 A11 A11 P52 Port A10 A10 A10 P51 Port A9 A9 A9 P50 Port A8 A8 A8 External Address Space 256 bytes or less 4K bytes or less 16K bytes or less About 32K bytes or less Table 6-3. Pin Function Setting (PD78323) Memory Expansion Mode Register MM7 ASTB -- Fetch Cycle Control Register Pin Function Remarks AD0 to AD7 A8 to A15 RD WR P92 TAS P93 TMD EA Pin PD78324 emulation mode External device connection mode 0 1 1 00H AD0 to AD7 A8 to A15 RD WR General port Except 00H TAS TMD PD71P301 connection mode 47 PD78323, 78324 7. OPERATION AFTER RESET If the RESET input pin is set to the low level, the system reset is applied and each hardware becomes as initialized status (reset status). If RESET input becomes high level, program execution is started. Initialize the contents of various registers in the program as required. Change the number of cycles for the programmable wait register and the fetch cycle control register in particular. The RESET input pin is equipped with an analog delay noise suppressor to prevent malfunctioning due to noise. Cautions 1. While RESET is active(low level), all pins remain high impedance (except WDTO, AVREF, AVDD, AVSS, VDD, VSS, X1 and X2). 2. If RAM has been expanded externally, mount a pull-up resistor to the P90/RD and P91/WR pins. It is possible that the P90/RD and P91/WR pins become high impedance resulting in an external RAM contents corruption or input unit damage. In addition, signals may collide on the address/data bus, resulting in the destruction of the input/output circuit. Figure 7-1. Reset Signal Acknowledge RESET Input Reset Acknowledged Reset Release For reset operation upon power-up, secure the oscillation stabilizing time of about 40 msec from power-up to reset acknowledge as shown in Figure 7-2. Figure 7-2. Reset Upon Power-Up VDD RESET Reset Release 48 Oscillation Stabilizing Time Analog Delay Analog Delay Removed as Noise Analog Delay Analog Delay PD78323, 78324 8. INSTRUCTION SET This chapter covers instruction operations. For the operation codes and the number of instruction execution clock cycles, see PD78322 User's Manual (IEU-1248). (1) Operand representation format and description method In each instruction operand column, enter the operand using the description method for the instruction operand representation format (refer to the assembler specification for details). If two or more factors are included in the description method column, select one factor. The capital alphabetic letters and +, -, #, $, ! and [ ] symbols are keywords and should be described as they are. In case of immediate data, describe appropriate numeric values or labels. When describing labels, make sure to describe #, $, ! and [ ] symbols. Table 8-1. Operand Representation and Description Method Representation Format r r1 r2 rp rp1 rp2 sfr sfrp Description Method R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15 R0, R1, R2, R3, R4, R5, R6, R7 C, B RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7 RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7 DE, HL, VP, UP Special function register code (see Table 2-2) Special function register code (16-bit operation enable register; see Table 2-2) RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7 (Two or more instructions can be described. Only PUSH and POP instructions can be described for RP5 and only PUSHU and POPU instructions can be described for PSW.) [DE], [HL], [DE+], [HL+], [DE-], [HL-], [VP], [UP] [DE+A], [HL+A], [DE+B], [HL+B], [VP+DE], [VP+HL] [DE+byte], [HL+byte], [VP+byte], [UP+byte], [SP+byte] word[A], word[B], word[DE], word[HL] ; ; ; ; Register indirect mode Based indexed mode Based mode Index mode post mem saddr saddrp $addr16 !addr16 addr11 addr5 word byte bit n FE20H to FF1FH Immediate data or label FE20H to FF1EH Immediate data (bit0 = 0) or label (for 16-bit operation) 0000H to FDFFH Immediate data or label; relative addressing 0000H to FDFFH Immediate data or label; immediate addressing (Up to FFFFH describable by MOV instruction) 800H to FFFH Immediate data or label 40H to 7EH Immediate data (bit0 = 0)Note or label 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label 3-bit immediate data (0 to 7) Note Do not make work access to bit0 = 1 (odd address). Remarks 1. 2. Although rp and rp1 have the same describable register names, they generate different codes. r, r1, rp, rp1 and post can be described with absolute names (R0 to R15, RP0 to RP7) as well as functional names (X, A, C, B, E, D, L, H, AX, BC, DE, HL, VP, UP (refer to Table 2-1 for details of the relationships between the absolute and functional names). Immediate addressing is enabled for all spaces. Relative addressing is only enabled from the first address of the subsequent instruction to the range of -128 to +127. 49 3. PD78323, 78324 Instruction Group Mnemonic Operand Bytes Flags Operation S r1 byte (saddr) byte sfr byte r r1 A r1 A (saddr) (saddr) A (saddr) (saddr) A sfr sfr A Z AC P/V CY r1, #byte saddr, #byte sfrNote, r, r1 A, r1 A, saddr saddr, A saddr, saddr A, sfr sfr, A MOV 8-bit data transfer A, mem mem, A A, [saddrp] [saddrp], A A, !addr16 !addr16, A PSWL, #byte PSWH, #byte PSWL, A PSWH, A A, PSWL A, PSWH A, r1 r, r1 A, mem XCH A, saddr A, sfr A, [saddrp] saddr, saddr #byte 2 3 3 2 1 2 2 3 2 2 1-4 A (mem) 1-4 (mem) A 2 2 4 4 3 3 2 2 2 2 1 2 A ((saddrp)) ((saddrp)) A A (addr16) (addr16) A PSWL byte PSWH byte PSWL A PSWH A A PSWL A PSWH A r1 r r1 x x x x x x x x x x 2-4 A (mem) 2 3 2 3 A (saddr) A sfr A ((saddrp)) (saddr) (saddr) Note If STBC and WDM are described for sft, a different dedicated instruction having a different number of bytes is used. Remark For the symbols in the Flags column, refer to the table below. Symbol (Blank) 0 1 x P V R Description No change Clear to 0. Set to 1. Set/clear according to the result. P/V flag operates as a parity flag P/V flag operates as an overflow flag. The previously stored value is restored. 50 PD78323, 78324 Instruction Group Bytes Flags Operation S rp1 word (saddrp) word sfrp word rp rp1 AX (saddrp) (saddrp) AX (saddrp) (saddrp) AX sfrp sfrp AX rp1 (addr16) (addr16) rp1 Z AC P/V CY Mnemonic Operand rp1, #word saddrp, #word sfrp, #word rp, rp1 AX, saddrp saddrp, AX 16-bit data transfer MOVW saddrp, saddrp AX, sfrp sfrp, AX rp1, !addr16 !addr16, rp1 AX, mem mem, AX AX, saddrp AX, sfrp XCHW saddrp, saddrp rp,rp1 AX, mem A, #byte saddr, #byte sfr, #byte r, r1 ADD A, saddr A, sfr saddr, saddr 8-bit opration A, mem mem, A A, #byte saddr, #byte sfr, #byte r, r1 ADDC A, saddr A, sfr saddr, saddr A, mem mem, A 3 4 4 2 2 2 3 2 2 4 4 2-4 AX (mem) 2-4 (mem) AX 2 3 3 2 AX (saddrp) AX sfrp (saddrp) (saddrp) rp rp1 2-4 AX (mem) 2 3 4 2 2 3 3 A, CY A + byte (saddr), CY (saddr) + byte sfr, CY sfr + byte r, CY r + r1 A, CY A + (saddr) A, CY A + sfr (saddr), CY (saddr) + (saddr) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x 2-4 A, CY A + (mem) 2-4 (mem), CY (mem) + A 2 3 4 2 2 3 3 A, CY A + byte + CY (saddr), CY (saddr) + byte + CY sfr, CY sfr + byte + CY r, CY r + r1 + CY A, CY A + (saddr) + CY A, CY A + sfr + CY (saddr), CY (saddr) + (saddr) + CY 2-4 A, CY A + (mem) + CY 2-4 (mem), CY (mem) + A + CY 51 PD78323, 78324 Instruction Group Bytes Flags Operation S A, CY A - byte (saddr), CY (saddr) - byte sfr, CY sfr - byte r, CY r - r1 A, CY A - (saddr) A, CY A - sfr (saddr), CY (saddr) - (saddr) x x x x x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x x x x x x x AC P/V CY x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V P P P P P P P P P x x x x x x x x x x x x x x x x x x Mnemonic Operand A, #byte saddr, #byte sfr, #byte r, r1 SUB A, saddr A, sfr saddr, saddr A, mem mem, A A, #byte saddr, #byte sfr, #byte 8-bit opration r, r1 SUBC A, saddr A, sfr saddr, saddr A, mem mem, A A, #byte saddr, #byte sfr, #byte r, r1 AND A, saddr A, sfr saddr, saddr A, mem mem, A 2 3 4 2 2 3 3 2-4 A, CY A - (mem) 2-4 (mem), CY (mem) - A 2 3 4 2 2 3 3 A, CY A - byte - CY (saddr), CY (saddr) - byte - CY sfr, CY sfr - byte - CY r, CY r - r1 - CY A, CY A - (saddr) - CY A, CY A - sfr - CY (saddr), CY (saddr) - (saddr) - CY 2-4 A, CY A - (mem) - CY 2-4 (mem), CY (mem) - A - CY 2 3 4 2 2 3 3 A A byte (saddr) (saddr) byte sfr sfr byte r r r1 A A (saddr) A A sfr (saddr) (saddr) (saddr) 2-4 A A (mem) 2-4 (mem) (mem) A 52 PD78323, 78324 Instruction Group Bytes Flags Operation S A A byte (saddr) (saddr) byte sfr sfr byte r r r1 A A (saddr) A A sfr (saddr) (saddr) (saddr) x x x x x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x AC P/V CY P P P P P P P P P P P P P P P P P P V V V V V V V V V x x x x x x x x x Mnemonic Operand A, #byte saddr, #byte sfr, #byte r, r1 OR A, saddr A, sfr saddr, saddr A, mem mem, A A, #byte saddr, #byte sfr, #byte 8-bit opration r, r1 XOR A, saddr A, sfr saddr, saddr A, mem mem, A A, #byte saddr, #byte sfr, #byte r, r1 CMP A, saddr A, sfr saddr, saddr A, mem mem, A 2 3 4 2 2 3 3 2-4 A A (mem) 2-4 (mem) (mem) A 2 3 4 2 2 3 3 A A byte (saddr) (saddr) byte sfr sfr byte r r r1 A A (saddr) A A sfr (saddr) (saddr) (saddr) 2-4 A A (mem) 2-4 (mem) (mem) A 2 3 4 2 2 3 3 A - byte (saddr) - byte sfr - byte r - r1 A - (saddr) A - sfr (saddr) - (saddr) 2-4 A - (mem) 2-4 (mem) - A 53 PD78323, 78324 Instruction Group Bytes Flags Operation S AX, CY AX + word (saddrp), CY (saddrp) + word sfrp, CY sfrp + word rp, CY rp + rp1 AX, CY AX + (saddrp) AX, CY AX + sfrp (saddrp), CY (saddrp) + (saddrp) AX, CY AX - word (saddrp), CY (saddrp) - word sfrp, CY sfrp - word rp, CY rp - rp1 AX, CY AX - (saddrp) AX, CY AX - sfrp (saddrp), CY (saddrp) - (saddrp) AX - word (saddrp) - word sfrp - word rp - rp1 AX - (saddrp) AX - sfrp (saddrp) - (saddrp) AX A x r1 AX(quotient), r1(remainder) AX / r1 AX(higher 16 bits), rp1(lower 16 bits) x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x AC P/V CY x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x x x x Mnemonic Operand AX, #word saddrp, #word sfrp, #word ADDW rp, rp1 AX, saddrp AX, sfrp saddrp, saddrp AX, #word saddrp, #word 16-bit opration sfrp, #word SUBW rp, rp1 AX, saddrp AX, sfrp saddrp, saddrp AX, #word saddrp, #word sfrp, #word CMPW rp, rp1 AX, saddrp AX, sfrp saddrp, saddrp Multiplication/division MULU DIVUM MULUW r1 r1 rp1 3 4 5 2 2 3 3 3 4 5 2 2 3 3 3 4 5 2 2 3 3 2 2 2 AX x rp1 AXDE(quotient), rp1(remainder) AXDE / rp1 AX(higher 16 bits), rp1(lower 16 bits) DIVUX rp1 rp1 2 Signed multiplication MULW 2 AX x rp1 54 PD78323, 78324 Instruction Group Mnemonic Operand Bytes Flags Operation S r1 r1 + 1 (saddr) (saddr) + 1 r1 r1 - 1 (saddr) (saddr) - 1 rp2 rp2 + 1 (saddrp) (saddrp) + 1 rp2 rp2 - 1 (saddrp) (saddrp) - 1 (CY, r17 r10, r1m-1 r1m) x n times (CY, r10 r17, r1m+1 r1m) x n times (CY r10, r17 CY, r1m-1 r1m) x n times (CY r17, r10 CY, r1m+1 r1m) x n times (CY r10, r17 0, r1m-1 r1m) x n times (CY r17, r10 0, r1m+1 r1m) x n times (CY rp10, rp115 0, rp1m-1 rp1m) x n times (CY rp115, rp10 0, rp1m+1 rp1m) x n times Z x x x x AC P/V CY x x x x V V V V r1 INC Increase/decrease saddr r1 DEC saddr rp2 INCW saddrp rp2 DECW ROR ROL RORC ROLC SHR Shift-rotate SHL SHRW SHLW saddrp r1, n r1, n r1, n r1, n r1, n r1, n rp1, n rp1, n 1 2 1 2 1 3 1 3 2 2 2 2 2 2 2 2 x x x x P P P P x x x x x x x x 0 0 0 0 P P P P x x x x x x x x A3-0 (rp1)3-0, ROR4 [rp1] 2 (rp1)7-4 A3-0, (rp1)3-0 (rp1)7-4 A3-0 (rp1)7-4, ROL4 [rp1] 2 (rp1)3-0 A3-0, (rp1)7-4 (rp1)3-0 BCD calibration ADJBA 2 ADJBS Decimal Adjust Accumulator x x x P x Data conversion CVTBW 1 When A7 = 0, X A, A 00H When A7 = 1, X A, A FFH 55 PD78323, 78324 Instruction Group Bytes Flags Operation S CY (saddr.bit) CY sfr.bit CY A.bit CY X.bit CY PSWH.bit CY PSWL.bit (saddr.bit) CY sfr.bit CY A.bit CY X.bit CY PSWH.bit CY PSWL.bit CY CY CY (saddr.bit) CY CY (saddr.bit) CY CY sfr.bit CY CY sfr.bit CY CY A.bit CY CY A.bit CY CY X.bit CY CY X.bit CY CY PSWH.bit CY CY PSWH.bit CY CY PSWL.bit CY CY PSWL.bit CY CY (saddr.bit) CY CY (saddr.bit) CY CY sfr.bit CY CY sfr.bit CY CY A.bit CY CY A.bit CY CY X.bit CY CY X.bit CY CY PSWH.bit CY CY PSWH.bit CY CY PSWL.bit CY CY PSWL.bit x x x x x x x x x x x x x x x x x x x x x x x x Z AC P/V CY x x x x x x Mnemonic Operand CY, saddr. bit CY, sfr. bit CY, A. bit CY, X. bit CY, PSWH. bit CY, PSWL. bit MOV1 saddr. bit, CY sfr. bit, CY A. bit, CY X. bit, CY PSWH. bit, CY PSWL. bit, CY CY, saddr. bit CY, /saddr. bit CY, sfr. bit CY, /sfr. bit Bit manipulation CY, A. bit AND1 CY, /A. bit CY, X. bit CY, /X. bit CY, PSWH. bit CY, /PSWH. bit CY, PSWL. bit CY, /PSWL. bit CY, saddr. bit CY, /saddr. bit CY, sfr. bit CY, /sfr. bit CY, A. bit CY, /A. bit OR1 CY, X. bit CY, /X. bit CY, PSWH. bit CY, /PSWH. bit CY, PSWL. bit CY, /PSWL. bit 3 3 2 2 2 2 3 3 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 2 56 PD78323, 78324 Instruction Group Bytes Flags Operation S CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY X.bit CY CY PSWH.bit CY CY PSWL.bit (saddr.bit) 1 sfr.bit 1 A.bit 1 X.bit 1 PSWH.bit 1 PSWL.bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 X.bit 0 PSWH.bit 0 PSWL.bit 0 (saddr.bit) (saddr.bit) sfr.bit sfr.bit A.bit A.bit X.bit X.bit PSWH.bit PSWH.bit PSWL.bit PSWL.bit CY 1 CY 0 CY CY x x x x x 1 0 x x x x x x x x x x x Z AC P/V CY x x x x x x Mnemonic Operand CY, saddr. bit CY, sfr. bit CY, A. bit XOR1 CY, X. bit CY, PSWH. bit CY, PSWL. bit saddr. bit sfr. bit A. bit SET1 X. bit PSWH. bit Bit manipulation PSWL. bit saddr. bit sfr. bit A. bit CLR1 X. bit PSWH. bit PSWL. bit saddr. bit sfr. bit A. bit NOT1 X. bit PSWH. bit PSWL. bit SET1 CLR1 NOT1 CY CY CY 3 3 2 2 2 2 2 3 2 2 2 2 2 3 2 2 2 2 3 3 2 2 2 2 1 1 1 57 PD78323, 78324 Instruction Group Mnemonic Operand Bytes Flags Operation S (SP-1) (PC+3)H, (SP-2) (PC+3)L, PC addr16, SP SP-2 (SP-1) (PC+2)H, (SP-2) (PC+2)L, PC15-1100001, PC10-0addr11,SPSP-2 (SP-1) (PC+1)H, (SP-2) (PC+1)L, PCH(TPF, 00000000, addr5+1), PCL(TPF, 00000000, addr5), SPSP-2 (SP-1) (PC+2)H, (SP-2) (PC+2)L, PCH rp1H, PCL rp1L, SP SP-2 (SP-1) (PC+2)H, (SP-2) (PC+2)L, PCH (rp1+1), PCL (rp1), SP SP-2 (SP-1) PSWH, (SP-2) PSWL (SP-3) (PC+1)H, (SP-4) (PC+1)L, PCL (003EH), PCH (003FH), SP SP-4 IE 0 PCL (SP), PCH (SP+1), SP SP+2 PCL (SP), PCH (SP+1) PSWL (SP+2), PSWH (SP+3) SP SP+4 PCL (SP), PCH (SP+1) PSWL (SP+2), PSWH (SP+3) SP SP+4 (SP-1) sfrH (SP-2) sfrL SP SP-2 {(SP-1)postH, (SP-2) postL,SPSP-2} x n timesNote (SP-1)PSWH, (SP-2)PSWL, SPSP-2 {(UP-1)postH, (UP-2)postL, UPUP-2} x n timesNote sfrL (SP) sfrH (SP+1) SP SP+2 {postL (SP), postH (SP+1), SPSP+2} x n timesNote PSWL(SP), PSWH(SP+1), SPSP+2 {postL (UP), postH (UP+1), UPUP+2} x n timesNote SP word SP AX AX SP SP SP+1 SP SP-1 (pin level) (signal level before output buffer) A (pin level) (signal level before output buffer) x x x x P P R R R R R R R R R R Z AC P/V CY CALL CALLF !addr16 !addr11 3 2 1 CALLT [addr5] rp1 Call-return CALL [rp1] 2 2 BRK 1 RET RETB 1 1 RETI 1 R R R R R sfrp PUSH post PSW PUSHU Stack manipulation post sfrp POP post PSW POPU post SP, #word MOVW SP, AX AX, SP INCW DECW Special CHKL CHKLA SP SP sfr sfr 3 2 1 2 3 2 1 2 4 2 2 2 2 3 3 Note n indicates the number of registers described as post. 58 PD78323, 78324 Instruction Group Bytes Flags Operation S PC addr16 PCH rp1H, PCL rp1L PCH (rp1+1), PCL (rp1) PC PC+2+jdisp8 PC PC+2+jdisp8 if CY=1 Z AC P/V CY Mnemonic Operand Unconditional branch !addr16 BR rp1 [rp1] $ addr16 BC BL BNC $ addr16 BNL BZ $ addr16 BE BNZ $ addr16 BNE BV $ addr16 BPE BNV $ addr16 BPO BN BP $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 saddr. bit, $ addr16 sfr. bit, $ addr16 BT A. bit, $ addr16 X. bit, $ addr16 PSWH. bit, $ addr16 PSWL. bit, $ addr16 saddr. bit, $ addr16 sfr. bit, $ addr16 A. bit, $ addr16 BF X. bit, $ addr16 PSWH. bit, $ addr16 PSWL. bit, $ addr16 $ addr16 3 2 2 2 2 2 PC PC+2+jdisp8 if CY=0 2 PC PC+2+jdisp8 if Z=1 2 PC PC+2+jdisp8 if Z=0 2 PC PC+2+jdisp8 if P/V=1 2 2 2 3 3 3 3 3 3 3 4 3 3 3 3 4 4 3 3 3 3 PC PC+2+jdisp8 if P/V=0 PC PC+2+jdisp8 if S=1 PC PC+2+jdisp8 if S=0 PC PC+3+jdisp8 if (P/V S) Z=0 PC PC+3+jdisp8 if P/V S=0 PC PC+3+jdisp8 if P/V S=1 PC PC+3+jdisp8 if (P/V S) Z=1 PC PC+3+jdisp8 if Z CY=0 PC PC+3+jdisp8 if Z CY=1 PC PC+3+jdisp8 if (saddr.bit)=1 PC PC+4+jdisp8 if sfr.bit=1 PC PC+3+jdisp8 if A.bit=1 PC PC+3+jdisp8 if X.bit=1 PC PC+3+jdisp8 if PSWH.bit=1 PC PC+3+jdisp8 if PSWL.bit=1 PC PC+4+jdisp8 if (saddr.bit)=0 PC PC+4+jdisp8 if sfr.bit=0 PC PC+3+jdisp8 if A.bit=0 PC PC+3+jdisp8 if X.bit=0 PC PC+3+jdisp8 if PSWH.bit=0 PC PC+3+jdisp8 if PSWL.bit=0 Conditional branch BGT BGE BLT BLE BH BNH 59 PD78323, 78324 Instruction Group Bytes Flags Operation S PC PC+4+jdisp8 if (saddr.bit)=1 Z AC P/V CY Mnemonic Operand saddr.bit, $ addr16 4 then reset (saddr.bit) PC PC+4+jdisp8 if sfr.bit=1 sfr.bit, $ addr16 4 then reset sfr.bit PC PC+3+jdisp8 if A.bit=1 3 then reset A.bit PC PC+3+jdisp8 if X.bit=1 A.bit, $ addr16 BTCLR X.bit, $ addr16 3 then reset X.bit PC PC+3+jdisp8 if PSWH.bit=1 PSWH.bit, $ addr16 3 then reset PSWH.bit PC PC+3+jdisp8 if PSWL.bit=1 PSWL.bit, $ addr16 Conditional branch 3 then reset PSWL.bit PC PC+4+jdisp8 if (saddr.bit)=0 x x x x x saddr.bit, $ addr16 4 then set (saddr.bit) PC PC+4+jdisp8 if sfr.bit=0 sfr.bit, $ addr16 4 then set sfr.bit PC PC+3+jdisp8 if A.bit=0 A.bit, $ addr16 BFSET X.bit, $ addr16 3 then set A.bit PC PC+3+jdisp8 if X.bit=0 3 then set X.bit PC PC+3+jdisp8 if PSWH.bit=0 PSWH.bit, $ addr16 3 then set PSWH.bit PC PC+3+jdisp8 if PSWL.bit=0 PSWL.bit, $ addr16 3 then set PSWL.bit r2 r2-1, x x x x x r2, $ addr16 DBNZ saddr, $ addr16 2 then PC PC+2+jdisp8 if r20 (saddr) (saddr)-1, 3 then PC PC+3+jdisp8 if (saddr) 0 PCH R5, PCL R4, R7 PSWH, Context switching BRKCS RBn 2 R6PSWL, RBS2-0 n, RSS0, IE0 PCH R5, PCL R4, R5, R4 addr16, 3 PSWH R7, PSWL R6 PCH R5, PCL R4, R5, R4 addr16, R R R R R RETCS !addr16 RETCSB !addr16 4 PSWH R7, PSWL R6 R R R R R 60 PD78323, 78324 Instruction Group Bytes Flags Operation S (DE + ) A, C C-1 Z AC P/V CY Mnemonic Operand [DE + ], A MOVM [DE - ], A 2 End if C=0 (DE - ) A, C C-1 2 End if C=0 (DE + ) (HL + ), C C-1 2 End if C=0 (DE - ) (HL - ), C C-1 [DE + ], [HL + ] MOVBK [DE - ], [HL - ] 2 End if C=0 (DE + ) A, C C-1 [DE + ], A XCHM [DE - ], A 2 End if C=0 (DE - ) A, C C-1 2 End if C=0 (DE + ) (HL + ), C C-1 [DE + ], [HL + ] XCHBK [DE - ], [HL - ] 2 End if C=0 (DE - ) (HL - ), C C-1 2 End if C=0 (DE + ) - A, C C-1 [DE + ], A String CMPME [DE - ], A 2 End if C=0 or Z=0 (DE - ) - A, C C-1 2 End if C=0 or Z=0 (DE + ) - (HL + ), C C-1 x x x V x x x x V x [DE + ], [HL + ] CMPBKE [DE - ], [HL - ] 2 End if C=0 or Z=0 (DE - ) - (HL - ), C C-1 2 End if C=0 or Z=0 (DE + ) - A, C C-1 x x x V x x x x V x [DE + ], A CMPMNE [DE - ], A 2 End if C=0 or Z=1 (DE - ) - A, C C-1 2 End if C=0 or Z=1 (DE + ) - (HL + ), C C-1 x x x V x x x x V x [DE + ], [HL + ] CMPBKNE [DE - ], [HL - ] 2 End if C=0 or Z=1 (DE - ) - (HL - ), C C-1 2 End if C=0 or Z=1 (DE + ) - A, C C-1 x x x V x x x x V x [DE + ], A CMPMC [DE - ], A 2 End if C=0 or CY=0 (DE - ) - A, C C-1 2 End if C=0 or CY=0 x x x V x x x x V x 61 PD78323, 78324 Instruction Group Bytes Flags Operation S (DE + ) - (HL + ), C C-1 x Z x AC P/V CY x V x Mnemonic Operand [DE + ], [HL + ] CMPBKC [DE - ], [HL - ] 2 End if C=0 or CY=0 (DE - ) - (HL - ), C C-1 x x x V x 2 End if C=0 or CY=0 (DE + ) - A, C C-1 2 End if C=0 or CY=1 (DE - ) - A, C C-1 [DE + ], A String CMPMNC [DE - ], A x x x V x 2 End if C=0 or CY=1 (DE + ) - (HL + ), C C-1 x x x V x [DE + ], [HL + ] CMPBKNC [DE - ], [HL - ] STBC, #byte MOV CPU control SWRS SEL NOP EI DI RBn RBn, ALT WDM, #byte 2 End if C=0 or CY=1 (DE - ) - (HL - ), C C-1 2 End if C=0 or CY=1 4 4 1 2 2 1 1 1 STBC byteNote WDM byteNote RSS RSS RBS2 - 0 n, RSS 0 RBS2 - 0 n, RSS 1 No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) x x x V x x x x V x Note If the operation code of STBC register and WDM register operation instructions is abnormal, an operation code trap interrupt is generated. Operation in the eent of trap: (SP-1) PSWH, (SP-2) PSWL, (SP-3) (PC-4)H, (SP-4) (PC-4)L, PCL (003CH), PCH (003DH), SP SP-4, IE 0 62 PD78323, 78324 9. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 C) Parameter Symbol VDD Supply voltage voltage AVDD AVSS Input voltage Output voltage Output current low VI VO All output pins Note 1 Test Conditions Rating -0.5 to + 7.0 -0.5 to VDD + 0.5 -0.5 to + 0.5 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 4.0 90 -1.0 -20 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to VDD + 0.3 -0.5 to AVDD + 0.3 -10 to + 70 -65 to + 150 Unit V V V V V mA mA mA mA V IOL IOH All output pins total All output pins All output pins total Output current high Analog input voltage A/D converter reference input voltage Operating ambient temperature Storage temperature VIAN Note 2 AVDD > VDD VDD AVDD AVDD > VDD VDD AVDD AVREF TA Tstg V C C Notes 1. Except the pin described in Note 2. 2. P70/ANI0 to P77/ANI7 pins Caution If the absoute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the product may be physically damaged if any of the absolute maximum raings is exceeded. Be sure to use the product without exceeding these rarings. RECOMMENDED OPERATING CONDITION Oscillation frequency 8 MHz fXX 16 MHz TA -10 to +70 C VDD +5.0 V 10 % CAPACITANCE (TA = 25 C, VSS = VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f=1 MHz Unmeasured pins returned to 0 V. Test Conditions MIN. TYP. MAX. 10 20 20 Unit pF pF pF 63 PD78323, 78324 OSCILLATOR CHARACTERISTICS (TA = -10 to +70 C, VDD = +5 V 10 %, VSS = 0 V) Resonator Recommended Circuit Parameter MIN. MAX. Unit X2 Ceramic resonator or crystal resonator X1 VSS Oscillation frequency (fXX) 8 16 MHz C2 C1 X1 X2 X1 input frequency (fX) 8 16 MHz HCMOS Invertor External clock or X1 X2 Open X1 input rise/fall time (tXR, tXF) 0 20 ns X1 input high/low level width HCMOS Invertor (tWXH , tWXL) 25 80 ns Caution When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. * Make the wiring as short as possible. * Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. * Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. * Do not fetch signals from the oscillation circuit. 64 PD78323, 78324 RECOMMENDED OSCILLATOR CONSTANT CERAMIC RESONATOR Manufacturer Product Name Frequency [MHz] 8.0 12.0 14.74 16.0 8.0 12.0 17.74 16.0 Recommended Constant C1 [pF] C2 [pF] CSA8.00MT CSA12.0MT Murata Mfg. Co., Ltd. CSA14.74MXZ040 CSA16.00MXZ040 CST8.00MTW CST12.0MTW CST14.74MXW0C3 CST16.00MXW0C3 30 30 15 15 On-chip On-chip CRYSTAL RESONATOR Manufacturer Product Name Frequency [MHz] Recommended Constant C1 [pF] C2 [pF] HC49/U-S Kinseki Co., Ltd. HC49/U 8 to 16 10 10 65 PD78323, 78324 DC CHARACTERISTICS (TA = -10 to +70 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Input voltage low Symbol VIL VIH1 Note 1 Note 2 Test Conditions MIN. 0 2.2 TYP. MAX. 0.8 Unit V V Input voltage high VIH2 Output voltage low Output voltage high Input leakage current Output leakage current VDD supply current IDD2 Data retention voltage Data retention current VDDDR IDDDR HALT mode STOP mode VDDDR = 2.5 V STOP mode VDDDR = 5.0 V 10 % 2.5 2 10 10 50 20 45 VOL VOH ILI ILO IDD1 0.8VDD 0.45 VDD - 1.0 10 10 40 75 IOL = 2.0 mA IOH = -400 A 0 V VI VDD 0 V VO VDD Operating mode V V A A mA mA V A A Notes 1. Except the pin descried in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2,P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins. 66 PD78323, 78324 AC CHARACTERISTICS (TA = -10 to +70 C, VDD = +5 V 10 %, VSS = 0 V) Non-consecutive read/write operation (with general-purpose memory connected) Parameter System clock cycle time Address setup time (vs. ASTB) Address hold time (vs. ASTB) RD delay time from address Address float time from RD Data input time from address Data input time from RD RD delay time from ASTB Data hold time (vs. RD) Address active time from RD RD low-level width ASTB high-level width WR delay time from address Data output time from ASTB Data output time from WR WR delay time from ASTB Data setup time (vs. WR) Data hold time (vs. WR) ASTB delay time from WR WR low-level width Symbol tCYK tSAST tHSTA tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tWSTH tDAW tDSTOD tDWOD tDSTW tSODW tHWOD tDWST tWWL 42 147 32 42 147 42 0 50 147 37 85 102 40 Test Conditions MIN. 125 32 32 85 10 222 112 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 67 PD78323, 78324 tCYK Dependent Bus Timing Definition Parameter tSAST tHSTA tDAR tDAID tDRID tDSTR tDRA tWRL tWSTH tDAW tDSTOD tDSTW tSODW tHWOD tDWST tWWL Expression 0.5T - 30 0.5T - 30 T - 40 (2.5 + n) T - 90 (1.5 + n) T - 75 0.5T - 20 0.5T - 12 (1.5 + n) T - 40 0.5T - 25 T - 40 0.5T + 40 0.5T - 20 1.5T - 40 0.5T - 30 0.5T - 20 (1.5 + n) T - 40 MIN./MAX. MIN. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. 2. 3. T = tCYK = 1/fCLK (fCLK is internal system clock frequency) n indicates the number of wait cycles defined by user software. Depends on tCYK for the bus timing shown in this table only. 68 PD78323, 78324 SERIAL OPERATION (TA = -10 to +70 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Serial clock cycle time Symbol SCK output tCYSK SCK input SCK output Test Conditions Internal division by 8 External clock Internal division by 8 External clock Internal division by 8 External clock MIN. 1 1 420 420 420 420 80 80 MAX. Unit s s ns ns ns ns ns ns 210 ns Serial clock low-level width tWSKL SCK input SCK output Serial clock high-level width SI setup time (to SCK) SI hold time (from SCK) SO delay time from SCK tWSKH SCK input tSRXSK tHSKRX tDSKTX R = 1 k, C = 100 pF OTHER OPERATION (TA = -10 to +70 C, VDD = +5 V 10 %, VSS = 0 V) Parameter NMI high/low-level width INTP0 high/low-level width INTP1 high/low-level width INTP2 high/low-evel width NTP3 high/low-level width NTP4 high/low-level width INTP5 high/low-level width INTP6 high/low-level width RESET high/low-level width TI high/low-level width Symbol tWNIH, tWNIL tWI0H, tWI0L tWI1H, tWI1L tWI2H, tWI2L tWI3H, tWI3L tWI4H, tWI4L tWI5H, tWI5L tWI6H, tWI6L tWRSH, tWRSL tWTIH, tWTIL In TM1 event counter mode Test Conditions MIN. 5 8T 8T 8T 8T 8T 8T 8T 5 8T MAX. Unit s tCYK tCYK tCYK tCYK tCYK tCYK tCYK s tCYK 69 PD78323, 78324 A/D CONVERTER CHARACTERISTICS(TA = -10 to +70 C, VDD = +5 V 10 %, VSS = AVSS = 0 V, VDD - 0.5 V AVDD VDD) Parameter Resolution Total error Note 1 4.5 V AVREF AVDD 3.4 V AVREF AVDD Quantization error Conversion time Sampling time Zero scale error Note 1 tCONV tSAMP 4.5 V AVREF AVDD 3.4 V AVREF AVDD Full scale error Note 1 4.5 V AVREF AVDD 3.4 V AVREF AVDD Non-linear error Note 1 Symbol Test Conditions MIN. 10 TYP. MAX. Unit bit 0.4 % 0.7 1/2 144 24 1.5 1.5 1.5 1.5 1.5 1.5 -0.3 3.4 1.0 2.0 2.5 4.5 2.5 4.5 2.5 4.5 AVDD AVDD 3.0 6.0 10 50 %FSR %FSR LSB tCYK tCYK LSB LSB LSB LSB LSB LSB V V mA mA 4.5 V AVREF AVDD 3.4 V AVREF AVDD Analog input voltage Reference voltage AVREF current AVDD supply current A/D converter data retention current Note 2 VIAN AVREF AIREF AIDD AVDDR = 2.5 V AIDDR STOP mode AVDDR = 5 V 10 % 2.0 10 A A Notes 1. Quantization error excluded. 2. When -0.3 V VIAN 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits. When AVREF VIAN AVDD, the conversion result is 3FFH. 70 PD78323, 78324 Non-Consecutive Read Operation tCYK (CLK) P50-P57 (Output) tDAID tSAST P40-P47 (Input/ Output) ASTB (Output) Hi-Z Lower Address (Output) Higher Address Higher Address Hi-Z Data (Input) Hi-Z Lower Address (Output) Hi-Z tWSTH tHRID tHSTA tFRA RD (Output) tDSTR tDRID tDAR tWRL tDRA Non-Consecutive Write Operation (CLK) P50-P57 (Output) tSAST P40-P47 (Input/ Output) tWSTH ASTB (Output) tHSTA tDSTOD WR (Output) tDSTW Lower Address (Output) Higher Address Higher Address Undefined Data (Output) Lower Address (Output) tHWOD tDWST tDWOD tDAW tWWL tSODW 71 PD78323, 78324 Serial Operation tCYSK tWSKL SCK tDSKTX SO tWSKH SI tSRXSK tHSKRX Interrupt Input Timing tWNIH tWNIL NMI 0.8VDD 0.8V tWInH tWInL INTPn Remarks n = 0 to 6 72 PD78323, 78324 Reset Input Timing tWRSH tWRSL 0.8VDD RESET 0.8V TI Pin Input Timing tWTIH tWTIL TI 73 PD78323, 78324 10. PACKAGE DRAWINGS 74 PIN PLASTIC QFP ( 20) A B F2 56 57 38 37 detail of lead end C D S F1 74 1 19 18 G1 G2 H I M J K P N NOTE L ITEM A B C D F1 F2 G1 G2 H I J K L M N P Q R S MILLIMETERS 23.20.4 20.00.2 20.00.2 23.20.4 2.0 1.0 2.0 1.0 0.400.10 0.20 1.0 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 3.7 0.10.1 55 4.0 MAX. INCHES 0.913 +0.017 -0.016 0.787 +0.009 -0.008 0.787 +0.009 -0.008 0.913 +0.017 -0.016 0.079 0.039 0.079 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.146 0.0040.004 55 0.158 MAX. S74GJ-100-5BJ-3 Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. 74 M Q R PD78323, 78324 68 PIN PLASTIC QFJ ( 950 mil) A B F E U G H J T K M N M Q I P C D 68 1 P68L-50A1-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K M N P Q T U MILLIMETERS 25.2 0.2 24.20 24.20 25.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 MIN. 3.4 1.27 (T.P.) 0.40 1.0 0.12 23.12 0.20 0.15 R 0.8 0.20 +0.10 -0.05 INCHES 0.992 0.008 0.953 0.953 0.992 0.008 0.076+0.007 -0.006 0.024 0.173+0.009 -0.008 0.110+0.009 -0.008 0.035 MIN. 0.134 0.050 (T.P.) 0.016+0.004 -0.005 0.005 0.910+0.009 -0.008 0.006 R 0.031 0.008+0.004 -0.002 75 PD78323, 78324 11. RECOMMENDED SOLDERING CONDITIONS The PD78323 and 78324 should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (IE1-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 11-1. Soldering Conditions for Surface Mount Type PD78323GJ-5BJ : 74-pin plastic QFP (20 x 20 mm) PD78324GJ-xxx-5BJ : 74-pin plastic QFP (20 x 20 mm) Recommended Condition Symbol Soldering Method Soldering Conditions Package peak temperature: 230 C, Time: 30 sec. max. (at 210 C or above) Number of times: Once, Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125 C) Package peak temperature: 215 C, Time: 40 sec. max. (at 200 C or above) Number of times: Once, Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125 C) Pin temperature: 300 C max, Time: 3 sec. max. (Per side of the device) Infrared reflow IR30-107-1 VPS VP15-107-1 Pin part heating PD78323LP : 68-pin plastic QFJ ( PD78324LP-xxx : 68-pin plastic QFJ ( Soldering Method 950 mil) 950 mil) Recommended Condition Symbol Soldering Conditions Package peak temperature: 235 C, Time: 30 sec. max. (at 210 C or above) Number of times: twice or less, Time limit: 7 daysNote (thereafter 36 hours prebaking required at 125 C) Infrared reflow IR30-367-2 VP15-367-2 VPS Pin part heating Note For the storage period after dry-pack decompression, storage conditions are max. 25 C, 65 % RH. Caution Use more than one soldering method should be avoided (except in the case of pin part heating). 76 APPENDIX A. LIST OF 78K/III SERIES PRODUCTS (1/2) PD78324 Basic instruction Minimum instruction execution time ROM Internal memory RAM Memory space Input I/O lines Output I/O 39 21 16 (including 8 analog inputs) -- 39 21 40 32768 x 8 bits 1024 x 8 bits PD78323 111 PD78322 PD78320 PD78312A 96 PD78310A 250 ns (at 16 MHz operation) -- 16384 x 8 bits 640 x 8 bits 64K bytes -- 500 ns (at 12 MHz operation) 8192 x 8 bits 256 x 8 bits -- 12 (including 4 analog inputs) 1 24 Pulse unit Real-time pulse unit * 18/16-bit free running timer x 1 * 16-bit timer/event counter x 1 Real-time pulse unit * 16-bit compare register x 6 * 18/16-bit free running timer x 1 * 18-bit capture register x 4 * 16-bit timer/event counter x 1 * 18-bit capture/compare register x 2 * 16-bit compare register x 6 * Real-time output port x 8 * 18-bit capture register x 4 * 18-bit capture/compare register x 2 * Real-time output port x 8 mode) function available Multi-function pulse I/O unit * 16-bit presettable up-/down-counter x2 * 16-bit free running counter capture function x 2 * 16-bit interval timer x 2 * High-precision PWM output x 2 * Real-time output port : 4 bits x 2 Count unit mode 4 (4-multiplication Counter start function by interval timer external trigger available * * * * Dedicated on-chip baud rate generator UART ...1 channel SBI ...1 channel 3-wire serial I/O * 8 bits (full-duplex transmission/ reception) * Dedicated on-chip baud rate generator * 2 transfer modes (asynchronous mode, I/O interface mode) Four 8-bit resolution inputs * 4 external, 13 internal * 8-level programmable priority order Serial communication interface PD78323, 78324 A/D converter Eight 10-bit resolution inputs * 8 external, 14 internal (shared with external 2) * 3-level programmable priority order * 3 processing methods (vectored interrupt, context switching and macro service functions) Interrupt 77 78 LIST OF 78K/III SERIES PRODUCTS (2/2) PD78324 Test source Internal : 1 Following instructions added for PD78312 and 78310 * MOVW rp1, !addr16 instruction * MOVW !addr16, rp1 instruction PD78323 PD78322 PD78320 PD78312A PD78310A Instruction set Instructions for PD78312 and 78310 significantly increased. * On-chip watchdog timer * Standby function (STOP/HALT) Others -- * 20-bit time base counter * Pseudo static RAM refresh function 950 mil) * 74-pin plastic QFP (20 x 20 mm) * 80-pin plastic QFP (14 x 20 mm) * 68-pin plastic QFJ ( * * * * 64-pin 64-pin 64-pin 68-pin plastic plastic plastic plastic shurink DIP (750 mil) QFP (14 x 20 mm) QUIP QFJ ( 950 mil) Package * 68-pin plastic QFJ ( 950 mil) * 74-pin plastic QFP (20 x 20 mm) PD78323, 78324 PD78323, 78324 APPENDIX B. TOOLS B.1 DEVELOPMENT TOOLS The following development tools are available for system development using the PD78324. Language Processor 78K/III series relocatable assembler (RA78K/III) Refers to the relocatable assembler which can be used commonly for the 78K/III series. Equipped with the macro function, the relocatable assembler is aimed at improved development efficiency. The assembler is also accompanied by the structured assembler which can describe the program control structure explicitly, thus making it possible to improve the productivity and the maintainability of the program. Host machine OS PC-9800 series IBM PC/ATTM and its compatible machine HP9000 series 700TM SPARCstationTM NEWSTM MS-DOSTM 5-inch 2HD 3.5-inch 2HC PC DOSTM 5-inch 2HC HP-UXTM SunOSTM NEWS-OSTM DAT Cartridge tape (QIC-24) Supply medium 3.5-inch 2HD Part number S5A13RA78K3 S5A10RA78K3 S7B13RA78K3 S7B10RA78K3 S3P16RA78K3 S3K15RA78K3 S3R15RA78K3 78K/III series C compiler (CC78K/III) Refers to the C compiler which can be commonly used in the 78K/III series. This compiler is a program converting the programs written in the C language to those object codes which are executable by microcontrollers. When using this compiler, the 78K/III series relocatable assembler (RA78K/III) is required. Part number OS PC-9800 series IBM PC/AT and its compatible machine HP9000 series 700 SPARCstation NEWS MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC HP-UX SunOS NEWS-OS DAT Cartridge tape (QIC-24) Supply medium 3.5-inch 2HD Host machine S5A13CC78K3 S5A10CC78K3 S7B13CC78K3 S7B10CC78K3 S3P16CC78K3 S3K15CC78K3 S3R15CC78K3 Remark Relocatable assembler and C compiler operations are assured only on the host machine and the OS above. 79 PD78323, 78324 PROM Writing Tools This PROM programmer allows programming, in standalone mode or via operation from a host computer, of a singlechip microcontroller with on-chip PROM by connection of the board provided and a separately available programmer adapter. It can program typical 256K-bit to 4M-bit PROMs. PG-1500 UNISITE 2900 Hardware PROM programmer made by Data I/O Japan Corporation. PA-78P324GJ PA-78P324KC PA-78P324KD PA-78P324LP PROM programmer adapters for writing programs to the PD78P324 with a general PROM programmer such as the PG-1500. PA-78P324GJ ... For PD78P324GJ PA-78P324KC ... For PD78P324KC PA-78P324KD ... For PD78P324KD PA-78P324LP ... For PD78P324LP Connects PG-1500 and host machine via a serial and parallel interface, and controls the PG-1500 on the host machine. Ordering Code (Product Name) Host Machine OS Software PG-1500 controller PC-9800 series IBM PC/AT and its compatible machine MS-DOS Supply Medium 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500 Remark Operation of the PG-1500 controller is guaranteed only on the host machines and operating systems quoted above. 80 PD78323, 78324 Debugging Tools These are the in-circuit emulators which can be used for the development and debugging of application systems. Debugging is performed by connecting them to a host machine. The IE-78327-R can be used commonly for both the PD78322 subseries and the PD78328 subseries. The IE-78320-R can be used for the PD78322 subseries. These are the emulation probes for connecting the IE-78327-R or IE-78320-R to a target system. EP-78320GJ-R: for 74-pin plastic QFP EP-78320L-R: for 68-pin plastic QFJ This program is for controlling the IE-78327-R from a host machine. It can execute commands automatically, thus enabling more efficient debugging. Host machine OS IE-78327-R control program (IE controller) PC-9800 series IBM PC/AT and its compatible machine MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number IE-78327-R IE-78320-RNote EP-78320GJ-R EP-78320L-R Hardware S5A13IE78327 S5A10IE78327 S7B13IE78327 S7B10IE78327 This program is for controlling the IE-78320-R from a host machine. It can execute commands automatically, thus enabling more efficient debugging. Host machine Software IE-78320-R control programNote (IE controller) PC-9800 series IBM PC/AT and its compatible machine OS MS-DOS 5-inch 2HD PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13IE78320 S5A10IE78320 S7B10IE78320 Remarks 1. The operation of each software is assured only on the host machine and the OS above. 2. PD78322 subseries: PD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1), 78320(A2), 78322(A), 78322(A1), 78322(A2), 78323(A), 78323(A1), 78323(A2), 78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1), 78P324(A2) PD78328 subseries: PD78327, 78328, 78P328, 78327(A), 78328(A) Note The existing product IE-78320-R is a maintenance product. If you are going to newly purchase an in-circuit emulator, please use the alternative product IE-78327-R. 81 82 Host machine PC-9800 series IBM PC/AT or its compatible machine RS-232-C Development Tool Configurations Emulation probes Software IE-78327-R in-circuit emulator RS-232-C PROM programmer EP-78320GJ-R EP-78320L-R Relocatable assembler PG-1500 (With structured assembler) controller IE controller Socket for connecting the emulation probe and the target system Note PG-1500 EV-9200G-74 Socket for plastic QFJ PROM-incorporated products PD78P324GJ PD78P324LP PD78P324KC PD78P324KD + + + Programmer adapters Target system PA-78P324KC PA-78P324KD PA-78P324GJ PA-78P324LP PD78323, 78324 Note The socket is supplied with the emulation probe. Remarks 1. It is also possible to use the host machine and the PG-1500 by connecting them directly by the RS-232-C. 2. In the diagram above, representative software supply media and 3.5-inch FDs. PD78323, 78324 B.2 EVALUATION TOOLS To evaluate the functions of the PD78324, the following tools are made available. Part Number Host Machine Function By connecting to a host machine, it is possible to evaluate the functions equipped by the PD78324 in a simple manner. The command system of this product basically conforms to that of IE-78327-R and IE-78320-R. Therefore, it is easy to move to the development work of application systems by IE-78327-R or IE78320-R. In addition a turbo access manager (PD71P301)Note can be mounted on the board. EB-78320-98 PC-9800 series EB-78320-PC IBM PC/AT or its compatible machine Note The turbo access manager (PD71P301) is a maintenance product. Cautions 1. This product is not a development tool of PD78324 application systems. 2. This product is not equipped with the emulation function for executing the ROM incorporated in the PD78324. B.3 EMBEDDED SOFTWARE The following embedded software programs are available to perform program development and maintenance more efficiently. Eeal-time OS The RX78K/III is designed to provide a multi-task environment in the field of control application where real-time operation is required. By using this real-time OS, the performance of the whole system can be improved by allocating CPU's idle time to other processings. The RX78K/III provides the system call based on the ITRON specifications. The RX78K/III package provides tools (configurators) for creating RX78K/III's nucleus and multiple information table. Real-time OS (RX78K/III) Host machine OS PC-9800 series MS-DOS 5-inch 2HD IBM PC/AT and its compatible machine 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13RX78320 S5A10RX78320 S7B13RX78320 S7B10RX78320 Caution To purchase the operating system above, you need to fill in a purchase application form beforehand and sign a contract allowing you to use the software. Remark When using the real-time OS RX78K/III, you need the assembler package RA78K/III (optional) as well. 83 PD78323, 78324 Fuzzy Inference Development Support System This program supports inputting/editing/evaluating (through simulation) of the fuzzy knowledge data (fuzzy rules and membership functions). Host machine OS Fuzzy knowledge data creation tools (FE9000, FE9200) PC-9800 series MS-DOS 5-inch 2HD IBM PC/AT and its compatible machine 3.5-inch 2HC PC DOS WinsowsTM 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13FE9000 S5A10FE9000 S7B13FE9200 S7B10FE9200 This program converts the fuzzy knowledge data obtained with fuzzy knowledge data creation tools to an assembler source program for RA78K/III. Host machine OS Translator (FT78K3)Note 3.5-inch 2HD PC-9800 series IBM PC/AT and its compatible machine MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium Part number S5A13FT78K3 S5A10FT78K3 S7B13FT78K3 S7B10FT78K3 This program executes fuzzy inference. Fuzzy inference is executed by being linked to the fuzzy knowledge data converted by the translator. Part number OS Fuzzy inference module (FI78K/III)Note PC-9800 series MS-DOS 5-inch 2HD IBM PC/AT and its compatible machine 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Host machine S5A13FI78K3 S5A10FI78K3 S7B13FI78K3 S7B10FI78K3 This is a support software program for evaluating and adjusting the fuzzy knowledge data at a hardware level by using the in-circuit emulator. Host machine OS Fuzzy inference debugger (FD78K/III) PC-9800 series MS-DOS 5-inch 2HD IIBM PC/AT and its compatible machine 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13FD78K3 S5A10FD78K3 S7B13FD78K3 S7B10FD78K3 Note Under development 84 PD78323, 78324 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 85 PD78323, 78324 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed : The customer must judge the need for license : PD78323 PD78324 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. |
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