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| 3-BIT 4:1 MUX-LATCH SY10E156 SY100E156 FEATURES s s s s s s s 900ps max. D to output Extended 100E VEE range of -4.2V to -5.5V 800ps max. LEN to output Differential outputs Asynchronous Master Reset Dual latch enables Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E156 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latches. When both LEN1 and LEN2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched. The multiplexer operation is controlled by the Select (SEL0, SEL1) signals which select one of the four bits of input data at each mux to be passed through. The MR (Master Reset) signal operates asynchronously to take all outputs to a logic LOW. BLOCK DIAGRAM PIN CONFIGURATION D2b D2a VCCO D1b D1a SEL0 SEL1 MR D0a D0b D0c D0d 4:1 MUX D E NR Q0 Q0 26 27 28 1 2 3 4 25 24 23 22 21 20 19 18 17 D2d D2c Q2 Q2 VCC Q1 Q1 VCCO Q0 D1a D1b D1c D1d D 4:1 MUX E NR Q1 Q1 VEE LEN1 LEN2 D1c PLCC TOP VIEW J28-1 16 15 14 13 12 5 6 7 8 9 10 11 D2a D2b D2c D2d SEL0 SEL1 LEN1 LEN2 MR D 4:1 MUX E NR Q2 Q2 PIN NAMES Pin D0x-D2x SEL0, SEL1 LEN1, LEN2 MR Q0-Q2 Q0-Q2 VCCO Function Input Data Select Inputs Latch Enables Master Reset True Outputs Inverted Outputs VCC to Output Rev.: C Amendment: /1 1 VCCO Q0 Issue Date: February, 1998 D1d D0a D0b D0c D0d Micrel SY10E156 SY100E156 TRUTH TABLES LEN1 L H X LEN2 L X H Latch Transparent Latched Latched SEL0 L H L H SEL1 L L H H Data a b c d DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 75 75 90 90 -- -- 75 75 90 90 -- -- 75 86 90 103 TA = +25C TA = +85C Max. 150 Unit A mA Condition -- -- Min. Typ. Max. Min. Typ. -- -- 150 -- -- Max. Min. Typ. 150 -- -- AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output D SEL0 SEL1 LEN MR Set-up Time D SEL0 SEL1 Hold Time D SEL0 SEL1 Reset Recovery Time Minimum Pulse Width, MR Within-Device Skew Rise/Fall Time 20% to 80% TA = +25C TA = +85C Max. 900 1050 900 800 825 ps 400 700 600 300 100 200 800 400 -- 275 275 300 400 -275 -300 -400 600 -- 50 475 -- -- -- -- -- -- -- -- -- 700 400 700 600 300 100 200 800 400 -- 275 275 300 400 -275 -300 -400 600 -- 50 475 -- -- -- -- -- -- -- -- -- 700 400 700 600 300 100 200 800 400 -- 275 275 300 400 -275 -300 -400 600 -- 50 475 -- -- -- ps -- -- -- -- -- -- 700 ps ps ps ps -- -- 1 -- -- -- Unit ps 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 Condition -- Min. Typ. Max. Min. Typ. Max. Min. Typ. tS tH tRR tPW tskew tr tf NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code SY10E156JC SY10E156JCTR SY100E156JC SY100E156JCTR 2 Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial Micrel SY10E156 SY100E156 28 LEAD PLCC (J28-1) Rev. 03 3 Micrel SY10E156 SY100E156 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
Price & Availability of SY10E156
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