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RF1K49086
Data Sheet August 1999 File Number
3986.5
3.5A, 30V, 0.06 Ohm, Dual N-Channel LittleFETTM Power MOSFET
This Dual N-Channel power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching convertors, motor drivers, relay drivers, and low voltage bus switches. This device can be operated directly from integrated circuits. Formerly developmental type TA49086.
Features
* 3.5A, 30V * rDS(ON) = 0.060 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RF1K49086 PACKAGE MS-012AA BRAND RF1K49086
Symbol
D1(8) D1(7)
NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4908696.
S1(1) G1(2)
D2(6) D2(5)
S2(3) G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5 1 2 3 4
8-87
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. LittleFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RF1K49086
Absolute Maximum Ratings
TA = 25oC Unless Otherwise Specified RF1K49086 30 30 20 3.5 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation TA = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 12) VGS = VDS, ID = 250A, (Figure 11) VDS = 30V, VGS = 0V VGS = 20V ID = 3.5A (Figures 9, 10) VGS = 10V VGS = 4.5V TA = 25oC TA = 150oC MIN 30 1 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 24V, ID = 3.5A, RL = 6.86 (Figure 14) Pulse Width = 1s Device mounted on FR-4 material TYP 10 30 60 45 35 13 2.3 575 275 100 MAX 3 1 50 100 0.060 0.132 50 130 45 17 2.9 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance
IGSS rDS(ON)
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJA
VDD = 15V, ID 3.5A, RL = 4.29, VGS = 10V, RGS = 25
VDS = 25V, VGS = 0V, f = 1MHz (Figure 13)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 3.5A ISD = 3.5A, dISD/dt = 100A/s MIN TYP MAX 1.25 45 UNITS V ns
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RF1K49086 Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0.8 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150 0.0 25 75 100 125 50 TA, AMBIENT TEMPERATURE (oC) 150
0.6 0.4
0.2
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
10
ZJA, NORMALIZED THERMAL IMPEDANCE
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
0.1
t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
0.01 10-3
10-2
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
IDM, PEAK CURRENT CAPABILITY (A)
TJ = MAX RATED TA = 25oC
200 100 VGS = 10V
TA = 25oC
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
ID, DRAIN CURRENT (A)
10
= I25
150 - TA 125
1
5ms 10ms 100ms
10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
0.1
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) VDSS(MAX) = 30V
1s DC 100
0.01 0.1
1
10
1 10-5
10-4
10-3
10-2
10-1
100
101
VDS, DRAIN TO SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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RF1K49086 Typical Performance Curves
(Continued)
IAS, AVALANCHE CURRENT (A)
20 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10 ID, DRAIN CURRENT (A)
25 VGS = 20V 20 VGS = 10V VGS = 5V
15
VGS = 4.5V
STARTING TJ = 25oC
10
VGS = 4V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC VGS = 3V 0 1.0 2.0 3.0 4.0 5.0 VDS, DRAIN TO SOURCE VOLTAGE (V)
STARTING TJ = 150oC 1 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100
5
0
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
25 ID(ON), ON-STATE DRAIN CURRENT (A)
25oC
rDS(ON), ON-STATE RESISTANCE (m)
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
250 VDD = 15V ID = 7.0A ID = 3.5A ID = 1.75A
20 -55oC 15 150oC
200
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
150
10
100 ID = 0.5A 50
5
0 0
0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5
3
4
5
6
7
8
9
10
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
2.0 NORMALIZED ON RESISTANCE
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 3.5A THRESHOLD VOLTAGE NORMALIZED GATE
2.0 VGS = VDS, ID = 250A
1.5
1.5
1.0
1.0
0.5
0.5
0.0 -80
-40
0
40
80
120
160
0.0 -80
-40
TJ, JUNCTION TEMPERATURE (oC)
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
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RF1K49086 Typical Performance Curves
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.5 750
(Continued)
1000
C, CAPACITANCE (pF)
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD CISS
1.0
500 COSS 250 CRSS
0.5
0.0 -80
-40
0 40 80 120 TJ , JUNCTION TEMPERATURE (oC)
160
0
0
5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
30 VDS , DRAIN-SOURCE VOLTAGE (V)
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10.0 VGS , GATE-SOURCE VOLTAGE (V)
22.5
VDD = BVDSS RL = 8.57 IG(REF) = 0.75mA VGS = 10V
VDD = BVDSS
7.5
15
5.0
7.5
PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS
2.5
0
0 I G ( REF )
20 --------------------I G ( ACT )
I G ( REF )
t, TIME (s)
80 --------------------I G ( ACT )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
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RF1K49086 Test Circuits and Waveforms
(Continued)
tON td(ON) tr RL VDS 90%
tOFF td(OFF) tf 90%
+
RG DUT
-
VDD
0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 17. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
VDS RL
VDD VDS
Qg(TOT)
VGS = 20V VGS
+
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORM
Soldering Precautions
The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device.
3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided.
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RF1K49086 PSPICE Electrical Model
SUBCKT RF1K49086 2 1 3 ;
CA 12 8 1.75e-9 CB 15 14 1.80e-9 CIN 6 8 1.20e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 33.29 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1e-4 RGATE 9 20 1.83 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 13.5e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 S1B CA + EGS 6 8 EDS 13 8 14 13 13 CB + 14 5 8 IT GATE 1
rev 12/15/94
DPLCAP 10 5 LDRAIN DRAIN 2
DBREAK RDRAIN
ESG + EVTO 9 20 + 18 8 LGATE RGATE
6 8 VTO + 6
11 16 EBREAK 17 18
+
DBODY
21 MOS1
MOS2
RIN
CIN 8 RSOURCE 7 LSOURCE 3 SOURCE
S2A 15 17 S2B RBREAK 18 RVTO 19 VBAT +
VBAT 8 19 DC 1 VTO 21 6 0.1 .MODEL DBDMOD D (IS = 2.50e-13 RS = 1.35e-2 TRS1 = 4.31e-5 TRS2 = 2.15e-5 CJO = 9.33e-10 TT = 2.08e-8) .MODEL DBKMOD D (RS = 1.14 TRS1 = 2.23e-3 TRS2 = -8.91e-6) .MODEL DPLCAPMOD D (CJO = 7.99e-10 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 2.15 KP = 6.25 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.74e-4 TC2 = 1.13e-6) .MODEL RDSMOD RES (TC1 = 4.5e-3 TC2 = -7.45e-7) .MODEL RVTOMOD RES (TC1 = -4.16e-3 TC2 = 2.16e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.15 VOFF= -5.15) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.15 VOFF= -7.15) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.6 VOFF= 2.4) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.4 VOFF= -2.6) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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