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LTC1344 Software-Selectable Cable Terminator
FEATURES
s
DESCRIPTIO
s
Software-Selectable Cable Termination for: RS232 (V.28) RS423 (V.10) RS422 (V.11) RS485 RS449 EIA530 EIA530-A V.35 V.36 X.21 Outputs Won't Load the Line with Power Off
The LTC (R) 1344 features six software-selectable multiprotocol cable terminators. Each terminator can be configured as an RS422 (V.11) 100 minimum differential load, V.35 T-network load or an open circuit for use with RS232 (V.28) or RS423 (V.10) transceivers that provide their own termination. When combined with the LTC1343, the LTC1344 forms a complete software-selectable multiprotocol serial port. A data bus latch feature allows sharing of the select lines between multiple interface ports. The LTC1344 is available in a 24-lead SSOP.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s
Data Networking CSU and DSU Data Routers
TYPICAL APPLICATION
CTS DSR DCD DTR RTS RL TM RXD RXC TXC SCTE TXD LL
Daisy-Chained Control Outputs
LTC1343 D4 R4 R3 R2 R1 D3 D2 D1 R4 R3 R2 R1 LTC1343 D4 D3 D2 D1
13 5
22 6
10 8
23 20 19
4
21
1
7
25
16 3
9
17 12 15
11 24 14 2
DB-25 CONNECTOR
U
LTC1344 18
U
U
DSR B
DSR A (107)
RL A (140)
CTS B
CTS A (106)
DTR B
DTR A (108)
RTS B
RTS A (105)
SHIELD (101)
SGND (102)
TM A (142)
RXD B
RXD A (104)
RXC B
RXC A (115)
DCD B
DCD A (109)
SCTE B
SCTE A (113)
TXD B
TXD A (103)
LL A (141)
TXC B
TXC A (114)
1344 TA01
1
LTC1344 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER I FOR ATIO
TOP VIEW M0 VEE R1C R1B R1A R2A R2B R2C R3A 1 2 3 4 5 6 7 8 9 24 M1 23 M2 22 DCE/DTE 21 LATCH 20 R6B 19 R6A 18 R5A 17 R5B 16 R4A 15 R4B 14 VCC 13 GND
Positive Supply Voltage (VCC) ................................... 7V Negative Supply Voltage (VEE) ........................... - 13.2V Input Voltage (Logic Inputs) .... VEE - 0.3V to VCC + 0.3V Input Voltage (Load Inputs) .................................. 18V Operating Temperature Range LTC1344C ............................................... 0C to 70C LTC1344I ........................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1344CG LTC1344IG
R3B 10 R3C 11 GND 12
G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 150C, JA = 100C/W
Consult factory for Military grade parts.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25. VCC = 5V 5%, VEE = -5V 5%, TA = TMIN to TMAX (Notes 2, 3) unless otherwise noted.
SYMBOL Supplies ICC RV.35 Supply Current Differential Mode Impedance Common Mode Impedance All Digital Pins = GND or VCC All Loads (Figure 1), - 2V VCM 2V (Commercial) All Loads (Figure 2), - 2V VCM 2V (Commercial) All Loads (Figure 1), - 2V VCM 2V (Industrial) All Loads (Figure 2), - 2V VCM 2V (Industrial) RV.11 Differential Mode Impedance All Loads (Figure 1), - 7V VCM 7V (Commercial) All Loads (Figure 1), VCM = 0V (Commercial) All Loads (Figure 1), VCM = 0V (Industrial) ILEAK VIH VIL IIN High Impedance Leakage Current Input High Voltage Input Low Voltage Input Current All Loads, - 7V VCM 7V (Commercial) All Logic Input Pins All Logic Input Pins All Logic Input Pins Logic Inputs
q q q q
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS
MIN
TYP 200
MAX 700 110 165 125 170 110 125 50
UNITS A A V
Terminator Pins
q q q q q q q
90 135 90 130 100 100 95
103 153 104 153 104 104 104 1
2 0.8 10
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified.
Note 3: All typicals are given at VCC = 5V, VEE = - 5V, TA = 25C.
2
U
V A
W
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U
WW
W
LTC1344 TYPICAL PERFORMANCE CHARACTERISTICS
V.11 or V.35 Differential Mode Impedance vs Temperature
120 DIFFERENTIAL MODE IMPEDANCE () DIFFERENTIAL MODE IMPEDANCE ()
108
115
VCM = -7V
106
110
VCM = -2V VCM = 0V
DIFFERENTIAL MODE IMPEDANCE ()
105 VCM = 7V 100 -40 -20 0 20 40 60 80 100
1344 G01
TEMPERATURE (C)
V.11 or V.35 Differential Mode Impedance vs Negative Supply Voltage (VEE)
105 165 COMMON MODE IMPEDANCE ()
DIFFERENTIAL MODE IMPEDANCE ()
160 VCM = -2V 155
COMMON MODE IMPEDANCE ()
104
103 - 5.4 - 5.2 - 5.0 - 4.8 VEE VOLTAGE (V) - 4.6
1344 G04
V.35 Common Mode Impedance vs Supply Voltage (VCC)
153 154
COMMON MODE IMPEDANCE ()
COMMON MODE IMPEDANCE ()
SUPPLY CURRENT (A)
152
151 4.6 4.8 5.0 5.2 VCC VOLTAGE (V) 5.4
1344 G07
UW
V.11 or V.35 Differential Mode Impedance vs Common Mode Voltage
105
V.11 or V.35 Differential Mode Impedance vs Supply Voltage (VCC)
104
104
102
100
103 -8 -6 - 4 -2 0 2 4 6 COMMON MODE VOLTAGE (V) 8 4.6 4.8 5.0 5.2 VCC VOLTAGE (V) 5.4
1344 G03
1344 G02
V.35 Common Mode Impedance vs Temperature
158
V.35 Common Mode Impedance vs Common Mode Voltage
156
154
150 VCM = 2V 145 - 40 -20
VCM = 0V
152
0
60 40 20 TEMPERATURE (C)
80
100
1344 G05
150 -2
0 -1 1 COMMON MODE VOLTAGE (V)
2
1344 G06
V.35 Common Mode Inpedance vs Negative Supply Voltage (VEE)
310 290
153
Supply Current vs Temperature
270 250 230 210 190 170
152
151
150
- 5.4
- 5.2 - 4.8 - 5.0 VEE VOLTAGE (V)
- 4.6
1344 G08
150 -50
-20
10 40 TEMPERATURE (C)
70
100
1344 G09
3
LTC1344
PIN FUNCTIONS
M0 (Pin 1): TTL Level Mode Select Input. The data on M0 is latched when LATCH is high. VEE (Pin 2): Negative Supply Voltage Input. Can connect directly to the LTC1343 VEE pin. R1C (Pin 3): Load 1 Center Tap. R1B (Pin 4): Load 1 Node B. R1A (Pin 5): Load 1 Node A. R2A (Pin 6): Load 2 Node A. R2B (Pin 7): Load 2 Node B. R2C (Pin 8): Load 2 Center Tap. R3A (Pin 9): Load 3 Node A. R2B (Pin 10): Load 2 Node B. R3C (Pin 11): Load 3 Center Tap. GND (Pin 12): Ground Connection for Load 1 to Load 3. GND (Pin 13): Ground Connection for Load 4 to Load 6. VCC (Pin 14): Positive Supply Input. 4.75V VCC 5.25V. R4B (Pin 15): Load 4 Node B. R4A (Pin 16): Load 4 Node A. R5B (Pin 17): Load 5 Node B. R5A (Pin 18): Load 5 Node A. R6A (Pin 19): Load 6 Node A. R6B (Pin 20): Load 6 Node B. LATCH (Pin 21): TTL Level Logic Signal Latch Input. When it is low the input buffers on M0, M1, M2 and DCE/DTE are transparent. When it is high the logic pins are latched into their respective input buffers. The data latch allows the select lines to be shared between multiple I/O ports. DCE/DTE (Pin 22): TTL Level Mode Select Input. The DCE mode is selected when it is high and DTE mode when low. The data on DCE/DTE is latched when LATCH is high. M2 (Pin 23): TTL Level Mode Select Input 1. The data on M2 is latched when LATCH is high. M1 (Pin 24): TTL Level Mode Select Input 2. The data on M1 is latched when LATCH is high.
TEST CIRCUITS
A R1 51.5 S1 ON S2 OFF R2 51.5 B V 7V OR 2V
1344 F01
Figure 1. Differential V.11 or V.35 Impedance Measurement
4
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U
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C R3 124
R1 51.5 S1 ON A, B V R2 51.5 2V S2 ON
C R3 124
1344 F02
Figure 2. V.35 Common Mode Impedance Measurement
LTC1344
ODE SELECTIO
X 0 1 0 1 0 1 0 1 0 1 X X LTC1344 MODE NAME V.10/RS423 RS530A Reserved X.21 V.35 RS530/RS449/V.36 V.28/RS232 No Cable
DCE/DTE
X = don't care, 0 = logic low, 1 = logic high
A R1 51.5 S1 ON S2 OFF R2 51.5 B C R3 124
V.11 Mode
U
M2 0 0 0 0 0 0 0 1 1 1 1 1 1 M1 0 0 0 1 1 1 1 0 0 0 0 1 1 M0 0 1 1 0 0 1 1 0 0 1 1 0 1 R1 Z Z Z Z V.11 Z Z V.35 V.35 Z Z Z V.11 R2 Z Z Z Z V.11 Z Z V.35 V.35 Z Z Z V.11 R3 Z Z Z Z V.11 Z Z Z V.35 Z Z Z V.11 R4 Z V.11 Z V.11 Z V.11 Z V.35 Z V.11 Z Z V.11 R5 Z V.11 V.11 V.11 Z V.11 V.11 V.35 V.35 V.11 V.11 Z V.11 R6 Z V.11 V.11 V.11 Z V.11 V.11 V.35 V.35 V.11 V.11 Z V.11
A R1 51.5 S1 ON S2 ON R2 51.5 B B C R3 124 S1 OFF A R1 51.5 S2 OFF R2 51.5
1344 F03
W
C R3 124
V.35 Mode Figure 3. LTC1344 Modes
Hi-Z Mode
5
LTC1344
APPLICATIONS INFORMATION
Multiprotocol Cable Termination One of the most difficult problems facing the designer of a multiprotocol serial interface is how to allow the transmitters and receivers for different electrical standards to share connector pins. In some cases the transmitters and receivers for each interface standard can be simply tied together and the appropriate circuitry enabled. But the biggest problem still remains: how to switch the various cable terminations required by the different standards. Traditional implementations have included switching resistors with expensive relays or requiring the user to change termination modules every time the interface standard has changed. Custom cables have been used with the termination in the cable head or separate terminations are built on the board, and a custom cable routes the signals to the appropriate termination. Switching the terminations using FETs is difficult because the FETs must remain off even though the signal voltage is beyond the supply voltage for the FET drivers or the power is off. The LTC1344 solves the cable termination switching problem via software control. The LTC1344 provides termination for the V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical protocols. V.10 (RS423) Termination A typical V.10 unbalanced interface is shown in Figure 4. A V.10 single-ended generator output A with ground C is connected to a differential receiver with inputs A' connected to A and input B' connected to the signal return ground C. The receiver's ground C' is separate from the signal return. Usually no cable termination is required for V.10 interfaces but the receiver inputs must be compliant with the impedance curve shown in Figure 5. In V.10 mode, both switches S1 and S2 are turned off so the only cable termination is the input impedance of the V.10 receiver.
Z 3V - 3.25mA GENERATOR BALANCED INTERCONNECTING CABLE LOAD CABLE TERMINATION RECEIVER A C B' C'
1344 F04
6
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W
U
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A'
Figure 4. Typical V.10 Interface
A 51.5 S1 OFF S2 OFF LTC1344 Z 124 Z 51.5 B C IZ 3.25mA -10V -3V VZ 10V
1344 F05
V.10 RECEIVER
Figure 5. V.10 Interface Using the LTC1344
V.11 (RS422) Termination A typical V.11 balanced interface is shown in Figure 6. A V.11 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.11 interface requires a different termination at the receiver end that has a minimum value of 100. The receiver inputs must also be compliant with the impedance curve shown in Figure 7. In V.11 mode, switch S1 is turned on and S2 is turned off so the cable is terminated with a 103 impedance.
LTC1344
APPLICATIONS INFORMATION
GENERATOR BALANCED INTERCONNECTING CABLE LOAD CABLE TERMINATION RECEIVER A A' 100 MIN
B C
B' C'
1344 F06
Figure 6. Typical V.11 Interface
A 51.5 S1 ON S2 OFF LTC1344 Z 124 Z 51.5 B C IZ 3.25mA -10V Z 3V - 3.25mA -3V VZ 10V
1344 F07
V.11 RECEIVER
Figure 7. V.11 Interface Using the LTC1344
V.28 (RS232) Termination A typical V.28 unbalanced interface is shown in Figure 8. A V.28 single-ended generator output A with ground C is connected to a single-ended receiver with inputs A' connected to A, ground C' connected via the signal return ground to C. The V.28 standard requires a 5k terminating resistor to ground which is included in almost all compliant receivers as shown in Figure 9. Because the termination is included in the receiver, both switches S1 and S2 in the LTC1344 are turned off.
U
W
U
U
GENERATOR
BALANCED INTERCONNECTING CABLE
LOAD CABLE TERMINATION RECEIVER
A C
A' C'
1344 F08
Figure 8. Typical V.28 Interface
A 51.5 S1 OFF S2 OFF LTC1344 V.28 RECEIVER
124
5k
51.5 B C
1344 F09
Figure 9. V.28 Interface Using the LTC1344
V.35 Termination A typical V.35 balanced interface is shown in Figure 10. A V.35 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.35 interface requires a T-network termination at the receiver end and the generator end. In V.35 mode both switches S1 and S2 in the LTC1344 are turned on as shown in Figure 11. The differential impedance measured at the connector must be 100 10 and the impedance between shorted terminals A' and B' to ground C' must be 150 15. The input impedance of the V.35 receiver is connected in parallel with the T-network inside the LTC1344, which can cause the overall impedance to fail the specification on the
7
LTC1344
APPLICATIONS INFORMATION
GENERATOR BALANCED INTERCONNECTING CABLE
A
LOAD CABLE TERMINATION RECEIVER
V.35 DRIVER
A 50 50 B C 125
A' 125 50 50 B' C'
1344 F10
Figure 10. Typical V.35 Interface
A 51.5 S1 ON S2 ON 51.5 B C IZ 1mA -7V Z 3V -0.8mA -3V VZ 12V
1344 F11
LTC1344 Z 124 Z
V.35 RECEIVER
Figure 11. V.35 Receiver Using the LTC1344
low side. However, all of Linear Technology's V.35 receivers meet the RS485 input impedance specification as shown in Figure 11, which insures compliance with the V.35 specification when used with the LTC1344. The generator differential impedance must be 50 to 150 and the impedance between shorted terminals A
8
U
W
U
U
LTC1344
51.5 S2 ON 51.5 B C1 100pF C
1344 F12
124
S1 ON
Figure 12. V.35 Driver Using the LTC1344
and B to ground C must be 150 15. For the generator termination, switches S1 and S2 are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in Figure 12. Any mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground causing a high frequency common mode spike on the A and B terminals. The common mode spike can cause EMI problems that are reduced by capacitor C1 which shunts much of the common mode energy to ground rather than down the cable. The LATCH Pin The LATCH pin (21) allows the select lines (M0, M1, M2 and DCE/DTE) to be shared with multiple LTC1344s, each with its own LATCH signal. When the LATCH pin is held low the select line input buffers are transparent. When the LATCH pin is pulled high, the select line input buffers latch the state of the Select pins so that changes on the select lines are ignored until LATCH is pulled low again. If the latch feature is not used, the LATCH pin should be tied to ground.
LTC1344
TYPICAL APPLICATIONS N
Figure 13 shows a typical application for the LTC1344 using the LTC1343 mixed mode transceiver chip to generate the clock and data signals for a serial interface. The LTC1344 VEE supply is generated from the LTC1343 charge pump and the select lines M0, M1, M2, DCE and LATCH are shared by both chips. Each driver output and receiver input is connected to one of the LTC1344 termination ports. Each electrical protocol can then be chosen using the digital select lines.
M0 M1 M2
1 24 23
M0 M1 M2 LTC1344
DCE/DTE LATCH
22 21
DCE/DTE LATCH VCC 14
5V
3
8
42
17 18 19 21 22 6
LTC1343 M0 M1 M2 DCE/DTE LATCH
38 37 36
7 35 34 9 33 32 13 31 30 14 29 28 15 27 NC RXC + RXC TXC +
-
Figure 13. Typical Application Using the LTC1344
+
C1 1F
U
100pF 100pF 3 8 11
100pF 12 13
VEE 2 5 4 6 7 9 10 16 15 18 17 19 20
C2 3.3F
DTE TXD+ TXD- SCTE + SCTE - NC
DCE RXD+ RXD- TXC+ TXC - RXC + RXC - NC NC SCTE+ SCTE - TXD+ TXD-
1344 F13
TXC - RXD+ RXD-
9
LTC1344
TYPICAL APPLICATIONS N
Controller Selectable Multiprotocol DTE Port with DB-25 Connector
C6 100pF C7 100pF C8 100pF
VCC 5V 14 1 C3 1F 2 C1 1F C5 1F DTE_LL/DCE_TM DTE_TXD/DCE_RXD DTE_SCT/DEC_RXC 4 3 8 LTC1343 5 6 7 9 10 12 13 14 15 D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 CHARGE PUMP 44 43 42 41 C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 16 15 VCC
DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD DTE_TM/DCE_LL
R1 R2 R3
R1 100k
16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB
EC
24
1 C11 1F 2 4 3 C12 1F 8 LTC1343 5 6 7 9 10 12 13 14 15 16 VCC LATCH D1 D2 D3 D4 CHARGE PUMP C9 1F
44 43 42 41
VCC
DTE_RL/DCE_RL DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR
39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0
DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS
R1 R2 R3
R2 100k LB DCE/DTE M2 M1 M0
R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET
40 GND 23 LB
EC
24
10
+
+
U
3
8
11
12 13 LTC1344
LATCH
21
DCE/ DTE M2 M1 M0 18 17 19 20 22 23 24 1 18
DB-25 CONNECTOR
DTE LL A
DCE TM A RXD A RXD B RXC A RXC B
2 TXD A 14 TXD B 24 SCTE A 11 SCTE B
15 12 17 9 3 16
TXC A TXC B RXC A RXC B RXD A RXD B
TXC A TXC B SCTE A SCTE B TXD A TXD B LL A
25 TM A
VCC
7
SGND SHIELD
C10 1F C13 3.3F
1
RL A 4 RTS A 19 RTS B 20 DTR A 23 DTR B
21
RL A CTS A CTS B DSR A DSR B
8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B
DCD A DCD B DTR A DTR B RTS A RTS B
1344 TA02
LTC1344
TYPICAL APPLICATIONS N
Cable Selectable Multiprotocol DTE Port with DB-25 Connector
C6 100pF C7 100pF C8 100pF
VCC 5V 14 1 C3 1F 2 C1 1F C5 1F 4 3 8 LTC1343 5 6 7 9 10 12 13 14 15 D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 CHARGE PUMP 44 43 42 41 C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 16 15 VCC
DTE_TXD/DCE_RXD DTE_SCTE/DEC_RXC
DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD
R1 R2 R3
R1 100k
16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB 1
VCC 1
EC
24
VCC VCC R3 10k VCC R4 10k VCC R5 10k
44 43 42 41 LTC1343
C11 1F
2 4 3 C12 1F 8 5 6 7 9 10 12 13 14 15 16 CHARGE PUMP
C9 1F
VCC
D1 D2 D3 D4
39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 4 RTS A 19 RTS B 20 DTR A 23 DTR B CTS A CTS B DSR A DSR B
DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/ DCE_RTS
R1 R2 R3
VCC
R2 100k LB
R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET
VCC
40 GND 23 LB
24 EC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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3
8
11
12 13 LTC1344
LATCH
21
DCE/ DTE M2 M1 M0 18 17 19 20 22 23 24 1
DB-25 CONNECTOR
VCC
DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B
DCE RXD A RXD B RXC A RXC B
15 12 17 9 3 16
TXC A TXC B RXC A RXC B RXD A RXD B
TXC A TXC B SCTE A SCTE B TXD A TXD B
7
SGND SHIELD
C10 1F C13 3.3F
25 21 18
DCE/DTE M1 M0
8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B
DCD A DCD B DTR A DTR B RTS A RTS B
1344 TA03
CABLE WIRING FOR MODE SELECTION MODE PIN 18 PIN 21 V.35 PIN 7 PIN 7 EIA-530, RS449, NC PIN 7 V.36, X.21 RS232 PIN 7 NC
CABLE WIRING FOR DTE/DCE SELECTION MODE PIN 25 DTE PIN 7 DCE NC
11
LTC1344
PACKAGE DESCRIPTION
5.20 - 5.38** (0.205 - 0.212)
0.13 - 0.22 (0.005 - 0.009)
0.55 - 0.95 (0.022 - 0.037)
NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
RELATED PARTS
PART NUMBER LTC1334 LTC1343 LTC1345 LTC1346A LTC1344A LTC1543 LTC1544 LTC1545 DESCRIPTION Single Supply RS232/RS485 Transceiver Multiprotocol Serial Transceiver Single Supply V.35 Transceiver Dual Supply V.35 Transceiver Multiprotocol Cable Terminator, Pin Compatible to LTC1344 Multiprotocol Serial Transceiver Multiprotocol Serial Transceiver Multiprotocol Serial Transceiver COMMENTS 2 RS485 Dr/Rx or 4 RS232 Dr/Rx Pairs Software Selectable Mulitprotocol Interface 3 Dr/3 Rx for Data and CLK Signals 3 Dr/3 Rx for Data and CLK Signals Allows Separate RS449 Mode 3 Dr/3 Rx for Data and CLK Signals 4 Dr/4 Rx for Control Signals and LL 5 Dr/5 Rx for Control Signals, LL, RL amd TM
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
8.07 - 8.33* (0.318 - 0.328) 24 23 22 21 20 19 18 17 16 15 14 13
7.65 - 7.90 (0.301 - 0.311)
1 2 3 4 5 6 7 8 9 10 11 12 1.73 - 1.99 (0.068 - 0.078)
0 - 8
0.65 (0.0256) BSC
0.25 - 0.38 (0.010 - 0.015)
0.05 - 0.21 (0.002 - 0.008)
G24 SSOP 1098
1344fa LT/TP 0300 2K REV A * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1996

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