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IH5352
Data Sheet July 1999 File Number
3134.2
Quad SPST, CMOS RF/Video Switch
The IH5352 is a quad SPST, CMOS monolithic switch which uses a "Series/Shunt" ("T" switch) configuration to obtain high OFF isolation while maintaining good frequency response in the ON condition. Construction of remote and portable video equipment with extended battery life is facilitated by the extremely low current requirements. Switching speeds are typically tON = 150ns and tOFF = 80ns. "Break-Before-Make" switching is guaranteed. Switch ON resistance is typically 40 - 50 with 15V power supplies, increasing to typically 175 for 5V supplies.
Features
* rDS(ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 * Switch Attenuation Varies Less Than 3dB From DC to 100MHz * OFF Isolation at 10MHz . . . . . . . . . . . . . . . . . . . . . >70dB * Crosstalk Isolation at 10MHz . . . . . . . . . . . . . . . . . >60dB * Compatible With TTL, CMOS Logic * Wide Operating Power Supply Range * Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . <1A * "Break-Before-Make" Switching * Fast Switching (Typ) . . . . . . . . . . . . . . . . . . . . 80ns/150ns
PKG. NO.
Ordering Information
PART NUMBER IH5352CPE IH5352CBP TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 16 Ld PDIP 20 Ld SOIC
Applications
* Video Switch * Communications Equipment * Disk Drives
E16.3 M20.3
Pinouts
IH5352 (PDIP) TOP VIEW
IIN1 1 S1 2 IIN2 3 S2 4 IIN3 5 S3 6 IIN4 7 S4 8 16 D1 15 V+ 14 D2 13 GND 12 D3 11 V10 D4 9 VL
* Instrumentation * CATV
Functional Diagram
SWITCH STATE SHOWN FOR LOGIC "0" INPUT
S1 IIN1 D1
S2 IIN2
D2
IH5352 (SOIC) TOP VIEW
IIN1 1 S1 2 NC 3 IIN2 4 S2 5 IIN3 6 S3 7 NC 8 IIN4 9 S4 10 20 D1 19 V+ 18 NC 17 D2 16 GND 15 D3 14 V13 NC 12 D4 11 VL
S3 IIN3
D3
S4 IIN4
D4
TRUTH TABLE LOGIC 0 1 SWITCHES Off On
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
IH5352 Schematic Diagram
1/ IH5352 4
+15V -15V Q3 Q7 Q5 Q20 +15V 10k 5k Q3 Q1 TTL Q8 Q19 S -15V -15V Q16 Q9 5 Q22 Q18 Q17
Q10 +15V +15V +5V 5k Q4 Q6 Q11 3k Q 12 +15V Q21 Q15
D Q13 -15V Q14
2
IH5352
Absolute Maximum Ratings
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18V VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VLogic Control Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VAnalog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VCurrent (Any Terminal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Supply Voltage Range V+, VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 15V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to -15V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = +15V, VL = +5V, V- = -15V, Unless Otherwise Specified (NOTE 2) TYP 25oC (NOTE 4) 0 oC 25oC 70oC UNITS
PARAMETER DYNAMIC CHARACTERISTICS Turn ON Time, tON Turn OFF Time, tOFF OFF Isolation, OIRR Crosstalk, CCRR Switch Attenuation 3dB Frequency, f3dB DIGITAL INPUT CHARACTERISTICS Logic "1" Input Voltage, VIH Logic "0" Input Voltage, VIL Input Logic Current, IIN ANALOG SWITCH CHARACTERISTICS Drain-Source ON Resistance, rDS(ON) Figure 2 Figure 3 Figure 4 Figure 1
TEST CONDITIONS
150 80 70 -60 100
-
-
-
ns ns dB dB MHz
>2.4 <0.8 VIN > 2.4V or < 0V 0.1
1
1
10
V V A
VD = 5V, IS = 10mA, VIN 2.4V VD = 10V, IS = 10mA, VIN 2.4V V+ = VL = +5V, VIN = 3V, V- = -5V, VD = 3V, IS = 10mA
50 100 175 5 -
75 150 300 -
75 150 300 2 2
100 175 350 100 100
nA nA
On Resistance Match Between Channels, rDS(ON) Switch OFF Leakage Current, ID(OFF) or IS(OFF) Switch ON Leakage Current, ID(ON) + IS(ON) POWER SUPPLY CHARACTERISTICS Positive Supply Quiescent Current, I+ Negative Supply Quiescent Current, ILogic Supply Quiescent Current, IL NOTES:
IS = 10mA, VD = 5V VS/D = 5V or 14V, VIN 0.8V (Note 3) VS/D = 5V or 14V, VIN 2.4V
VIN = 0V or +5V
0.1 0.1 0.1
1 1 1
1 1 1
10 10 10
A A A
2. Typical values are not tested in production. They are given as a design aid only. 3. Positive and negative voltages applied to opposite sides of switch, in both directions successively. 4. Min or Max value, unless otherwise specified.
3
IH5352 Test Circuits and Waveforms
15V 5V +3V TTL INPUT 0V +3.5V D1 IN1 D2 IN2 VOUT (VANALOG + 5V) 0V tON 0V GND -15V VOUT (VANALOG - 5V) -3.5V 10% tOFF 90% 50% 50%
VANALOG (5V) VOUT +3V 0V TTL IN RL = 100
S1
V+
VL
S2
90%
10%
NOTE: Only one channel shown. Others act identically. FIGURE 1A. TEST CIRCUIT FIGURE 1. tON AND tOFF
15V 5V 15V VIN RG-59 COAX D1 RG-59 COAX IN1 D2 IN2 +5V VGND V-15V GND IN1 IN2 S1 V+ VL S2 75 S1 V+ VL S2 OPEN 75 VOUT 5V
FIGURE 1B. MEASUREMENT POINTS
75
VOUT 75
VIN
D1
D2
V IN = 5V ( 10V P-P ) at f = 10MHz V IN OIRR = 20Log --------------V OUT NOTE: Only one channel shown. Others act identically. FIGURE 2. OFF ISOLATION TEST CIRCUIT
75 VIN RG-59 COAX D1 IN1 D2 IN2 75 15V 5V
-15V
V IN = 225mV RMS at f = 10MHz V OUT CCRR = 20Log --------------V IN FIGURE 3. CROSSTALK TEST CIRCUIT
S1
V+
VL
S2
NC
VOUT 75
RG-59 COAX
+5V
V-
GND
-15V
RL ATTN: = 20Log ----------------------------------r DS ( ON ) + R L Nominally, at DC, ATTN equals -4dB. When the attenuation reaches -1dB, the frequency at which this occurs is f3dB . NOTE: Only one channel shown. Others act identically. FIGURE 4. SWITCH ATTENUATION TEST CIRCUIT
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IH5352 Detailed Description
Figure 5 shows the internal circuit of one channel of the IH5352. Here, a shunt switch is closed, and the two series switches are open when the video switch channel is open or off. This provides much better isolation between the input and output terminals than a simple series switch does, especially at high frequencies. The result is excellent offisolation in the Video and RF frequency ranges when compared to conventional analog switches. The control input level shifting circuitry is very similar to that of the IH5140 series of Analog Switches, and gives very high speed, guaranteed "Break-Before-Make" action, low static power consumption and TTL compatibility.
SWITCH SOURCE (VIDEO INPUT) LOGIC CONTROL INPUT SHUNT SWITCH DRIVER TRANSLATOR SWITCH DRAIN (VIDEO OUTPUT)
Since individual parts are very consistent in their charge injection, it is possible to replace the potentiometer with a pair of fixed resistors, and achieve less than 5mV error for all devices without adjustment. An alternative arrangement, using a standard TTL inverter to generate the required inversion, is shown in Figure 7. The capacitor needs to be increased, and becomes the only method of adjustment. A fixed value of 22pF is good for analog values referred to ground, while 35pF is optimum for AC coupled signals referred to -5V as shown in the figure. The choice of -5V is based on the virtual disappearance at this analog level of the transient component of switching charge injection. This combination will lead to a virtually "glitch-free" switch.
75 15V 1F 5V
VOUT
S1
V+
VL
S2
-15V 1k CERMET NOT WIRE WOUND (NOTE)
NOTE: 1 channel of 4 shown. FIGURE 5. INTERNAL SWITCH CONFIGURATION
ANALOG INPUT
D1 IN1
D2 IN2
Typical Applications
Charge Compensation Techniques
Charge injection results from the signals out of the level translation circuit being coupled through the gate-channel and gate-source/drain capacitances to the switch inputs and outputs. This feedthrough is particularly troublesome in Sample-and-Hold or Track-and-Hold applications, as it causes a Sample (Track) to Hold offset. The IH5352 has a typical injected charge of 30pC-50pC (corresponding to 30mV-50mV on a 1000pF capacitor), at VS-D of about 0V. This Sample (Track) to Hold offset can be compensated by bringing in a signal equal in magnitude but of the opposite polarity. The circuit of Figure 6 accomplishes this charge injection compensation by using one side of the device as a S & H (T & H) switch, and the other side as a generator of a compensating signal. The 1k potentiometer allows the user to adjust the net injected charge to exactly zero for any analog voltage in the -5V to +5V range.
10pF
V-
GND
75
CHOLD 1000pF
+3V 0V TTL IN (STROBE)
1F
NOTE: Adjust pot for 0mVP-P step at VOUT with no analog (AC) signal present. FIGURE 6. CHARGE INJECTION COMPENSATION
5
IH5352
15V 5V +5V
VOUT DC BIAS VOLTAGE = -5V ANALOG INPUT
S1
V+
VL
S2
1 2
14 13 12 SN7400 11 10 9 8
75 D1 1F IN1 IN2 D2
3 4 5 6 7
V-15V +4V 0V
GND
22pF-35pF CHOLD 1000pF
+3V 0V TTL CONTROL IN
FIGURE 7. ALTERNATIVE COMPENSATION CIRCUIT
Overvoltage Protection
If sustained operation with no supplies but with analog signals applied is possible, it is recommended that diodes (such as 1N914) be inserted in series with the supply lines to the IH5352. Such conditions can occur if these signals come from a separate power supply or another location, for example. The diodes will be reverse biased under this type of operation, preventing heavy currents from flowing from the analog source through the IH5352. The same method of protection will provide over 25V overvoltage protection on the analog inputs when the supplies are present. The schematic for this connection is shown in Figure 8.
15V 1N914 1F S1 V+
5V
VL
S2
D1 IN1
D2 IN2
V1N914
GND
-15V 1F
FIGURE 8. OVERVOLTAGE PROTECTION
6
IH5352 Typical Performance Curves
70 PIN 3 = +15V, PIN 7 = -15V PIN 10 = +5V, TA = 25oC 160 60 rDS(ON) () rDS(ON) () 140 180 PIN 3 = PIN10 = +5V PIN 7 = -5V, TA = 25oC
50
120
40 100
30 -15
-10
-5
0
5
10
15
80 -5 0 ANALOG INPUT VOLTAGE (V) 5
ANALOG INPUT VOLTAGE (V)
FIGURE 9. rDS(ON) vs ANALOG INPUT VOLTAGE WITH 15V POWER SUPPLIES
FIGURE 10. rDS(ON) vs ANALOG INPUT LEVEL WITH 5V POWER SUPPLIES
100 90 OFF ISOLATION (dB) 80 70 60 50 40 30 0.1
TA = 25oC
-100 -90 -80 -70 -60 -50 -40 -30 0.1
TA = 25oC
CROSSTALK (dB)
1 10 FREQUENCY (MHz)
100
1 10 FREQUENCY (MHz)
100
FIGURE 11. OFF ISOLATION vs FREQUENCY (SEE FIGURE 2)
FIGURE 12. CROSSTALK vs FREQUENCY (SEE FIGURE 3)
-3.3 -3.4 SWITCH ATTENUATION (dB) -3.5 -3.6 -3.7 -3.8 -3.9 -4.0 0.1
TA = 25oC
1 10 FREQUENCY (MHz)
100
FIGURE 13. SWITCH ATTENUATION vs FREQUENCY (RL = 75, SEE FIGURE 4)
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IH5352 Die Characteristics
DIE DIMENSIONS: 2617m x 5233m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG/Nitride PSG Thickness: 7kA 1.4kA Nitride Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
IH5352
S1 IN1 D1 V+ (SUBSTRATE)
IN2
D2
S2 GND
IN3 D3 S3 V-
IN4 D4 S4 VL
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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