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| DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number DM74S112 Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table Inputs PR L H L H H H H H CLR H L L H H H H H CLK X X X H J X X X L H L H X K X X X L L H H X Q0 H L H* Q0 H L Toggle Q0 Outputs Q Q L H H* Q0 L H H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level = Negative going edge of pulse. Q0 = The output logic level of Q before the indicated input conditions were established. * = This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to its inactive (HIGH) level. Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse. (c) 2000 Fairchild Semiconductor Corporation DS006459 www.fairchildsemi.com DM74S112 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) Clock HIGH Clock LOW Clear LOW Preset LOW tW Pulse Width (Note 3) Clock HIGH Clock LOW Clear LOW Preset LOW tSU tH TA Setup Time (Note 4)(Note 5) Input Hold Time (Note 4)(Note 5) Free Air Operating Temperature 0 0 6 6.5 8 8 8 8 10 10 7 0 0 70 ns ns C ns ns 125 80 Parameter Min 4.75 2 0.8 -1 20 80 60 Nom 5 Max 5.25 Units V V V mA mA MHz MHz Note 2: CL = 15 pF, R L = 280, TA = 25C and VCC = 5V. Note 3: CL = 50 pF, R L = 280, TA = 25C and VCC = 5V. Note 4: TA = 25C and V CC = 5V. Note 5: The symbol () indicates the falling edge at the clock pulse is used for reference. www.fairchildsemi.com 2 DM74S112 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage HIGH Level Input Current Conditions VCC = Min, II = - 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max VI = 2.7V J, K Clear Preset Clock IIL LOW Level Input Current VCC = Max VI = 0.5V (Note 7) IOS ICC Short Circuit Output Current Supply Current VCC = Max (Note 8) VCC = Max (Note 9) J, K Clear Preset Clock -40 30 2.7 3.4 0.5 1 50 100 100 100 -1.6 -7 -7 -4 -100 50 mA mA mA A Min Typ (Note 6) Max -1.2 Units V V V mA Input Current @ Max Input Voltage VCC = Max, VI = 5.5V Note 6: All typicals are at VCC = 5V, TA = 25C. Note 7: Clear is tested with preset HIGH and preset is tested with clear HIGH. Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 9: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock input is grounded. Switching Characteristics at VCC = 5V and TA = 25C RL = 280 Symbol Parameter From (Input) To (Output) fMAX tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Preset to Q CL = 15 pF Min 80 7 Max CL = 50 pF Min 60 9 Max MHz ns Units Preset to Q 7 12 ns Clear to Q Clear to Q 7 7 9 12 ns ns Clock to Q or Q 7 9 ns Clock to Q or Q 7 12 ns 3 www.fairchildsemi.com DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 4 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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