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Integrated Circuit Systems, Inc.
ICS94203
Programmable System Frequency Generator for PII/IIITM
Recommended Application: 810/810E and Solano (815) type chipset Output Features: * 2 - CPUs @ 2.5V * 13 - SDRAM @ 3.3V * 3 - 3V66 @ 3.3V * 7 - PCI @3.3V * 1 - 24/48MHz@ 3.3V * 1 - 48MHz @ 3.3V fixed * 1 - REF @3.3V, 14.318MHz Features: * Programmable ouput frequency * Gear ratio change detection * Real time system reset output * Spread spectrum for EMI control with programmable spread percentage * Watchdog timer technology to reset system if over-clocking causes malfunction. * Support power management through PD#. * Uses external 14.318MHz crystal * FS pins for frequency select Key Specifications: * CPU Output Jitter: <250ps * IOAPIC Output Jitter: <500ps * 48MHz, 3V66, PCI Output Jitter: <500ps * CPU Output Skew: <175ps * PCI Output Skew: <500ps * 3V66 Output Skew <175ps * For group skew timing, please refer to the Group Timing Relationship Table.
VDDA GNDA X1 X2 GND3V66 VDD3V66 3V66-0 3V66-1 3V66-2 VDDPCI GNDPCI 1 *FS0/PCICLK0 1 *FS1/PCICLK1 1 *SEL24_48#/PCICLK2 GNDPCI VDDPCI PCICLK3 PCICLK4 PCICLK5 PCICLK6 RATIO_0 PD# SCLK SDATA VDD48 GND48 *FS2/24_48MHz 1 *FS3/48MHz
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF/FS4* VDDLAPIC 1 IOAPIC0 VDDLCPU GNDLCPU CPUCLK0 CPUCLK1 GNDSDR VDDSDR SDRAM0 SDRAM1 SDRAM2 SDRAM3 VDDSDR GNDSDR SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM_F GNDSDR VDDSDR SDRAM8 SDRAM9 SDRAM10 SDRAM11 RESET# RATIO_1
1
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum
CPU DIVDER SDRAM DIVDER
2
ICS94203
48MHz 24_48MHz
REF CPUCLK (1:0) SDRAM (11:0) SDRAM_F
IOAPIC DIVDER
12
Power Groups
VDDA, GNDA = Core PLL, Xtal VDD48, GND48 = 48MHz, Fixed PLL
FS(4:0) PD# SEL24_48# SDATA SCLK Control Logic Config. Reg.
IOAPIC PCICLK (6:0) 3V66 (2:0) RESET# RATIO_0 RATIO_1
PCI DIVDER 3V66 DIVDER
7
3
94203 Rev B 02/13/01
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS94203
General Description
The ICS94203 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary clock signals for such a system. The ICS94203 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. Spread spectrum typically reduces system EMI by 7dB to 8dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding.
Pin Configuration
PIN NUMBER P I N NA M E VDD X1 X2 GND 3V66 [2:0] PCICLK01 FS0 PCICLK11 TYPE PWR IN OUT PWR OUT OUT IN OUT IN IN OUT OUT OUT IN IN I/O IN OUT IN OUT OUT OUT OUT OUT OUT PWR PWR OUT IN OUT 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B 3.3V PCI clock output, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. 3.3V PCI clock output, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. 2 4 / 4 8 M H z f r e q u e n cy s e l e c t p i n f o r p i n 2 7 3.3V PCI clock output, with Synchronous CPUCLKS 3.3V PCI clock outputs, with Synchronous CPUCLKS Output to chipset, replacing the BSEL0 signals orginally from the processor. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock input of I2C input Data input for I2C serial input. Logic input frequency select bit. Input latched at power on. 3 . 3 V 2 4 _ 4 8 M H z o u t p u t D e fa u l t i s 2 4 M H z . Logic input frequency select bit. Input latched at power on. 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B . Output to chipset, replacing the BSE1 signals orginally from the processor. R e a l t i m e s y s t e m r e s e t s i g n a l f o r f r e q u e n cy r a t i o c h a n g e o r w a t c h d o g t i m m e r t i m e o u t . This signal is active low. 3.3V SDRAM output can be turned off through I2C 3.3V output. All SDRAM outputs can be turned off through I2C 2.5V Host bus clock output. Output frequency derived from FS pins. Ground for 2.5V power supply for CPU & APIC 2.5V power suypply for CPU, IOAPIC 2.5V clock outputs running at 16.67MHz. Logic input frequency select bit. Input latched at power on. 3.3V, 14.318MHz reference clock output. DESCRIPTION
1, 6, 10, 16, 25, 35, 43, 48 3 4 2, 5, 11, 15, 26, 36, 42, 49 9, 8, 7 12 13
FS1 SEL24_48#
14
PCICLK2
20, 19, 18, 17 21 22 23 24 27
PCICLK [6:3] RATIO_0 PD# SCLK SDATA FS2 24_48MHz FS3
28 29 30 37 31, 32, 33, 34, 38, 39, 40, 41, 44, 45, 46, 47
50, 51 52 53, 55 54 56
48MHz RATIO_1 RESET SDRAM_F SDRAM [11:0] CPUCLK [1:0] GNDL VDDL IOAPIC FS4 REF1
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ICS94203
General I2C serial interface information for the ICS94203 How to Write:
* * * * * * * * Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 28 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 6 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 6). * Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit * * * * * * *
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK If 7H has been written to B6 ACK Byte 7
Byte 26 ACK Byte 27 ACK Byte 28 ACK Stop Bit
*See notes on the following page.
If 1AH has been written to B6 ACK If 1BH has been written to B6 ACK If 1CH has been written to B6 ACK Stop Bit
Byte26 Byte 27 Byte 28
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ICS94203
Brief I2C registers description for ICS94203 Programmable System Frequency Generator
Register Name
Functionality & Frequency Select Register Output Control Registers Byte Count Read Back Register
Byte
0 1-5 6
Description
Pwd Default
Output frequency, hardware / I2C frequency See individual byte select, spread spectrum & output enable description control register. Active / inactive output control registers.
See individual byte description
Writing to this register will configure byte count and how many byte will be read back. 06H Do not write 00H to this byte. Latched Inputs Read Back The inverse of the latched inputs level could See individual byte 7 description Register be read back from this register. Watchdog enable, watchdog status and 000,0000 Watchdog Control Registers 8 Bit[6:0] programmable 'safe' frequency' can be configured in this register. This bit select whether the output frequency 0 VCO Control Selection Bit 8 Bit[7] is control by hardware/byte 0 configurations or byte 14&15 programming. Writing to this register will configure the FFH Watchdog Timer Count Register 9 number of seconds for the watchdog timer to reset. This is an unused register. Writing to this ICS Reserved Register 10 00H register will not affect device functionality. Byte 11 bit[3:0] is ICS vendor id - 0001. Device ID, Vendor ID & Revision ID See individual byte 11-12 Other bits in these 2 registers designate description Registers device revision ID of this part. Don't write into this register, writing 1's will ICS Reserved Register 13 00H cause malfunction. These registers control the dividers ratio Depended on VCO Frequency Control Registers 14-15 into the phase detector and thus control the hardware/byte 0 configuration VCO output frequency. Spread Spectrum Control Registers 16-17 These registers control the spread percentage amount. Changing bits in these registers result in frequency divider ratio changes. Incorrect configuration of group output divider ratio can cause system malfunction. Increment or decrement the group skew amount as compared to the initial skew. These register will control the group rise and fall time.
Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description
Output Dividers Control Registers
18-20
Group Skews Control Registers Output Rise/Fall Time Select Registers
21 22
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 6. When writing to byte 14 - 15, byte 16 - 17 and byte 18 - 20, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
2. 3. 4. 5. 6.
7.
4
ICS94203
Byte 0: Functionality and frequency select register (Default=0)
Bit Bit2 Bit7 Bit6 Bit5 Bit4 VCO/REF Divider FS4 FS3 FS2 FS1 FS0 Description VCO MHz VCO/ CPUCLK SDRAM CPU MHz MHz 66.45 60.00 66.80 68.33 70.00 75.00 80.00 83.00 99.65 80.00 100.23 103.00 105.00 110.00 115.00 200.00 132.86 160.00 133.64 137.00 140.00 145.00 150.00 160.00 132.90 160.00 133.64 137.00 140.00 145.00 150.00 160.00 99.65 90.00 100.20 102.50 105.00 112.50 120.00 124.50 99.65 80.00 100.23 103.00 105.00 110.00 115.00 200.00 132.86 160.00 133.64 137.00 140.00 145.00 150.00 160.00 99.65 100.00 100.23 102.75 105.00 108.75 112.50 120.00 3V66 MHz 66.43 60.00 66.80 68.33 70.00 75.00 80.00 83.00 66.43 53.33 66.84 68.67 70.00 73.33 76.67 100.00 66.43 80.00 66.82 68.50 70.00 72.50 75.00 80.00 66.93 80.00 66.82 68.50 70.00 72.50 75.00 80.00 PCICLK MHz 33.21 30.00 33.40 34.17 35.00 37.50 40.00 41.50 33.21 26.67 33.41 34.33 35.00 36.67 38.33 50.00 33.21 40.00 33.41 34.25 35.00 36.25 37.50 40.00 33.21 40.00 33.41 34.25 35.00 36.25 37.50 40.00 IOAPIC MHz 16.61 15.00 16.70 17.08 17.50 18.75 20.00 20.75 16.61 13.33 16.70 17.17 17.50 18.33 19.17 25.00 16.61 20.00 16.70 17.13 17.50 18.13 18.75 20.00 16.61 20.00 16.7 17.13 17.50 18.13 18.75 20.00 PWD
Bit (2,7:4)
Bit 3 Bit 1 Bit 0
0 0 0 0 0 362/13 398.71 6 0 0 0 0 1 352/14 360.00 6 0 0 0 1 0 504/18 400.91 6 0 0 0 1 1 315/11 410.02 6 0 0 1 0 0 440/15 420.00 6 0 0 1 0 1 440/14 450.00 6 0 0 1 1 0 503/15 480.14 6 0 0 1 1 1 313/9 497.95 6 0 1 0 0 0 515/37 199.29 2 0 1 0 0 1 447/40 160.29 2 0 1 0 1 0 518/37 200.45 2 0 1 0 1 1 446/31 206.00 2 0 1 1 0 0 484/33 210.00 2 0 1 1 0 1 507/33 219.98 2 0 1 1 1 0 514/32 229.99 2 0 1 1 1 1 461/11 600.06 2 1 0 0 0 0 362/13 398.71 3 1 0 0 0 1 503/15 480.14 3 1 0 0 1 0 504/18 400.91 3 1 0 0 1 1 488/17 411.02 3 1 0 1 0 0 440/15 420.00 3 1 0 1 0 1 395/13 435.05 3 1 0 1 1 0 440/14 450.00 3 1 0 1 1 1 503/15 480.14 3 1 1 0 0 0 362/13 398.71 3 1 1 0 0 1 503/15 480.14 3 1 1 0 1 0 504/18 400.91 3 1 1 0 1 1 488/17 411.02 3 1 1 1 0 0 440/15 420.00 3 1 1 1 0 1 395/13 435.05 3 1 1 1 1 0 440/14 450.00 3 1 1 1 1 1 503/15 480.14 3 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,7:4 0- Normal 1- Spread spectrum enable 0.35% Center Spread 0- Running 1- Tristate all outputs
Note 1
0 1 0
Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
5
ICS94203
Byte 1: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 27 28 37 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) 24_48MHz (Reserved) 48MHz (Reserved) SDRAM_F
Byte 2: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 38 39 40 41 44 45 46 47
PW D 1 1 1 1 1 1 1 1
Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 3: Output Control Register (1 = enable, 0 = disable)
Byte 4: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 20 19 18 17 14 13 12
PWD 0 1 1 1 1 1 1 1
Description Reserved PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 9 7 8 56 54 50 51
PW D 1 1 1 1 1 X 1 1
Description 3V66_2 3V66_0 3V66_1 REF IOAPIC0 Reserved CPUCLK1 CPUCLK0
Byte 5: Output Control Register (1 = enable, 0 = disable)
Byte 6: Byte Count Read Back Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 31 32 33 34
PWD 1 1 1 1 1 1 1 1
Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 SDRAM10 SDRAM9 SDRAM8
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
PW D 0 0 0 0 0 1 1 0
Description R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Note: Writing to this register will configure byte count and how many bytes will be read back, default is 6 bytes.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
6
ICS94203
Byte 7: Latch Inputs Readback Register
Byte 8: VCO Control Selection Bit & Watchdog Timer Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 X X X X X X
Description (Reserved) (Reserved) (SEL24_48#)# FS4# FS3# FS2# FS1# FS0#
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 0 0 0 0
Description 0=Hw/B0 freq / 1=B14&15 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, FS4 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS values. Default safe frequency is same as 00000 entry in byte0.
Byte 9: Watchdog Timer Count Register
Byte 10: ICS Reserved Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 1 1 1 1
Description The decimal representation of these 8 bits correspond to 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 15 X 290ms = 4.4 seconds. Note, this timer does not control the RESET# signal (pin 30) in case of the frequency ratio change.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 0 0 0 0
Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Note: This is an unused register. Writing to this register will not affect device performance or functionality.
Byte 11: Vender ID & Device ID Register
Byte 12: Revision ID Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD X X X X X X X X Description Revision Revision Revision Revision Revision Revision Revision Revision ID ID ID ID ID ID ID ID
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 1 1 0 0 0 1
Description Device ID Device ID Device ID Device ID Vendor ID Vendor ID Vendor ID Vendor ID
Note: ICS Vendor ID is 0001 as in Number 1 in frequency generation.
Note: Device ID and Revision ID values will be based on individual device and its revision.
Notes: 1. PWD = Power on Default
7
ICS94203
Byte 13: ICS Reserved Register
Byte 14: VCO Frequency Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD Description 0 (Reserved) 0 (Reserved) 0 (Reserved) W0 timer base select 0 0=290ms 1=0.5ms 0 (Reserved) 0 (Reserved) 0 (Reserved) 0 (Reserved)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0
Note: The decimal representation of these 7 bits (Byte 14 [6:0]) + 2 is equal to the REF divider value .
Note: DON'T write a '1' into this register, it will cause malfunction.
Byte 15: VCO Frequency Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1
VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
Note: The decimal representation of these 9 bits (Byte 15 bit [7:0] & Byte 14 bit [7] ) + 8 is equal to the VCO divider value. For example if VCO divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 15 bit & byte 14 bit 7.
To program the VCO frequency for over-clocking. 0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming. 1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to byte 0, or using initial hardware power up frequency. 2. Write 0001, 0111 (17H) to byte 6 for readback of 23 bytes (byte 0-22). 3. Read back byte 16-24 and copy values in these registers. 4. Re-initialize the write sequence. 5. Write a '1' to byte 8 bit 7 indicating you want to use byte 14 and 15 to control the VCO frequency. 6. Write to byte 14 & 15 with the desired VCO & REF divider values. 7. Write to byte 16 to 22 with the values you copy from step 3. This maintains the output divider mux controls the same gear ratio. 8. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed again, user only needs to write to byte 14 and 15 unless the system is to reboot.
8
ICS94203
Note: 1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group divider ratio programmed into bytes 16-20 could be unstable. Step 3 & 7 assure the correct spread and gear ratio. 2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly. 3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz). 4. Users can also utilize software utility provided to program VCO frequency from ICS Application Engineering. 5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See Application note for software support.
Byte 16: Spread Sectrum Control Register
Byte 17: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X 0 X X X X X X
Description Divider control Bit26 Divider control Bit25 Divider control Bit24 Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bit9 Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Byte 18: Output Dividers Control Register
Byte 19: Output Dividers Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Output Divider MUX Control Bit7 Output Divider MUX Control Bit6 Output Divider MUX Control Bit5 Output Divider MUX Control Bit4 Output Divider MUX Control Bit3 Output Divider MUX Control Bit2 Output Divider MUX Control Bit1 Output Divider MUX Control Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Output Divider MUX Control Bit15 Output Divider MUX Control Bit14 Output Divider MUX Control Bit13 Output Divider MUX Control Bit12 Output Divider MUX Control Bit11 Output Divider MUX Control Bit10 Output Divider MUX Control Bit9 Output Divider MUX Control Bit8
Note: Changing bits in these registers results in frequency divider ratio changes. Incorrect configuration of group gear ratio can cause system malfunction.
Note: Changing bits in these registers results in frequency divider ratio changes. Incorrect configuration of group gear ratio can cause system malfunction.
Notes: 1. PWD = Power on Default 2. The power on default for byte 16-20 depends on the harware (latch inputs FS[0:4]) or IIC (Byte 0 bit [1:7]) setting. Be sure to read back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass.
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ICS94203
Byte 20: Output Dividers Control Register
Byte 21: ICS Reserved Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Output Divider MUX Control Bit23 Output Divider MUX Control Bit22 Output Divider MUX Control Bit21 Output Divider MUX Control Bit20 Output Divider MUX Control Bit19 Output Divider MUX Control Bit18 Output Divider MUX Control Bit17 Output Divider MUX Control Bit16
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 1 0 1 1 0
Description 3V66 to PCI Skew Bit3 3V66 to PCI Skew Bit2 3V66 to PCI Skew Bit1 3V66 to PCI Skew Bit0 3V66 to IOAPIC Skew Bit 3 3V66 to IOAPIC Skew Bit 2 3V66 to IOAPIC Skew Bit 1 3V66 to IOAPIC Skew Bit 0
Note: Changing bits in these registers results in frequency divider ratio changes. Incorrect configuration of group gear ratio can cause system malfunction.
Note: Each increment or decrement of bit 4 to 7 will introduce 100ps delay or advance on all of the above clocks.
Byte 22: Output Rise/Fall Time Select Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 0 0 0 0
Description 24,48MHz 0=Normal, 1=Weak IOAPIC/REF 0=Normal, 1=Weak PCI 0=Normal, 1=Weak SDRAM_F 0=Normal, 1=Weak SDRAM [0:11] 0=Normal, 1=Weak 3V66 0=Normal, 1=Weak CPU1 0=Normal, 1=Weak CPU0 0=Normal, 1=Weak
Notes: 1. PWD = Power on Default 2. The power on default for byte 16-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure to read back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass. 3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-22 will lose their default power up value.
Notes: 1. PWD = Power on Default
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ICS94203
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Timing Relationship Table1
Group CPU 66MHz SDRAM 100MHz Offset CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to PCI USB & DOT 2.5ns 7.5ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 100MHz SDRAM 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz SDRAM 100MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz SDRAM 133MHz Offset 3.75ns 0.0ns 3.75ns 1.5 -3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A
Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70 C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2 VDD+0.3 V Input High Voltage VIH VSS-0.3 0.8 V Input Low Voltage VIL Input High Current IIH VIN = VDD 5 A Input Low Current IIL1 VIN=0 V;Inputs with no pull-up resistors -5 uA Input Low Current IIL2 VIN=0 V; Inputs with pull-up resistors -200 uA Supply Current IDD3.3OP100 CL=30 pF 346 400 mA Power Down PD 4.3 600 mA 12 14.318 16 MHz Input frequency Fi VDD = 3.3 V; CIN Logic Inputs 5 pF Logic Inputs 5 pF Input Capacitance1 CIN CINX X1 & X2 pins 27 45 pF Clk Stabilization1 TSTAB From VDD= 3.3 V to 1% target Freq. 3 ms
1
Guaranteed by design, not 100% tested in production.
11
ICS94203
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 RDSP2B VO = VDD*(0.5) Output Impedance 1 RDSN2B VO = VDD*(0.5) Output Impedance VOH2B IOH = -1 mA Output High Voltage IOL = 1 mA VOL2B Output Low Voltage VOH @ MIN = 1.0 V IOH2B Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL2B Output Low Current VOL @ MAX = 0.3 V 1 tr2B VOL = 0.4 V, VOH = 2.0 V Rise Time Fall Time
1 1 1
MIN 13.5 13.5 2
-27 27 0.4 0.4 45
TYP 20 27 2.5 0.18 -51 -11 41 15 1 1 49 40 245 160 290
MAX UNITS 45 45 V 0.4 V -27 mA mA ns ns % ps ps
30 1.6 1.6 55 175 250 250 250
tf2B dt2B tsk2B
1
VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V, CPU=66 MHz VT = 1.25 V, CPU=100 MHz VT = 1.25 V, CPU=133 MHz
Duty Cycle
Skew window
Jitter, Cycle-to-cycle
1
tjcyc-cyc
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP1B VO = VDD*(0.5) 1 VO = VDD*(0.5) Output Impedance RDSN1B IOH = -1 mA Output High Voltage VOH1 IOL = 1 mA Output Low Voltage VOL1 VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 12 12 2.4
-27 29 0.5 0.5 45
TYP 17.4 22.4 3.3 0.009 -68 -14 77 24 1.4 1.7 49 35 292
MAX UNITS 55 55 V 0.55 V -29 mA mA ns ns % ps ps
27 2 2 55 175 500
tr1 tf1 dt1 tsk1 tjcyc-cyc1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
12
ICS94203
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) CONDITIONS PARAMETER SYMBOL 1 Output Impedance RDSP4B VO = VDD*(0.5) 1 VO = VDD*(0.5) Output Impedance RDSN4B Output High Voltage VOH4B IOH = -1 mA IOL = 1 mA Output Low Voltage VOL4B VOH @ MIN = 1.0 V IOH4B Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL4B Output Low Current VOL @ MAX = 0.3 V Rise Time1 Fall Time Duty Cycle1 Jitter, Cycle-to-cycle1
1 1
MIN 9 9 2
-27 27 0.4 0.4 45
TYP 28 28 2.4 0.25 -62 -12 35 8 1.45 0.97 49.3 130
MAX UNITS 30 30 V 0.4 V -27 mA mA ns ns % ps
30 1.6 1.6 55 500
tr4B tf4B dt4B tjcyc-cyc4B
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP3B VO = VDD*(0.5) Output Impedance RDSN3B1 Output High Voltage VOH3 IOH = -1 mA Output Low Voltage VOL3 IOL = 1 mA VOH @ MIN = 2.0 V IOH3 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL3 Output Low Current VOL @ MAX = 0.4 V Rise Time Fall Time
1
MIN 10 10 2.4
-54 54 0.4 0.4 45
TYP 16 17.5 3.3 0.01 -70 -29 90 28 0.9 0.8 49.2 83 214
MAX UNITS 24 24 V 0.4 V -46 mA mA ns ns % ps ps
53 1.6 1.6 55 250 250
tr3 tf3 dt3
1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, CPU=66,100,133 MHz
1 1
Duty Cycle Skew window1 Jitter, Cycle-to-cycle
1
tsk3 tjcyc-cyc3
Guaranteed by design, not 100% tested in production.
13
ICS94203
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP1B VO = VDD*(0.5) 1 VO = VDD*(0.5) Output Impedance RDSN1B IOH = -1 mA Output High Voltage VOH1 IOL = 1 mA Output Low Voltage VOL1 VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 12 12 2.4
-27 29 0.5 0.5 45
TYP 17.4 22.4 3.3 0.009 -67 -14 77 24 1.7 1.9 51 213 285
MAX UNITS 55 55 V 0.55 V -29 mA mA ns ns % ps ps
27 2.5 2.5 55 500 500
tr1 tf1 dt1 tsk1 tjcyc-cyc1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP5B VO = VDD*(0.5) Output Impedance RDSN5B1 VO = VDD*(0.5) Output High Voltage VOH15 IOH = -1 mA IOL = 1 mA Output Low Voltage VOL5 VOH @ MIN = 1.0 V IOH5 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL5 Output Low Current VOL @ MAX = 0.4 V Rise Time Fall Time
1 1
MIN 15 15 2.4
-33 27 0.4 0.4 45
TYP 18 18.75 3.27 0.025 -76 -12 71 22 1 1.7 54.1
MAX UNITS 60 60 V 0.4 V -33 mA 29 4 4 55 mA ns ns %
tr5 tf5 dt5
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V
1 1
Duty Cycle
Guaranteed by design, not 100% tested in production.
14
ICS94203
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS94203 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
15
ICS94203
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
16
ICS94203
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz CPU 100MHz CPU 133MHz
SDRAM 100MHz SDRAM 133MHz
3.5V 66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz
Group Offset Waveforms
17
ICS94203
SYMBOL
In Millimeters COMMON DIMENSIONS MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MAX .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 28 34 48 56 64
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MAX 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inch) MAX .380 .455 .630 .730 .830
Ordering Information
ICS94203yF-T
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
18
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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