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HV9120 HV9123 High-Voltage Current-Mode PWM Controller
Ordering Information
+VIN Min 10V 10V Max 450V 450V Feedback Accuracy <2% <2% Max Duty Cycle 49% 99% 16 Pin Plastic DIP HV9120P HV9123P Package Options 16 Pin 20 Pin SOIC Plastic PLCC HV9120NG HV9120PJ HV9123NG HV9123PJ DIE HV9120X HV9123X
Standard temperature range for all parts is industrial (-40 to +85C).
Features
10 to 450V input acceptance range <1.3mA supply current >1.0MHz clock >20:1 dynamic range @ 500KHz Low internal noise
General Description
The Supertex HV9120 and HV9123 are Switch Mode Power Supply (SMPS) controller subsystems that can start and run directly from almost any DC input, from a 12V battery to a rectified and filtered 240V AC line. They contain all the elements required to build a single-switch converter except for the switch, magnetic assembly, output rectifier(s) and filter(s). A unique input circuit allows the 912x to self-start directly from a high voltage input, and subsequently take the power to operate from one of the outputs of the converter it is controlling, allowing very efficient operation while maintaining input-to-output galvanic isolation limited in voltage only by the insulation system of the associated magnetic assembly. A 2% internal bandgap reference, internal operational amplifier, very high speed comparator, and output buffer allow production of rugged, high performance, high efficiency power supplies of 50 watts or more, which can still be over 80% efficient at outputs of 1.0W or less. The wide dynamic range of the controller system allows designs with extremely wide line and load variations with much less difficulty and much higher efficiency than usual. The exceptionally wide input voltage acceptance range also allows much better usage of energy stored in input dropout capacitors than with other PWM ICs. Remote on/off controls allow either latching or nonlatching remote shutdown. During shutdown, power required is under 6.0mW.
Applications
Off-line high frequency power supplies Universal input power supplies High density power supplies Very high efficiency power supplies Extra wide load range power supplies
Absolute Maximum Ratings
Voltages are referenced to -VIN +VIN Input Voltage VDD Device Supply Voltage Logic Input Voltages Linear Input Voltages IIN Preregulator Input Current (continuous) Tj Operating Junction Temperature Storage Temperature Power Dissipation, PDIP Power Dissipation PLCC Power Dissipation SOIC 450V 15.5V -0.3 to VDD + 0.3V -0.3 to VDD + 0.3V 2.5mA 150 C -65C to 150C 1000mW 1400mW 900mW
For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24.
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
HV9120/HV9123
Electrical Characteristics
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390K, ROSC = 330K,TA = 25C.) Symbol Parameters Min Typ Max Unit Conditions
Reference
VREF Output Voltage 3.92 3.84 ZOUT ISHORT VREF Output Impedance1 Short Circuit Current Change in VREF with Temperature1 15 4.00 4.00 30 125 0.25 4.08 4.16 45 250 K A mV/C VREF = -VIN TA = -55C to 125C V RL = 10M RL = 10M, TA = -55C to 125C
Oscillator
fMAX fOSC VOSC TCOSC Oscillator Frequency Initial Accuracy2 1.0 80 160 Voltage Stability Temperature Coefficient1 170 3.0 100 200 120 240 15 % ppm/C MHz KHz ROSC = 0 ROSC = 330K ROSC = 150K 9.5V < VDD <13.5V TA = -55C to 125C
PWM
DMAX Maximum Duty Cycle1 HV9120 HV9123 Deadtime1 DMIN Minimum Duty Cycle Minimum Pulse Width Before Pulse Drops Out 1 80 HV9123 49.0 95 49.4 97 225 0 125 49.6 99 nsec % nsec %
Current Limit
Vlim td Maximum Input Signal Delay to Output1 1.0 1.2 80 1.4 150 V ns VFB = 0V VSENSE = 1.5V, VCOMP 2.0V
Error Amplifier
VFB IIN VOS AVOL GB ZOUT ISOURCE ISINK PSRR Feedback Voltage Input Bias Current Input Offset Voltage Open Loop Voltage Unity Gain Output Gain1 60 1.0 3.92 4.00 25 4.08 500 V nA VFB Shorted to Comp VFB = 4.0V
nulled during trim 80 1.3 see fig. 1 -1.4 0.12 -2.0 0.15 see fig. 2 dB MHz mA mA dB VFB = 3.4V VFB = 4.5V
Bandwidth1
Impedance1
Output Source Current Output Sink Current Power Supply Rejection1
Notes: 1. Guaranteed by design. Not subject to production test. 2. Stray C on OSC IN pin must be 5pF.
2
HV9120/HV9123
Electrical Characteristics
Symbol Parameters
(continued)
Min Typ Max Unit Conditions
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390K, ROSC = 330K,TA = 25C.)
Pre-regulator/Startup
+VIN +IIN VTH VLOCK Input Voltage Input Leakage Current VDD Pre-regulator Turn-off Threshold Voltage Undervoltage Lockout 8.0 7.0 8.7 8.1 450 10 9.4 8.9 V A V V IIN < 10A; VCC > 9.4V VDD > 9.4V IPREREG = 10A
Supply
IDD IQ IBIAS VDD Supply Current Quiescent Supply Current Nominal Bias Current Operating Range 9.0 0.75 0.55 20 13.5 1.3 mA mA A V CL < 75pF Shutdown = -VIN
Shutdown Logic
tSD tSW tRW tLW VIL VIH IIH IIL Shutdown Delay1 Shutdown Pulse Width1 RESET Pulse Width1 Latching Pulse Width1 50 50 25 2.0 7.0 1.0 -25 5.0 -35 50 100 ns ns ns ns V V A A VIN = VDD VIN = 0V Shutdown and reset low CL = 500pF, VSENSE = -VIN
Input Low Voltage Input High Voltage Input Current, Input Voltage High Input Current, Input Voltage Low
Output
VOH Output High Voltage VDD -0.25 VDD -0.3 VOL Output Low Voltage 0.2 0.3 ROUT Output Resistance Pull Up Pull Down Pull Up Pull Down tR tF Rise Fall Time1 15 8.0 20 10 30 20 25 20 30 30 75 75 ns ns IOUT = 10mA, TA = -55C to 125C CL = 500pF CL = 500pF V V IOUT = 10mA IOUT = 10mA, TA = -55C to 125C IOUT = -10mA IOUT = -10mA, TA = -55C to 125C IOUT = 10mA
Time1
Note: 1. Guaranteed by design. Not subject to production test.
3
HV9120/HV9123
Truth Table
Shutdown H H L L LH Reset H HL H L L Output Normal Operation Normal Operation, No Change Off, Not Latched Off, Latched Off, Latched, No Change
Shutdown Timing Waveforms
1.5V Sense 0 td VDD Output 0 90% Output VDD 0 50% tR 10ns Shutdown 0 t SD 90% VDD 50% tF 10ns
t SW VDD Shutdown 50% 0 t LW VDD Reset 50% 0 t RW 50% 50% 50% tR, tF 10ns
Functional Block Diagram
FB 15 (19) COMP Discharge 14 (18) 10 (12) Error Amplifier - 11 (14) VREF REF GEN + 4V + S + - 16 (20) BIAS 7 (9) VDD 1 (3) +V IN - + 8.1V 8.6V - + Undervoltage Comparator Q R S 13 (17) Reset Current Sources To Internal Circuits Current Limit Comparator 6 (8)
-V IN
OSC In 9 (11)
OSC Out 8 (10)
OSC 2V - Modulator Comparator T R Q 9123 9120 Q To V DD 5 (6) Output
1.2V 4 (5) V DD 12 (16) Shutdown Sense
Pre-regulator/Startup
Pin number in parentheses are for PLCC package. 4
HV9120/HV9123
Typical Performance Curves
Fig. 1
10
6
Error Amplifier Output Impedance (Z0)
Fig. 4
1M
Output Switching Frequency vs. Oscillator Resistance
105 104 HV9123
ZO ()
10
3
fOUT (Hz)
100k
HV9120
102
10
1
.1 100
1K
10K
100K
1M
10M
10k 10k
100 k
1M
Frequency (Hz)
ROSC ()
Fig. 2
0 -10 -20
PSRR -- Error Amplifier and Reference
Fig. 5
80 70 60 50
Error Amplifier Open Loop Gain/Phase
180 120 60 0 -60 -120 -180
PSSR (dB)
40 30 20 10 0 -10
-40 -50 -60 -70 -80 110
100
1K
10K
100K
1M
100
1K
10K
100K
1M
Frequency (Hz)
Frequency (Hz)
Fig. 3
100
Fig. 6
104
RDISCHARGE vs. tOFF (9123 only)
Bias Current (A)
VDD = 12V
ROSC = 100K
tOFF (nsec)
VDD = 10V 10
103
ROSC = 10K
ROSC = 1K 1 105 106 107 102 10-1 100 101 102 103 104 105 106
Bias Resistance ()
RDISCHARGE ()
5
Phase (C)
Gain (dB)
-30
HV9120/HV9123
Test Circuits
Error Amp ZOUT
0.1V swept 10Hz - 1MHz
+10V (VDD) 1.0V swept 100Hz - 2.2MHz 60.4K
-
PSRR
100K1% 10.0V 100K1% 4.00V
- +
(FB) Reference GND (-VIN) 0.1F
+
V1
Tektronix P6021 (1 turn secondary)
V1
V2 40.2K
Reference 0.1F
V2
NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE 1mV before connecting transformer
Detailed Description
Preregulator
The preregulator/startup circuit for the HV912x consists of a highvoltage n-channel depletion-mode DMOS transistor driven by an error amplifier to form a variable current path between the VIN terminal and the VDD terminal. Maximum current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source (generally the supply the chip is controlling) no current other than leakage is drawn through the high voltage transistor. This minimizes dissipation. An external capacitor between VDD and VSS is generally required to store energy used by the chip in the time between shutoff of the high voltage path and the VDD supply's output rising enough to take over powering the chip. This capacitor should have a value of 100X or more the effective gate capacitance of the MOSFET being driven, i.e., Cstorage 100 x (gate charge of FET at 10V / 10V) as well as very good high frequency characteristics. Stacked polyester or ceramic caps work well. Electrolytic capacitors are generally not suitable. A common resistor divider string is used to monitor VDD for both the undervoltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the undervoltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the undervoltage lockout always releases before the FET shuts off. the 50% maximum duty cycle versions, a frequency dividing flipflop. A single external resistor between the OSC In and OSC Out pins is required to set oscillator frequency (see graph). For the 50% maximum duty cycle versions the Discharge pin is internally connected to VSS (ground). For the 99% duty cycle version, Discharge can either be connected to VSS directly or connected to VSS through a resistor used to set a deadtime. One difference exists between the Supertex HV912x and competitive 912x's: The oscillator is shut off when a shutoff command is received. This saves about 150A of quiescent current, which aids in the construction of power supplies to meet CCITT specification I-430, and in other situations where an absolute minimum of quiescent power dissipation is required.
Reference
The Reference of the HV912x consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier when connected in a gain of -1 configuration is as close to 4.000V as possible. This nulls out any input offset of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4.0V, the feedback voltage required for proper regulation will be. A 50K resistor is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and non-inverting input to the error amplifier). This allows overriding the internal reference with a low-impedance voltage source 6.0V. Using an external reference reinstates the input offset voltage of the error amplifier, and its effect of the exact value of feedback voltage required. In general, because the reference voltage of the Supertex HV912x is not noisy, as some previous examples have been, overriding the reference should seldom be necessary. Because the reference of the 912x is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and VSS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1F. 6
Bias Circuit
An external bias resistor, connected between the bias pin and VSS is required by the HV912x to set currents in a series of current mirrors used by the analog sections of the chip. Nominal external bias current requirement is 15 to 20A, which can be set by a 390K to 510K resistor if a 10V VDD is used, or a 510k to 680K resistor if VDD will be 12V. A precision resistor is not required; 5% is fine.
Clock Oscillator
The clock oscillator of the HV912x consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and, in
HV9120/HV9123
Detailed Description
Error Amplifier
(continued) Remote Shutdown
The shutdown and reset pins of the HV912x can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open-drain logic. When not used they should be left open, or connected to VDD.
The error amplifier in the HV912x is a true low-power differential input operational amplifier intended for around-the-amplifier compensation. It is of mixed CMOS-bipolar construction: A PMOS input stage is used so the common-mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity-gain stable.
Output Buffer
The output buffer of the HV912x is of standard CMOS construction (P-channel pull-up, N-channel pull-down). Thus the bodydrain diodes of the output stage can be used for spike clipping if necessary, and external Schottky diode clamping of the output is not required.
Current Sense Comparators
The HV912x uses a true dual comparator system with independent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction.
18
17
16
+VIN NC NC Sense Output -VIN VDD OSC Out
15
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
BIAS FB COMP Reset Shutdown VREF Discharge OSC In +VIN
3 9
FB BIAS NC NC
19
VREF
14
NC
Pinout
Shutdown
COMP
Reset
13
NC Discharge OSC In OSC Out VDD
20
12
1
*
11
2
10
16 Pin Dip Package top view
4 5 6 7 8
Output
Sense
+VIN
1
16 15 14
BIAS FB COMP Reset Shutdown VREF Discharge OSC In
20-pin PJ Package top view
Sense Output -VIN VDD OSC Out
4 5 6 7 8
13 12 11 10 9
16 Pin SOIC top view
Note: Pins 2 and 3 are removed 11/12/01
(c)2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com
-VIN
NC
NC

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