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ST75951
V.34/56K ANALOG FRONT END
. . . . . . . . . . . . . . . .
V.34/56K MODEM ANALOG FRONT-END (AFE) 16 BITS OVERSAMPLING SIGMA DELTA A/D AND D/A CONVERTERS 85dB DYNAMIC RANGE PROGRAMMABLE SAMPLING FREQUENCY AUXILIARY ANALOG INPUT MODEM SIDE OF SILICON DATA ACCESS ARRANGEMENT (DAA) INTEGRATED WITH AFE KRYPTON ISOLATION INC. PATENTED TECHNOLOGY ELIMINATE TRANSFORMER OR LINEAR OPTO-COUPLERS RING DETECT, LINE IN USE, CLID AND OVER LOOP CURRENT DETECT 4 GPIO ASSOCIATED WITH 1 GENERAL PURPOSE INTERRUPT OUTPUT ANALOG AND DIGITAL LOOP-BACK MODE SYNCHRONOUS SERIAL INTERFACE FOR PROCESSORS DATA EXCHANGE ON CHIP REFERENCE VOLTAGE SINGLE POWER SUPPLY RANGE : 2.7V TO 5.25V LOW POWER CONSUMPTION : 40mW @ 3.3V TQFP48 PACKAGE 0.5M CMOS PROCESS
TQFP48 (7 x 7 x 1.4mm) (Full Plastic Quad Flat Pack) ORDER CODE : ST75951
DESCRIPTION ST75951 is an analog front-end designed to implement modems application up to 56Kbps. ST75951 interfaces between DSP or HSP signals and capacitive isolation barrier. A complete D.A.A. is made with ST952 which interfaces between capacitive isolation barrier and the telephone line. Figure 1
Tip Digital
75951-30.EPS
ST75951 Digital
ST952
Ring
It integrates a high resolution A/D and D/A converter and incorporates Krypton Isolation Inc. patented silicon D.A.A. technology.
February 1999 1/21
ST75951
PIN CONNECTIONS
TSTA2 TSTA1 VCMS VCMP NC NC D1 D2 D3 D4 D5 D6
36 35 34 33 32 31 30 29 28 27 26 25 NC AGND2 VCM AVDD AUXIN HM RESET TS TSTD1 DIN DOUT NC 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC AGND1 VREFN VREFP GPIO0 GPIO1 GPIO2 GPIO3 GPI RING M/S NC
MCM
FS
DGND
NC
XTALOUT
XTALIN (MCLK)
PWRDWN
HC1
SCLK
DVDD
HC0
NC
2/21
75951-01.EPS
ST75951
PIN LIST
Pin Number 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 33 34 35 38 39 40 41 42 43 44 45 46 47 Name SCLK FS MCM DVDD DGND XTALOUT XTALIN HC1 HC0 PWRDWN M/S RING GPI GPIO3 GPIO2 GPIO1 GPIO0 VREFP VREFN AGND1 D6 D5 TSTA1 VCMP D4 D3 VCMS TSTA2 D2 D1 AGND2 VCM AVDD AUXIN HM RESET TS TSTD1 DIN DOUT Type O I/O I I I O I I I I I O O I/O I/O I/O I/O O O I O O O I I I I O O O I O I I I I I I I O Description Bit Shift Clock Output , SCLK = Coeff FS Frame Synchronization Input (Slave)/Output (Master) Master Clock Mode Positive Digital Power Supply Digital Ground (0V) (see Note1) Crystal Output Crystal Input Hardware Control Input Hardware Control Input Power Down Input Master/slave Control Input Ring Detect Output General Purpose Interrupt Output General Purpose Control Input/Output General Purpose Control Input/Output General Purpose Control Input/ Output General Purpose Control Input/Output Positive Reference Voltage Negative Reference Voltage Analog Ground (0V) (see Note1) ST952 Control Output ST952 Control Output Reserved for test Common Mode Voltage Input P Receive Input Receive Input Common Mode Voltage Input S Reserved for test Transmit Output Transmit Output Analog Ground (0V) (see Note1) Common Mode Voltage Output Positive Analog Power Supply Receive Auxiliary Analog Input Amplifier Hardware Control Input for Clid/Off-hook Reset Function to initialize the device Timeslot Control Input Serial Data Input Serial Data Output
75951-01.TBL
Reserved for Test (must be grounded in normal mode)
Note 1 : Digital and Analog ground must be connected externally together.
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ST75951
PIN DESCRIPTION 1 - Power Supply (5 Pins) 1.1 - Power Supply (AVDD, DVDD) These pins are the positive analog and digital power supply input (2.7 to 5.25V). In any case, the AVDD voltage must always be higher or equal to the DVDD voltage (AVDD DVDD). 1.2 - Analog Ground ( AGND1, AGND2) These pins are the ground return of the DAC and ADC analog section. 1.3 - Digital ground (DGND) This pin is the ground return of the digital circuitry. Note : In order to obtain published performances, the analog AVDD and digital DVDD should be decoupled with respect to analog ground and digital ground, respectively. Decoupling capacitors should be as close as possible to the supplies pins. All ground must be tied together. In the following section the ground is referred as : GND. 2 - Serial Synchronous Interface (4 Pins) 2.1 Data (DIN, DOUT) Digital data word input/output of the SSI (16 bits data). 2.2 - Frame Synchronization (FS) The frame synchronization is used to indicate that the device is ready to send and receive data. The data transfer begins on the falling edge of frame-sync signal. The frame-SYNC can be generated internally or externally. 2.3 Serial Bit Clock (SCLK) Clocks the digital data into DIN and out of DOUT during the frame synchronization interval. The serial bit clock is generated internally and equal to MCLK/R (R programmed value in register 3). The serial bit clock is a multiple of FS. 3 - Control Pins (10 Pins) 3.1 - Reset (RESET) This pin initializes the internal counters and control registers to their default value. A minimum low pulse of 100ns is required to reset the chip. 3.2 - Power-Down (PWRDWN) This input powers down the entire chip. In power down mode the existing internally programmed state is maintained. When power down is driven high, full operation resumes after 1ms. A software powerdown with wake-up on ring detect is also provided with bit 4 in control register 3. 3.3 - Hardware Control (HC0, HC1) These pins are used for hardware/software control programmation of the device. 3.4 - Hardware Control (HM) This pin is used for hardware/software control of CLID/OFFHOOK function. 3.5 - Master/Slave (M/S) When M/S = " 1 " the device is in master mode and FS is generated internally otherwise the device is in slave mode and Fs must be provided externally and equal to SCLK*R / OVER. 3.6 - Timeslot Control (TS) When TS = " 0 " the data are assigned to the first timeslot (1st 16 bits after falling edge of FS) otherwise the data are on the second timeslot (bits 17 to 32). 3.7 - Control (D5, D6) These pins transmit the control signals trough isolation capacitors to ST952 which converts and outputs the appropriate control signals. 3.8 - Master Clock Mode (MCM) When MCM = " 1 ", we have FS = Master Clock/[M Q OVER] otherwise we have FS = Master Clock/OVER and the M, Q dividers are bypassed. 4 - General Purpose Input/Output Circuitry 4.1 - GPIO (4 Pins) ST75951 offers 4 general purpose Input/Output pins. The setting of the GPIO configuration is done through the control register 1 and the signal level of the GPIO are reflected in the feedback register 2. At power on the GPIO are programmed as inputs. In order to take into account the evolution of ST952, thanks to the control register we will be able to send a clock signal equal to F0/N (N programmed in register 2) on GPIO0 and F0 on GPIO3. When in DAA control hardware mode HM = 1, the CLID and OFF-HOOK control is done by Pin GPIO1 (CLID) and GPIO2 (OFF-HOOK), otherwise when HM = 0 then the CLID/OFF-HOOK control is done by programming the adequate bit in the control register 3 (Bit 2 , Bit 3, see Table 7).
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ST75951
PIN DESCRIPTION (continued) 4.2 - General Purpose Interrupt System (GPI) The GPI will reflect any change of the GPIO'S inputs or RING output when non-masked, so the processor does not need to read the output control word continuously. GPI level change tells the processor, one of the non-masked input pins level has changed and he can read the control word. So GPIO could extend the number of interrupt pins of the processor. 5 - Ring This pin is used for the Ring detect but also reports the Line status, current limit. 6 - Digital Test Pin (TSTD1) This pin is reserved for digital test purpose. 7 - Crystal (XTALIN , XTALOUT) These pins must be tied to an external crystal or a master clock generator (MCLK). 8 - Analog Interface (12 Pins) 8.1 - DAC and ADC Reference Voltage Output (VREFP, VREFN ) These pins provide the positive and negative reference Voltage used by the 16-bit converters. The reference voltage, VREF, is the voltage difference between the VREFP and VREFN outputs. VREFP and VREFN should be externally decoupled with respect to VCM. 8.2 - Common Mode Voltage Output (VCM) This output pin is the common mode voltage (AVDD - AGND)/2 . This output must be decoupled with respect to GND. 8.3 - Common Mode Voltage Input (VCMP, VCMS) These input pins are the common mode voltage for internal circuitry. They have to be connected externally to VCM. 8.4 - Analog Transmit Output (D1 ,D2) These pins are the output of the fully differential converted analog signal, modulated at F0 (1MHz < F0 < 1.7MHz). The digital data IN signal is converted in analog signals (with (Sin X)/X compensation). Two ranges of signal amplitude have to be considered ; modem application with dynamic up to 2.5VPP with maximum performances SNDR = 83dB, voice application with dynamic up to 3.2VPP differential (SNDR = 75dB). The transmit output stage can be programmed to +2dB gain, 0db gain, 6dB or infinite attenuation. 8.5 - Analog Receive Inputs (D3, D4) These pins are the differential analog inputs. These analog inputs are presented to the F0 demodulator and the sigma-delta modulator. The analog input peak-to-peak differential signal range must be less than 2.5 VPP. The gain of the receive stage is programmable to 0dB or 6dB. 8.6. - Analog Test Pin (TSTA1, TSTA2) These pins are reserved for analog test purpose. 8.7 Analog Auxiliary Receive Inputs (AUXIN) This pin is the auxiliary analog input. This analog input is presented to the analog modulator. The analog input peak-to-peak signal range must be less than 1.25 VPP. The gain of the receive stage is 0dB.
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ST75951
BLOCK DIAGRAM
VCMS VCMP DVDD DGND AVDD AGND1 AGND2 VCM VREFN VREFP RESET PWRDWN HC0 HC1
32
AUXIN 41
29
5
6
40
23
38
39
22
21
43
11
10
9
F0 D3 31 D4 30 HIGH PASS FILTER LOW PASS FILTER
REFERENCE VOLTAGE
GAIN
MUX
ANALOG MODULATOR
SERIAL PORTS AND CONTROL REGISTER
LOW-PASS (0.425 x Sampling Frequency)
45 TSTD1 3 2 47 46 44
FS SCLK DOUT DIN TS
Bit DR RING 15 MUX
DETECTOR
F0 D1 35 GAIN 2dB GAIN 0dB ATTE 6dB ATTE INFINITE DAC 1 BIT First Order Differential Switched Capacitor Filter
D2 34
2nd ORDER MODULATOR
LOW-PASS (0.425 x Sampling Frequency)
CLOCK GENERATOR
DAA CONTROL + GPIO
16 17
GPI
STLC75951
D5 TSTA1 TSTA2 D6 M/S MCM XTALIN XTALOUT (MCLK) HM GPIO0 GPIO1 GPIO2 GPIO3
75951-02.EPS
28
33
27
26
14
4
8
7
42
20
19
18
FUNCTIONAL DESCRIPTION ST75951 is a modem AFE front-end integrating the modem side of Krypton K951 and fully compatible to work with ST952. 1 - Transmit Section The functions included in the transmit section are : - D/A converter, - F0 modulator, - Programmable stage +2dB gain, 0dB gain, 6dB attenuation or infinite attenuation, - Transmit Filter including noise shaper and Sinx/x correction. The digital base Band data (DIN) are converted and modulated at F0 and send differentially (D1, D2) to ST952 through capacitive connection. 2 - Receive Section The functions included in the receive section are : - Main and Aux inputs, - Programmable gain 0/6dB, - A/D converter, - F0 demodulator, - Receive filter. The analog differential Main input signal (D3, D4) coming from ST952 is demodulated at F0, goes to the multiplexer and gain receive block then is digitally converted and output on DOUT which is the base band data. Thanks to the multiplexer, we can also process base band analog signal on AUXIN. 3 - Clock Generator ST75951 generates all clocks from either a Master clock input on XTALIN (MCLK) or a crystal oscillator connected between XTALIN and XTALOUT. The bypass of the divider M and Q is selected by setting the MCM input pin to '0'. To be able to provide externally the sampling frequency (Slave mode), M/S input pin must be set to '0' (see Figure 2).
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ST75951
FUNCTIONAL DESCRIPTION (continued) Figure 2
XTALIN (MCLK) XTALOUT MCM SCLK M/S
8
7
4
2
14
%R Sync VDD %M %Q % OVER
3 FS
%2 D5 27 F0 D6 26 %2
Internal Sampling Frequency F0 or F0/2
GPIO2 or OH
GPIO1 or CL
4 - Power Down Mode Two PowerDown modes are available in ST75951 thanks to bit 4 in control register 3. 4.1 - PowerDown Mode 0 If bit 4 is set to '0' then when PWRDWN is set to '0' the entire chip is in powerdown mode 0. Figure 3
REG3 BIT4 = 0
75951-04.EPS
tomer feature associated with a defined GPIO (programmed as input and non-masked). 4.2.1 - Ring Bit and GPIO Bit Masked In this configuration the processor relies on the Ring output pin to process the wake-up of the system and does not need the SSI to be poweredon. The SSI will be put back in operative mode when PWRDWN is set to '1' (see Figure 4). 4.2.2 - Ring Bit or GPIO Bit Non-Masked In this configuration the processor relies on the SSI to process the wake-up of the system and needs the SSI to be powered-on. On an incoming Ring signal or an interrupt coming thanks to the GPIO, ST75951 will generate an interrupt on GPI output pin and power-up the SSI, the processor will be able to read the control register 2 and find out the origine of the interrupt. After a reading of the register 2, if the processor does not set high PWRDWN ST75951 puts back the SSI off in order to save energy (see Figure 5).
Normal PWRDWN Power Down 0
Normal
4.2 - PowerDown Mode 1 (100W) When bit 4 is set to '1' then when PWRDWN is set to '0' the chip is in powerdown except the Ring detect circuitry (wake-up on Ring = powerdown mode 1). The general purpose interrupt is also working in order to wake-up the system for dedicated cus-
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75951-03.EPS
ST75951
FUNCTIONAL DESCRIPTION (continued) Figure 4
REG3 BIT4 = 1 Normal PWRDWN Wake-up on Ring Ring Output Pin GPI '1' SSI ON OFF ON
75951-05.EPS
Off-Hook
Ring
Figure 5
REG3 BIT4 = 1 Normal PWRDWN Wake-up on Interrupt Ring or non-masked GPIO GPI Ring
Processor reads REG2 ST75951 resets Bit GPI
Off-Hook
Ring
SSI
ON
OFF
ON
OFF
ON
OFF ON
5 - Mode of Operation Thanks to MCM and M/S programmation pins we can get the following configuration. Configuration 1 : MCM = M/S = '1'. ST75951 is in master mode and we have : FS = FQ / (M x Q x OVER). FS is an output. (see Figure 6). Configuration 2 : MCM = '1', M/S = ' 0 '. ST75951 is in slave mode and the processor provides FS = (R x SCLK) OVER. FS is an input (see Figure 7). Configuration 3 : MCM = '0', M/S = '1'. ST75951 is in master mode and we have : FS = FQ / (OVER). FS is an output (see Figure 8).
Configuration 4 : MCM = '0', M/S = ' 0 '. The configuration 4 is equivalent to configuration 3 but the processor generates the FS and control the phase. ST75951 is in slave mode and the processor provides FS = (R x SCLK)/OVER. FS is an input (see Figure 9). Configuration 5 : Master codec 1 : MCM = '0', M/S = ' 1 '. Slave codec 2 : MCM = '0', M/S = ' 0 '. This is a dual codec application running on the same SSI. The master codec has his data in timeslot 0 ( bit 0 to bit15 ) and the slave codec has his data in timeslot 1 (bit 16 to bit 31) thanks to the programmation of TS (see Figure 10).
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75951-06.EPS
ST75951
FUNCTIONAL DESCRIPTION (continued) Figure 6
fQ = 36.864MHz 18.432MHz 9.216MHz
Figure 9
fQ
8
8 P R O C E S S O R XTALIN 2 SCLK 3 FS 46 DIN 47 DOUT M/S 14 MCM 4 TS 44 VDD VDD GND
75951-07.EPS
fS = fQ / Over
fS = fQ / (M x Q x Over)
Figure 10
P R O C E S S O R 8 XTALIN 2 SCLK 3 FS 46 DIN 47 DOUT RESET 43 M/S 14 MCM 4 TS 44 Master Codec 1 VDD GND GND
Figure 7
fQ = 36.864MHz 18.432MHz 9.216MHz
8 P R O C E S S O R XTALIN 2 SCLK 3 FS 46 DIN 47 DOUT M/S 14 MCM 4 TS 44 GND VDD
43
GND
75951-08.EPS
RESET 8 XTALIN 2 SCLK 3 FS M/S 14 MCM 4 TS 44
Slave Codec 2
fS = fQ / (M x Q x Over)
Figure 8
STLC7546 Functional Mode fQ
GND
75951-11.EPS
46 DIN 47 DOUT
GND VDD
8 P R O C E S S O R XTALIN 2 SCLK 3 FS 46 DIN 47 DOUT M/S 14 MCM 4 TS 44 VDD GND GND
75951-09.EPS
6 - General Purpose Input / Output ST75951 features 4 GPIO. The GPIO0..3 are traditional inputs/outputs programmed and set thanks to the control register 1 (mask, input/output) and control register 2 (output value, static or modulated). GPIO0 output is dedicated to output F0/N clocks instead of a static '1' if bit 6 in control register 2 is set. GPIO3 is dedicated to output F0 clock instead of a static '1' if bit 10 in control register 2 is set (see Figure 11 and 12).
fS = fQ / Over
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75951-10.EPS
P R O C E S S O R
XTALIN 2 SCLK 3 FS 46 DIN 47 DOUT M/S 14 MCM 4 TS 44 GND GND GND
ST75951
FUNCTIONAL DESCRIPTION (continued) Figure 11 : GPIO0 When bit6 = '1' in REG2
GPIO0 F0/N GPIO0 REG 2 - BIT1 SETTING
75951-12.EPS
VDD PP
Figure 12 : GPIO3 When bit10 = '1' in REG2
GPIO3 F0 GPIO3 REG 2 - BIT4 SETTING
75951-13.EPS
VDD PP
D5 D6
HM 1 1 1 1 HM 0 0 0 0
GPIO1 0 0 1 1 CL 0 0 1 1
GPIO2 0 1 0 1 OH 0 1 0 1
Function ON-HOOK OFF-HOOK CLID SPECIAL Function ON-HOOK OFF-HOOK CLID SPECIAL
7.1 - ON-HOOK During ON-HOOK state no signal is sent by D5, D6. D5 = D6 = VDD.
Ring When in ON-HOOK state, the ST952 sends a 1MHz differential signal on D3, D4 when it receives an incoming ringing signal from Tip/Ring. ST75951 will output on RING Pin the image of the ring signal (RING Pin is also duplicated in the read register 2 bit 5) (see Figure 15).
7.2 - OFF-HOOK Depending on Pin HM status (see Table 2), 2 possibilities are offered to control the device to go in OFF-HOOK state. Figure 14
D5 VDD F0
CL, OH : Bit 2, 3 Reg 3. Depending of the setting of the Mask bit in control register 1, any change of non-masked GPIO can generate an interrupt to the processor thanks to GPI (General purpose Interrupt). 7 - Operating Modes Three operating modes controlled either by the GPIO1 and 2 or by the control register 3 are implemented : - ON-HOOK, - OFF-HOOK, - CLID (Caller ID).
D6
VDD F0
D5 and D6 send F0 clock in opposite phase to ST952.
10/21
75951-15.EPS
75951-14.EPS
GPIO1 and GPIO2 are dedicated input and control CLID and OFF-HOOK function respectively if the control input Pin HM is set to '1'. Table 2
Figure 13
ST75951
FUNCTIONAL DESCRIPTION (continued) Figure 15
D3 VCM 1MHz
D4
VCM 1MHz
RING BIT & OUTPUT D5 D6
75951-16.EPS
D5 = D6 = VDD. 7.3 - Caller ID Depending on Pin HM status (see Table 2), 2 possibilities are offered to control the device to go in caller ID state. F0 clock is send to D5, in caller ID mode the modulation frequency of ST952 is equal to F0/2, so the demodulation on the receive signal at D3, D4 is at F0/2 in caller ID mode. Figure 16
8 - Phone Line Monitoring Features This chipset is intended to be used for a wide range of application such as modem, answering machine, telephony on PC, so because the home PSTN phone line will be shared by several terminals, information concerning the line status has to be sent to the host. As long as there is an alerting signal at D3, D4 Pins, the ADC converter is saturated and outputs 7FFF or 8000 at DOUT Pin. 8.1 - Line In Use Checking Before going OFF-HOOK the modem software can check that the line is free by setting the CLID mode and check that the RING Pin/bit output a low pulse. When in CLID mode if the line is free the ST952 will output a F0/2, 5VPP differential signal on D3, D4 (see Figure 18). 8.2 - Digital Phone Line or Over Loop Current Limit Detect When portable modem plug into digital line, it will cause over loop current during modem off-hook state. The modem controller should know this condition and go onhook to avoid the DAA being damaged. ST952 when OFF-HOOK will determine if the loop current exceeds the current limit or not (160mA). If we have overcurrent ST952 will continuously output a low level on RING output Pin.
D5
D6
D6 = VDD. Figure 17
FO Output at D5 FO/2 Demod Control Signal Caller ID Mode Phase Relative Hip
75951-18.EPS
75951-17.EPS
VDD F0
11/21
ST75951
FUNCTIONAL DESCRIPTION (continued) Figure 18
D5 D6 D3 VCM F0
D4 Xms * RING
VCM
RING
Line in use, Ring = '1'
*Xms value is fixed by ST75952 application
Figure 19
D5 F0
D6
D3
F0
D4
F0
RING Overcurrent
2nd ORDER MODULATOR
LOW-PASS (0.425 x Sampling Frequency)
DIN
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75951-21.EPS
9 - Analog / Digital Loop Back Test By programming bit 9,8 = ' 01' of control register 3, we can set ST75951 in 'local analog loop back' (see Figure 20). By programming bit 9, 8 =' 10' of control register 3, we can set ST75951 in 'local digital loop back' (see Figure 21).
Figure 20
LOW-PASS (0.425 x Sampling Frequency) DOUT
75951-20.EPS
75951-19.EPS
Line Free
ST75951
FUNCTIONAL DESCRIPTION (continued) Figure 21
AUXIN 41 F0 or F0/2 D3 31 D4 30 HIGH PASS FILTER Bit DR DETECTOR RING 15 MUX F0 or F0/2 D1 35 ATTENUATION 0dB/6dB/Infinite D2 34 DAC 1 BIT FIRST ORDER DIFFERENTIAL SWITCHED CAPACITOR FILTER LOW PASS FILTER ANALOG MODULATOR
MUX
GAIN
10 - Host Interface Table 3
HC1 0 0 0 1 HC0 0 0 1 x LSB 0 1 x x 2nd FS no yes no yes Mode Description Software mode, data transfer only Software mode, data xfer + control xfer Hardware mode, data transfer only Hardware mode, data + control transfer
Second mode is a hardware mode control (16bits data transmit and receive). In this mode the access of control register is done via dynamic setting of Pins HC0 and HC1 (see Table 3). The bit 15 of the control word is used to do a read only or a read and write of control register (bit 15 = 1 Read only, bit 15 = 0 Read & Write). 11 - Control Registers This section defines how to handle the 4 registers implemented in ST75951. 11.1 - Write / Read Operation (D15 = 0) This is a one sampling frequency period duration operation, where the 16-bit word sent from the host on DIN, contains the write qualifier, the address register and the data field. Contemporaly ST75951 ouptuts on DOUT the register 2 value (GPIO) (see Figure 22).
The host interface is a Serial Synchronous Interface (FS, SCLK, DOUT, DIN). Two modes of serial transfer are available and are selected via pins HC0 and HC1. First mode is a software mode control (15 bits transmit data and 16 bits receive data). In this mode ST75951 is completely controlled through the SSI, the access of control register is done by managing the LSB of the transmit data word. Figure 22 : WRITE REG n , READ default REG 2
Sampling Period 1/2 Sampling Period FS D15
DI
DATA WORD INPUT
0
@regN+cont.word
D0 HC0 HC1
DATA WORD OUTPUT
REGISTER 2 VALUE
75951-23.EPS
10
01
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75951-22.EPS
ST75951
FUNCTIONAL DESCRIPTION (continued) Figure 23
Sampling Period 1/2 Sampling Period FS D15 FS D15 1/2 Sampling Period Sampling Period
DI
DATA WORD INPUT
1
@regN (read only)
DATA WORD INPUT
1
@reg2 (read only)
D0 HC0 HC1
DATA WORD OUTPUT
REGISTER 2 VALUE
DATA WORD OUTPUT
REGISTER N VALUE
10
10
01
11.2 - Read Operation (Register n) (D15 = 1) This is a two sampling frequency period duration operation, where a first 16 bit word sent from the host on DIN, contains the read qualifier and the address register (register n). Contemporaly ST75951 ouptuts on DOUT the register 2 (GPIO) while the address field is decoded. Then a second read operation with the default address (register 2) is sent to the device. At that Figure 25
SCLK Sampling Period, (128, 192, 256, 320 or 384) 1/2 Sampling Period FS D15 DIN D15 DOUT HC1 = 0 HC0 = 0 DIN D15 DOUT D15 DIN HC1 = 0 HC0 = 1 DOUT D15 DIN HC1 = 1 HC0 = X DOUT D15 DATA WORD OUPUT (16 BITS) DATA WORD INPUT (16 BITS) D0 D15 DATA WORD OUPUT (16 BITS) D0 DATA WORD INPUT (16 BITS) D0 DATA WORD OUPUT (16 BITS) D0 D15 DATA WORD INPUT (15 BITS) DATA WORD OUPUT (16 BITS) D1 D0 1 D0 DATA WORD INPUT (15 BITS) D1 D0 0 D0
time ST75951 outputs on DOUT the register n value (see Figure 23, 24 and 25). Figure 24
16 Bits Control Word Format
75951-25.EPS 75951-26.EPS
R/W D15
ad2
ad1
ad0
d11...............d0 D0
(Only if Control Mode Selected) D15
D15
D15 CONTROL WORD (16 BITS) D15 REGISTER VALUE (16 BITS)
D0
D15
D0
D15
D15
D15
D15 CONTROL WORD (16 BITS) D15 REGISTER VALUE (16 BITS)
D0
D15
D0
D15
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75951-24.EPS
ST75951
FUNCTIONAL DESCRIPTION (continued) Table 4 : Control Register 0 : AFE Setting
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0 1 0 1 0 1 Function Main Receive input (INI) Auxil. Receive input 0dB Receive Gain (INI) +6dB Receive Gain OVER = 320 (INI) OVER = 384 OVER = 128 OVER = 192 OVER = 256 - Infin. attenuation XMIT (INI) +2dB gain XMIT 6dB attenuation XMIT 0dB gain XMIT M=1 M = 2 (INI) Q=3 Q = 6 (INI) Q=7 Q=8 Q = 4.5 Q = 5.5 Q = 6.5 Q = 7.5
Table 5 : Control Register 1 : GPIO Setting, Ring Bit
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 1 1 MR M3 M2 M1 M0 DR Di3 Di2 Di1 Di0 Function DIR. '0' = (Inp INI), 1 = Out MASK for INT. GPI '0' masked (INI), '1' unmasked Digital Ring '1' on, '0' off (INI)
Table 6 : Control Register 2 : GPIO / RING Output Setting
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 S x 0 0 1 1 x 0 1 0 1 0 1 1 1 1 RG G3 G2 G1 G0 Function GPIOx output setting, read input Read only, Ring GPIO3 '0' In static Value (INI) if set GPIO3 modulated at F0 GPIO0 In static Value (INI) GPIO0 Modulate at F0 GPIO0 Modul. at F0/2 GPIO0 Modul. at F0/4 GPIO0 Modul. at F0/8
Note : GPI is in "high" state, any change on one Gx or RG non-masked put GPI in "low" state, one read on this register (@010) put GPI in "hight" state.
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ST75951
FUNCTIONAL DESCRIPTION (continued) Table 7 : Control Register 3 : Clock / configuration setting
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 OH CL 0 1 Function Software value (HM = 0) Normal operation (INI) PowerDown with wake-up on ring or non-masked GPIO Transmit modulated (INI) Transmit not modulated SCLK = MCLK (R = 1) SCLK = MCLK/2 (R = 2) (INI) SCLK = MCLK/4 (R = 4) Reserved Normal mode (INI) Analog loop back Digital loop back Reserved Normal mode (INI) Reserved TSTD1 Pin = PCLK output TSTD1 Pin = PCLK input
Below you'll find a table giving different programmation for achieving all common V.34 baud rate with ST75951 working with an external crystal fQ = 36.864 MHz. The 8kHz could be used for voice processing and the 16kHz for the 56K (V.pcm). Table 8
Baud Rate 3429 3000 3490 3429 2400/3200 3000 2953 2743 2400 FS 16000 13714.29 12000 10472.73 10285.71 9600 9000 8861.54 8228.57 8000 7200 Over 192 192 256 320 256 320 256 320 320 384 320 M 2 2 2 2 2 2 2 2 2 2 2 Q 6 7 6 5.5 7 6 8 6.5 7 6 8 F0 1536000 1316571 1536000 1675636 1316571 1536000 1152000 1417846 1316571 1536000 1152000
In any cases attention must be paid to have F0 between 1MHz and 1.7 MHz , optimum value beeing 1.5MHz. The modulator and demodulator frequency F0 = OVERSAMPLING FREQUENCY / 2. When MCM = ' 0', we have OVERSAMPLING FREQUENCY = MCLK and F0 = MCLK / 2 SCLK = MCLK / R (see clock block diagram). Table 9 : (eg : with R = 4)
fS (kHz) 8 9.6 9.6 16 16/21 M X X X X Q X X X X Over 384 320 256 192 MCLK (MHz) 3.072 3.072 2.4576 3.072 F0 (MKz) 1.536 1.536 1.2288 1.536 SCLK (kHz) 768 768 614.4 768
ST75951
ELECTRICAL SPECIFICATION Unless otherwise noted, Electrical characteristics are specified over the operating range. Typical value are given for VDD = 3.3V, TAMB = 25C. Initial value MCLK external = 3.072MHz. Absolute Maximum Rating (AGND = DGND = 0V, all voltages with respect to 0V)
Symbol AVDD DVDD II IO VIA VID VIDGPIO Toper Tstg Ptot Analog Power Supply Digital Power Supply Input Current per Pin Output Current per Pin Analog Input Voltage Digital Input Voltage Digital Input Voltage at GPIO Operating Temperature Storage Temperature Maximum Power Dissipation Parameter Value -0.3, 6.0 -0.3, 6.0 -10, +10 -20, +20 -0.3, 6 -0.3, 6 5.25 0, +70 - 40, +125 200 Unit V V mA mA V V V C mW
75951-02.TBL 75951-04.TBL 75951-03.TBL
C
Warning : Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Dc Characteristics (Tamb = 0 to 70C unless otherwise specified) Power Supply And Common Mode Voltage
Symbol VDD IDVDD IAVDD IDLP IDLP R VCM
Note 1 :
Parameter Supply Voltage Digital Supply Current Analog Supply Current Low Power mode (Hardware control PWRDWN Pin) @ 25C Low Power mode (Software control with wake-up on Ring) @ 25C Common Mode Voltage Output (see note 1)
Min. 2.7
Typ. 3.3 6 9 10 30
Max. 5.25 8 12
Unit V mA mA A A V
100 AVDD/2+5%
AVDD/2-5%
VCM output voltage current must be DC (<10 A) If dynamic load exists, the VCM output must be buffered or the performances of ADCs and DACs will be degraded.
Digital Interface
Symbol VIH VIL VOH VOL ILEAK IXIN High Level Input Voltage Low Level Input Voltage High Level Output Voltage (ILOAD = +2mA) Low Level Output Voltage (ILOAD = -2mA ) Input Leakage Current Input Leakage Current (XTALIN Pin when MCM = 1) -1 -25 Parameter Min. DVDD-0.5 -0.3 DVDD-0.5 0.3 1 25 0.5 Typ. Max. Unit V V V V A A
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ST75951
ELECTRICAL SPECIFICATION (continued) Analog Interface (typical value are given for AVDD = DVDD = 3.3V, Tamb = 25oC. Measurement band = 0 to 0.425 x fS)
Symbol VREF VDIFF IN Parameter Differential reference voltage output VREF = (VREFP - VREFN) Differential Input Voltage [D3 - D4] 2 x VREF -50 2.5 3.2 -50 40 4 10 20 See Note 2 See Note 2 0 to 0.425 * fS, see Notes 2 & 3 f0 0.5 * fS XMIT = 0dB, see Note 1 XMIT = 2dB f = 1kHz, XMIT ATTE = 0dB, see Note 1, Measured over the full 0 to Fs/2 with -20dBr input and extrapoled to full scale -1 f = 1kHz, VAC = 200mVPP, see Note 1 16 -0.9 -0.5 0.2 -70 80 74 85 0.9 0.5 50 XMIT = 0dB XMIT= 2dB Input code = 0000h Test Conditions Min. 1.18 Typ. Max. Unit 1.25 2.5 50 1.32 V VPP mV VPP VPP mV k k k pF Bit Bit dB dB dB dB dB dB
75951-05.TBL
VADO OUT A/D Modulator Output DC Offset Voltage See Figure 26 VDIFF OUT Differential Output Voltage [D1 - D2] VOFF OUT RIN ROUT RL CL Res DNL GTX Ripple StopB SNDR DR Differential Output DC Offset Voltage Input Resistance (D3, D4) Output Resistance (D1, D2) Load Resistance (D1, D2) Load Capacitance (D1, D2) Converter Resolution Differential Non Linearity Channel Gain at f0 + 1kHz Ripple in Band Stop Band Attenuation Signal / Noise + Distortion at - 5dBr Dynamic Range
GRX PSRR
Receive Gain (Rx gain set to 0 dB) Power supply rejection ratio
0 40
+1
dB dB
Notes : 1. These parameters are valid for transmit and receive channels. 2. This specification is guaranteed by characterization, not production testing. 3. Transmit channels measured in baseband without modulation.
Figure 26
ST75951 D3 31 D4 30 VCM
75951-27.EPS
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ST75951
ELECTRICAL SPECIFICATION (continued) Serial Channel Timing (Reference level VIL = 0.8V, VIH = DVDD-0.5V, Vol = 0.4V, VOH = DVDD-0.5V, VBUS = 5V)
Symbol 1 2 3 4 5 6 7 8 9 10 11 12 SCLK Period SCLK Width Low SCLK Width High SCLK Rise Time SCLK Fall Time FS Set-up FS Hold Din set-up Din Hold DOUT Valid HC0, HC1 Set-up FS to SCLK Delay 20 0 50 100 100 50 0 20 Parameter Min. 300 150 150 10 10 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns
75951-06.TBL 75951-28.EPS
ns
Figure 27 : Timing Diagram (R = 4)
MCLK 12 SCLK 6 FS 8 DIN 10 DOUT 11 HC0, 1 MSB MSB 9 7 4 5 3 2 1
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ST75951
TYPICAL APPLICATION
Tip 10W SMTPA 270 22kW 47nF
D4
D5 Q1
ST952
1m F
ST75951
D1 30 D2 31
23 LINI
12V 82W
35 D1 34 D2
MCLK SCLK FS
8 2 3
P R O C E S S O R
D6 Ring
D7
47kW
24 GAIN
Q2 22kW 47nF Q4 47kW
11 OHC 10 COM
D3 D4
1 2
31 D3 30 D4
DIN 46 DOUT 47 RESET 43
Q5 Q3
17 TER1 16 TER2 3
1nF RIN
D5 D6
4 5
27 D5 26 D6 16 GPI
100nF 100nF
PWRDWN 11 HC1
9
DVDD DVDD DVDD
M/S 14 MCM 4 HC0 10
20 LINE 22 IDI
21 VREFP 39 VCM 22 VREFN 32 VCMS
10m F 10m F
TS 44 GPIO0 20 GPIO1 19 GPIO2 18 GPIO3 17 DVDD 5 AVDD 40 22m F 22m F DVDD AVDD 100nF
620W
21 IDG
47kW
9
15m F 100nF
IDC 100nF 10m F
19 VDR 15 VDREF
29 VCMP 41 AUXIN 28 TSTA1 33 TSTA2 45 TSTD1
4.7m F
14 IREF 18 SET 25 LCOM
LIM2 LIM1
7 8
82kW
AOUT 27 1m F AIN 26
39W
100nF
32 LCOM 6
TOFF
18 HM 8 XTALIN 7 XTALOUT
AGND2 38 AGND1 23 DGND 6 100nF
75951-29.EPS
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ST75951
PACKAGE MECHANICAL DATA 48 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
A A2 48 1 e A1 37 36 0,10 mm .004 inch SEATING PLANE
B
12 13 24
25
E3 E1 E
c
D3 D1 D
L1
L
K
Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K
Min. 0.05 1.35 0.17 0.09
Millimeters Typ.
1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00
Max. 1.60 0.15 1.45 0.27 0.20
Min. 0.002 0.053 0.007 0.004
Inches Typ.
0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039
Max. 0.063 0.006 0.057 0.011 0.008
0.45
0.75
0.018
0.030
5B.TBL
0o (Min.), 7o (Max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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PM-5B.EPS
0,25 mm .010 inch GAGE PLANE

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