View IDTCV104B_70556.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
IDTCV104B PRELIMINARY
FEATURES:
* * * * * * * * * * *
4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz CPU frequency VCO frequency up to 1.1G Support index block read/write, single cycle index block read Programmable REF, 3V66, PCI, 48MHz I/O drive strength Programmable 3V66 and PCI Skew Available in SSOP package
IDTCV104B is a 48 pin clock generation device for desktop PC platforms. This chip incorporates four PLLs to allow independent generation of CPU, AGP/ PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, providing high accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread Spectrum selection.
DESCRIPTION:
KEY SPECIFICATION:
* * * *
CPU/SRC CLK cycle to cycle jitter < 125ps SATA CLK cycle to cycle jitter < 125ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error as low as 36ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1 SSC EasyN Programming
CPU CLK Output Buffers
CPU[1:0]
X1
XTAL Osc Amp
IREF REF 3.1.0
X2
PLL2 SSC EasyN Programming SDATA SCLK SM Bus Controller
3V66/PCI Output Buffers PCI[5:0], PCIF[2:0] 3V66[3:0]
PLL3 SSC VTT_PWRGD Watch Dog Timer FS[1:0] Control Logic
SRC CLK Output Buffer
SRC
IREF
48MHz[1:0] SEL24_48# PLL4 48MHz Output Buffer 24 - 48MHz RESET#
OUTPUT TABLE
CPU (Pair) 2 3V66 3 3V66/VCH 1 PCI 6 PCIF 3 REF 3 48MHz 2 24 - 48MHz 1 SRC (Pair) 1 Reset# 1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
(c) 2003 Integrated Device Technology, Inc.
SEPTEMBER 2003
DSC-6382/16
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
*FS1/REF0 *FS0/REF1 VDD_REF
X1 X2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDA Description 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage GND - 0.5 Storage Temperature Ambient Operating Temperature Case Temperature Input ESD Protection Human Body Model
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Min
Max 4.6 4.6 +150 +70 +115
Unit V V C C C V
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
REF3
VDDIN TSTG TAMBIENT TCASE ESD Prot
VDDA VSS IREF VSS CPUT1 CPUC1 VDD_CPU CPUT0 CPUC0 VSS SRCT
SRCC
-65 0 2000
VSS PCIF0 PCIF1 PCIF2 VDD_PCI VSS
PCI0 PCI1 PCI2 PCI3
VDD_SRC *VTT_PWRGD#
*SDATA *SCLK
VDD_PCI VSS
PCI4 PCI5 *RESET#/PD#
HW FREQUENCY SELECTION
FS1.0 00 01 10 11 CPU 100 200 133.33 166.67 AGP 66.66 66.66 66.66 66.66 PCI 33.3 33.3 33.3 33.3 N Resolution 0.223721591 0.447443181 0.298295454 0.397727272
3V66_0 3V66_1 VSS VDD_3V66
3V66_2 3V66_3/VCH
**SEL24/24_48MHz
48MHz1 48MHz0
VSS
VDD48
* = ~ 130K internal pull-up. ** = ~ 130K internal pull-down.
SSOP TOP VIEW
2
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
SW FREQUENCY SELECTION
WDBS[2:0] or BS[2:0] = 000 100 100.9 102.91 104.93 110.07 114.99 119.91 125.06 0.223721591 447 WDBS[2:0] or BS[2:0] = 001 200.01 201.8 204.93 209.85 215.22 220.14 225.06 229.99 0.447443181 447
BS[2:0] and WBS[2:0] are band selects. Whenever there is a band switch, the user has to issue a WD soft alarm (see Byte 32 and Byte 33). In CPU N/M programming, CPU frequency = N * resolution, N from 290 - 600.
CFS[3:0] 000 001 010 011 100 101 110 111 N Resolution Corresponding N WDBS[2:0] or BS = 010 133.34 135.13 138.11 139.9 141.99 144.97 147.95 150.05 0.298295454 447 WDBS[2:0] or BS[2:0] = 011 166.65 167.84 169.83 173.01 175 178.18 180.17 184.94 0.397727272 419 0.447443181 447 0.894886363 447 0.894886363 298 0.795454544 419 WDBS[2:0] or BS[2:0] = 100 200.01 66.67 WDBS[2:0] or BS[2:0] = 101 400.01 401.8 WDBS[2:0] or BS[2:0] = 110 266.66 267.57 WDBS[2:0] or BS[2:0] = 111 333.3 334.89
SPREAD SPECTRUM MAGNITUDE CONTROL (SMC)
SMC[2:0] 000 001 010 011 100 101 110 111 Off - 0.25 - 0.5 - 0.75 -1 0.125 0.25 0.375
3V66-PCI/F SKEW
Skew[2:0] 000 001 010 011 100 101 110 111 normal, 3V66 leads PCI 2.5ns move forward 200ps move forward 400ps move forward 600ps move backward 200ps move backward 400ps move backward 600ps move backward 800ps
AGP/PCI FREQUENCY SELECTION
AFS[2:0] 000 001 010 011 100 101 110 111 AGP 66.67 68.68 70.7 72.71 74.5 76.51 78.53 80.54 PCI 33.33 34.34 35.35 36.35 37.25 38.26 39.26 40.27 Corresponding N 298 307 316 325 333 342 351 360
AGP/PCI STRENGTH
Str[1:0] 0, 0 0, 1 1, 0 1, 1 1.2x 0.7x 0.8x 1x
In AGP/PCI N/M programming, AGP frequency = N * 0.223721591, N from 290 - 600
REF STRENGTH
REF Str[1:0] 0, 0 0, 1 1, 0 1, 1 1x 0.8x 1.2x 0.7x
3
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name FS1/REF0 FS0/REF1 VDD_REF X1 X2 VSS PCIF0 PCIF1 PCIF2 VDD_PCI VSS PCI0 PCI1 PCI2 PCI3 VDD_PCI VSS PCI4 PCI5 RESET#/PD# SEL24/24_48MHZ 48MHz1 48MHz0 VSS VDD48 3V66_3/VCH 3V66_2 VDD_3V66 VSS 3V66_1 3V66_0 SCLK SDATA VTT_PWRGD# VDD_SRC SRCC SRCT VSS CPUC0 CPUT0 Type I/O I/O PWR IN OUT GND I/O OUT OUT PWR GND OUT OUT OUT OUT PWR GND OUT OUT OUT I/O OUT OUT GND PWR OUT OUT PWR GND OUT OUT IN I/O IN PWR OUT OUT GND OUT OUT Description Frequency select latch input 3.3V input HIGH/LOW voltage/ 14.318MHz reference clock output(1) Frequency select latch input 2.5V input HIGH/LOW voltage/ 14.318MHz reference clock output(1) 3.3V Xtal input Xtal output GND Frequency select latch input 3.3V input HIGH/LOW voltage/ PCI free running clock(2) PCI free running clock PCI free running clock 3.3V GND PCI clock PCI clock PCI clock PCI clock 3.3V GND PCI clock PCI clock Reset output signal from watchdog circuit, active LOW/ power down control input. Mode selectable through SM bus, Byte 34 bit 5, power on is RESET# mode.(1) 24MHz or 48MHz clock output. Frequency selected by SEL24 latch input. 1 = 24MHz, 0 = 48MHz, also can be programmed through SM bus Byte 34.(2) 48MHz clock output 48MHz clock output. Output drive strength can be doubled through SM programming. Power on is 2x. GND 3.3V 66MHz or 48MHz clock output. Selectable by SM bus. Power on is 66MHz. 66MHz clock output 3.3V GND 66MHz clock output 66MHz clock output SM bus clock(1) SM bus data(1) Used for power on latch, active HIGH after power on becomes power down control, active LOW.(1) 3.3V SATA 0.7V current mode differential clock output SATA 0.7V current mode differential clock output GND Hosts 0.7V current mode differential clock output Hosts 0.7V current mode differential clock output
NOTES: 1. ~ 130K internal pull-up. 2. ~ 130K internal pull-down.
4
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number 41 42 43 44 45 46 47 48 Name VDD_CPU CPUC1 CPUT1 VSS IREF VSS VDDA REF3 Type PWR OUT OUT GND OUT GND PWR OUT 3.3V Hosts 0.7V current mode differential clock output Hosts 0.7V current mode differential clock output GND Reference current for differential clock output GND 3.3V 14.318 MHz reference clock output Description
5
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
SM BUS PROTOCOL INDEX BLOCK WRITE PROTOCOL
Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Start D2h Acknowledge Register offset byte (starting byte) Acknowledge Byte count N (0 is not a valid byte count)(1) Acknowledge First data byte Acknowledge Second data byte Acknowledge : Nth data byte Stop
NOTE: 1. Bit [21:27] = byte count. Bit 20 = 1, bit [21:27] will be stored into I2C table, Byte 8. SM Bus Byte 8 is read byte count register, power on default is 0FH. Bit 20 = 0, normal SM bus operation.
ONECYCLETM INDEX BLOCK READ
Bit 1 2-9 10 11-18 19 20-27 28 29 30-37 38 39-46 47 48-55 56 57-64 # of bits 1 8 1 8 1 8 1 1 8 1 8 1 8 1 8 From Master Master Slave Master Slave Master Slave Master Master Slave Slave Master Slave Master Slave Slave Master Slave Start D2h Acknowledge Register offset byte (starting byte) Acknowledge 1xxxxxxx. Bit[20] = 1, followed with byte count, which will be stored into I2C table byte 8. Acknowledge Repeated start D3h Acknowledge Byte count, N, I2C table byte 8 value. Power on default is 0FH[15]. Acknowledge Offset data byte, specified by bit[11:18] Acknowledge Offset + 1 data byte : Offset + N-2 Acknowledge Offset + N-1 Not acknowledge Stop Description
Description
INDEX BLOCK READ PROTOCOL
Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 38 39-46 47 48-55 # of bits 1 8 1 8 1 1 8 1 8 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave Master Slave Master Slave Slave Master Slave Start D2h Acknowledge Register offset byte (starting byte) Acknowledge Repeated start D3h Acknowledge Byte count, N, I2C table byte 8 value. Power on default is 0FH[15]. Acknowledge Offset data byte, specified by bit 11-18 Acknowledge Offset + 1 data byte : Offset + N-2 Acknowledge Offset + N-1 Not acknowledge Stop Description
BYTE WRITE METHODS:
* Setting bit[11:18] = starting address, bit [20:27] = 01H.
BYTE READ METHODS (CHOSE ONE):
* Use IDT OneCycle Index Block Read, bit[20:27] = 10000001. Notice that byte count register (byte 8) will be changed to 0IH. * Use Index Block Write protocol to change byte count (byte 8) to 1. After that, use Index Block Read.
TO CHANGE BYTE 8 VALUE:
* Use IDT OneCycle Index Block Read, as above * Use Index Block Write protocol to change byte 8 value.
6
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
BYTE 0: DUMMY BYTE BYTE 1
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Reserve Reserve SS_EN Reserve SRCT, SRCC Reserve CPUT1, CPUC1 CPUT0, CPUC0 Output enable Output enable Tristate Tristate Enable Enable RW RW Output enable Tristate Enable RW Spread spectrum enable On Off RW Description/Function 0 1 Type Power On 0 0 1 0 1 1 1 1
BYTE 2
Bit 7 6 5 4 3 2 1 0 Output(s) Affected SRCT Reserve CPUT1, 0 Reserve 3V66_2 Reserve Reserve Reserve Output enable Tristate Enable RW CPUT Powerdown drive mode Driven in power down Tristate in power down RW Description/Function SRCT Powerdown drive mode 0 Driven in power down 1 Tristate in power down Type RW Power On 0 0 0 0 1 1 1 1
BYTE 3
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Reserve Reserve PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Output enable Output enable Output enable Output enable Output enable Output enable Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW Description/Function 0 1 Type Power On 0 1 1 1 1 1 0 1
7
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
BYTE 4
Bit 7 6 5 4 3 2 1 0 Output(s) Affected 48MHz0 SRCFS0 Reserve 3V66_1 3V66_0 PCIF2 PCIF1 PCIF0 Description/Function Drive strength SRC frequency select Output enable Output enable Output enable Output enable Output enable 0 2 * DRIVE 100MHz Tristate Tristate Tristate Tristate Tristate 1 Normal 200MHz Enable Enable Enable Enable Enable Type RW RW RW RW RW RW RW RW Power On 0 0 1 1 1 1 1 1
BYTE 5
Bit 7 6 5 4 3 2 1 0 Output(s) Affected 3V66_3/VCH Reserve Reserve 3V66_3/VCH Reserve Reserve Reserve Reserve Output enable Tristate Enable RW Description/Function 3V66_3/VCHmode select 0 3V66 mode, 66MHz 1 VCH mode, 48MHz Type RW Power On 0 0 0 1 0 0 0 0
BYTE 6: DUMMY BYTE
BYTE 7
Bit 7 6 5 4 3 2 1 0 Output(s) Affected RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Description/Function 0 1 Type Power On x x x x 0 1 0 1
8
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
BYTE 8 (READ BYTE COUNT REGISTER)
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Reserve BC6 BC5 BC4 BC3 BC2 BC1 BC0 See note 1 Description/Function 0 1 Type Power On 0 0 0 0 1 0 0 1
NOTE: 1. Can be written by index block write or OneCycle block read. See SM BUS PROTOCOL tables.
BYTES 9-20: DUMMY BYTES
BYTE 21
Bit 7 6 5 4 3 2 1 0 Output(s) Affected PCIFStr1 PCIFStr0 Reserve Reserve Reserve Reserve 3V66Str1 3V66Str0 AGP/PCI STRENGTH table AGP/PCI STRENGTH table Description/Function AGP/PCI STRENGTH table AGP/PCI STRENGTH table 0 1 Type Power On 1 1 1 1 1 1 1 1
BYTE 22
Bit 7 6 5 4 3 2 1 0 Output(s) Affected REFStr1 REFStr0 PCIStrC1 PCIStrC0 PCIStrB1 PCIStrB0 PCIStrA1 PCIStrA0 Description/Function REF STRENGTH table REF STRENGTH table PCI[7:5] strength control, AGP/PCI STRENGTH table PCI[7:5] strength control, AGP/PCI STRENGTH table PCI[4:2] strength control, AGP/PCI STRENGTH table PCI[4:2] strength control, AGP/PCI STRENGTH table PCI[1:0] strength control, AGP/PCI STRENGTH table PCI[1:0] strength control, AGP/PCI STRENGTH table 0 1 Type Power On 1 0 1 1 1 1 1 1
9
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
BYTE 23
Bit 7 6 5 4 3 2 1 0 Output(s) Affected 48MHz0 24_48MHz REF1 REF0 Reserve 48MHz1 REF3 Reserve Output enable Output enable Tristate Tristate Enable Enable RW RW Description/Function Output enable Output enable Output enable Output enable 0 Tristate Tristate Tristate Tristate 1 Enable Enable Enable Enable Type RW RW RW RW Power On 1 1 1 1 1 1 1 0
BYTE 24
Bit 7 6 5 4 3 2 1 0 FSR1 FSR0 HW FS1 read back HW FS0 read back R R 0 HW FS1 HW FS0 Output(s) Affected WDHRB WDSRB Description/Function WD hard alarm status read back WD soft alarm status read back 0 1 Type R R Power On
BYTE 25: CPU PLL CONTROL
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CPU frequency band source select BS2, Band select 2 BS1, Band select 1 BS0, Band select 0 CFS2 CFS1 CFS0 CPU N Programming Enable Description/Function 0 = selected by HW latched FS[1:0], CFS[2:0] 1 = selected by BS[2:0], CFS[2:0] BS[2:0] CFS[2:0] select CPU frequency(1) BS[2:0] CFS[2:0] select CPU frequency(1) BS[2:0] CFS[2:0] select CPU frequency BS[2:0] CFS[2:0] select CPU frequency BS[2:0] CFS[2:0] select CPU frequency CPU N Programming Enable
(1)
0 HW
1 SW
Type RW RW RW RW RW RW RW
Power On 0 0 0 0 0 0 0 0
BS[2:0] CFS[2:0] select CPU frequency(1)
(1) (1)
Disable
Enable
RW
NOTES: 1. See SW FREQUENCY SELECTION table.
10
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
BYTE 26: CPU PLL CONTROL
Bit 7 6 5 4 3 2 1 0 Output(s) Affected WDBS2 WDBS1 WDBS0 CSMC2 CSMC1 CSMC0 CPN9 CPN8 Description/Function At the event of WD hard alarm time out, If Byte 32 bit 7 = 1, CPU frequency is selected by WDBS[2:0] WDCFS[2:0](1) CPU SMC2, SMC table CPU SMC1, SMC table CPU SMC0, SMC table CPU PLL N9 CPU PLL N8 0 1 Type RW RW RW RW RW RW RW RW Power On 1 0 0 0 1 0
NOTE: 1. See SW FREQUENCY SELECTION table.
BYTE 27: CPU PLL N PROGRAMMING
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CPN7 CPN6 CPN5 CPN4 CPN3 CPN2 CPN1 CPN0
In CPU N programming mode, CPU frequency = CPN[9:0] * band resolution. CPN[9:0] range is 290 - 600. CPN0 has to be written for the CPN[9:0] to be loaded into PLL N driver. See SW FREQUENCY SELECTION table.
Description/Function CPU PLL N7 CPU PLL N6 CPU PLL N5 CPU PLL N4 CPU PLL N3 CPU PLL N2 CPU PLL N1 CPU PLL N0 0 1 Type RW RW RW RW RW RW RW RW Power On
BYTE 28: AGP/PCI PLL CONTROL
Bit 7 6 5 4 3 2 1 0 Output(s) Affected AFS2 AFS1 AFS0 WDAFS2 WDAFS1 WDAFSO APN9 APN8 Description/Function See AGP/PCI FREQUENCY SELECTION table See AGP/PCI FREQUENCY SELECTION table See AGP/PCI FREQUENCY SELECTION table AGP/PCI WD hard alarm time out frequency selection AGP/PCI WD hard alarm time out frequency selection AGP/PCI WD hard alarm time out frequency selection AGP/PCI PLL N9 AGP/PCI PLL N8 0 1 Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0
11
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
BYTE 29: AGP/PCI N PROGRAMMING
Bit 7 6 5 4 3 2 1 0 Output(s) Affected APN7 APN6 APN5 APN4 APN3 APN2 APN1 APN0
In AGP/PCI N programming mode, AGP/PCI frequency = APN[9:0] * 0.223721591. APN[9:0] range is 290 - 600. APN0 has to be written for the APN[9:0] to be loaded into PLL N divider.
Description/Function AGP/PCI PLL N7 AGP/PCI PLL N6 AGP/PCI PLL N5 AGP/PCI PLL N4 AGP/PCI PLL N3 AGP/PCI PLL N2 AGP/PCI PLL N1 AGP/PCI PLL N0 0 1 Type RW RW RW RW RW RW RW RW Power On
BYTE 30: AGP/PCI SRC CONTROL
Bit 7 6 5 4 3 2 1 0 Output(s) Affected AGP/PCI N Programming Mode Enable AGP/PCI Frequency Source Select AGP SMC 2 AGP SMC 1 AGP SMC 0 3V66-PCI/F skew 2 3V66-PCI/F skew 1 3V66-PCI/F skew 0 Description/Function AGP/PCI N Programming Enable 0 = fixed 66/33MHz 1 = selected by AFS[2:0](1) AGP/PCI SSC magnitude control(2) AGP/PCI SSC magnitude control(2) AGP/PCI SSC magnitude control Adjust 3V66 and PCI/F skew Adjust 3V66 and PCI/F skew
(3) (2)
0 Disable 66/33MHz
1 Enable
Type RW RW RW RW RW RW RW RW
Power On 0 0 0 1 0 0 0 0
Adjust 3V66 and PCI/F skew(3)
(3)
NOTES: 1. See AGP/PCI FREQUENCY SELECTION table. 2. See SMC table. 3. See 3V66 AND PCI/F SKEW table.
BYTE 31: WATCHDOG TIMER
Bit 7 6 5 4 3 2 1 0 Output(s) Affected WD Hard Alarm timer 7 WD Hard Alarm timer 6 WD Hard Alarm timer 5 WD Hard Alarm timer 4 WD Hard Alarm timer 3 WD Hard Alarm timer 2 WD Hard Alarm timer 1 WD Hard Alarm timer 0 Description/Function Specify WD Hard Alarm time out waiting time. Time Out time = WD Hard Alarm timer[7:0] * 290ms Default is 11*290 = 3.2s 0 1 Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 1 0 1 1
12
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
BYTE 32: WD SOFT RESET TIMER
Bit 7 Output(s) Affected CPU WD Hard Alarm safe frequency mode select WDCFS2 WDCFS1 WDCFS0 WD soft alarm timer 3 WD soft alarm timer 2 WD soft alarm timer 1 WD soft alarm timer 0
WD Soft Alarm timer has to be shorter than WD Hard Alarm timer. WDE and WD Soft Alarm bits, Byte 33 bit 7 and bit 5, have to be enabled for this Soft Alarm function.
Description/Function 0 = frequency select controlled by Byte 25 bit 7 1 = CPU frequency specified by WDBS[2:0] WDCFS[2:0] CPU WD time out safe frequency select(1) 0 HW/I2C 1 WDBS WDCFS Type RW Power On 0
6 5 4 3 2 1 0
RW RW RW
0 0 0 0 0 1 0
Specify WD Soft Alarm Time Out time Time Out time = WD Soft Alarm Timer[3:0]*290ms Default is 580ms.
RW RW RW RW
NOTE: 1. See SW FREQUENCY SELECTION table.
BYTE 33: WD CONTROL
Bit 7 6 5 4 Output(s) Affected WDE WD FS relatch WD Soft Alarm enable AGP/PCI WD Hard Alarm Description/Function Watchdog enable Relatch HW FS2, 1, 0 in event of WD Hard Alarm time out WD Soft Alarm enable In event of WD Hard Alarm time out 1 = AGP/PCI frequency specified by WDAFS[2:0] 3 2 1 0
NOTE: 1. See SMC table.
0 Disable Disable Disable HW/I2C
1 Enable Enable Enable WDAFS
Type RW RW RW RW
Power On 0 0 0 0
time out safe frequency mode select 0 = AGP/PCI frequency controlled by Byte 30 bit 6 SRC SMC 2 SRC SMC 1 SRC SMC 0 Reserve SRC SSC magnitude control(1) SRC SSC magnitude control
(1)
1 0 1 0
SRC SSC magnitude control(1)
BYTE 34
Bit 7 6 5 4 3 2 1 0 Output(s) Affected SW 24_48MHz control override 24_48MHz select Reset#/PD# Reset#/PD# mode select Description/Function 0 1 bit 6 48MHz Reset# 24MHz PD# RW RW 0 0 0 0 Type RW Power On 0 0 = controlled by hardware, 1 = controlled by bit 6 HW control controlled by
13
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
CPU AND AGP CLOCK FREQUENCY SELECTION
Band switch will take effect only when WD Soft Alarm time out is issued, which means there is a RESET issued. Even if the user changed BS[2:0], if there is no WD Soft Alarm, CPU PLL still uses the old band. CPN[9:0] and APN[9:0] will be loaded into PLL only when CPN0 and APN0 are written respectively.
CPU FREQUENCY
Byte 25 bit 0, bit 7 00 01 10 11 CPU Frequency Selected by: HW FS[1:0] BS[2:0], CFS[2:0], Byte 25 CPN[9:0] * Band Resolution CPN[9:0] * Band Resolution
AGP/PCI FREQUENCY
Byte 30 bit 7, bit 6 00 01 10 11 AGP/PCI Frequency Selected by: 66/33 AFS[2:0], Byte 28 APN[9:0] * 0.223721591 APN[9:0] * 0.223721591
WD SOFT AND HARD ALARM/TIME OUT OPERATION
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE Trigger Watch Dog Circuit
WD SOFT ALARM TIME OUT If WD Soft Alarm Enabled: Set WDSRB Issue RESET# Switch CPU PLL band
WD HARD ALARM TIME OUT Set WDHRB Issue RESET# Change CPU Frequency (see Byte 32, bit 7) Change AGP/PCI Frequency (see Byte 33, bit 4) If WD FS Relatch enabled, relatch HW FS2, FS1, FS0 Reset Byte 30 bit 7, and Byte 25 bit 0, to 0
User only uses WD Soft Alarm when there is a band switch. It can be from HW to SW select, or in the SW select with band change. Soft Alarm Timer has to be shorter than Hard Alarm Timer. At the event of WD Hard Alarm time out, CPU Safe return frequency is decided by two bits: Byte 32 bit 7 and Byte 25 bit 7. AGP/PCI Safe Return Frequency is decided by Byte 33 bit 4 and Byte 30 bit 6. Byte 30 bit 7, and Byte 25 bit 0, will be reset to 0.
Byte 32 bit 7, Byte 25 bit 7 00 01 10 11 Latched HW FS[1:0] BS[2:0], CFS[2:0], Byte 25 WDBS[2:0], WDCFS[2:0], Byte 26 and Byte 32 WDBS[2:0], WDCFS[2:0], Byte 26 and Byte 32 CPU WD Hard Alarm Time Out Frequency Select: Byte 33 bit 4, Byte 30 bit 6 00 01 10 11 66/33MHz AFS[2:0], Byte 28 WDAFS, Byte 28 WDAFS, Byte 28 AGP/PCI Hard Alarm Time Out Frequency Select:
14
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%
Symbol VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD FI LPIN CIN COUT CINX TSTAB Clock Stabilization(3,4) Modulation Frequency(3) TDRIVE_SRC(3) TDRIVE_PD#(3) TFALL_PD#(3) TRISE_PD#(4) TDRIVE_CPU_Stop#(3) TFALL_CPU_Stop#(3) TRISE_CPU_Stop#(4) Input Capacitance(3) Parameter 3.3V Input HIGH Voltage 3.3V Input LOW Voltage Input HIGH Current Input LOW Current Input LOW Current Operating Supply Current Powerdown Current Input Frequency(2) Pin Inductance(3) Logic inputs Output pin capacitance X1 and X2 pins From VDD power-up or de-assertion of PD# to first clock Triangular modulation SRC output enable after PCI_Stop# de-assertion CPU output enable after PD# de-assertion Fall time of PD# Rise time of PD# CPU output enable after CPU_Stop# de-assertion Fall time of PD# Rise time of PD# 3.3V 5% 3.3V 5% VIN = VDD VIN = 0V, inputs with no pull-up resistors VIN = 0V, inputs with pull-up resistors Full active, CL = full load All differential pairs driven All differential pairs tri-stated VDD = 3.3V Test Conditions Min. 2 VSS - 0.3 -5 -5 -200 -- -- -- -- -- -- -- -- -- 30 -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- 14.31818 -- -- -- -- -- -- -- -- -- -- -- -- -- Max. VDD + 0.3 0.8 5 -- -- 400 70 12 -- 7 5 6 5 1.8 33 15 300 5 5 10 5 5 ms KHz ns us ns ns us ns ns pF MHz nH Unit V V A A A mA mA
NOTES: 1. Available to CV104A, CV105A, CV107A, and CV109A. 2. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 3. This parameter is guaranteed by design, but not 100% production tested. 4. See TIMING DIAGRAMS for timing requirements.
15
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - CPU AND SRC 0.7 CURRENT MODE DIFFERENTIAL PAIR(1)
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 2pF
Symbol ZO VOVS VUDS VHIGH VLOW VOVS VUDS VCROSS(ABS) d - VCROSS ppm Parameter Current Source Output Impedance(2) Maximum Voltage (Overshoot) Minimum Voltage (Undershoot) Voltage HIGH(2) Voltage LOW(2) Max Voltage(2) Min Voltage(2) Crossing Voltage (abs)(2) Crossing Voltage (var)(2) Long Accuracy(2,3)
Variation of crossing over all edges
Test Conditions VO = VX
Min. 3000 -- -0.3
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. -- VH + 0.3 -- 850 150 1150 -- 550 140 300 2.5008 3.0009 3.7511 5.0015 6.0018 7.5023 10.003 2.5008 3.0009 3.7511 5.0266 6.032 7.54 10.0533 700 700 125 125 55 100 85
Unit V V mV mV mV mV ppm
Statistical measurement on single-ended signal using oscilloscope math function Measurement on single-ended signal using absolute value
660 -150 -- -300 250 -- -300 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 175 175 -- --
See TPERIOD Min. - Max. values 400MHz nominal, no Intel spec 333.33MHz nominal, no Intel spec 266.66MHz nominal, no Intel spec
TPERIOD
Average Period(3)
200MHz nominal 166.66MHz nominal 133.33MHz nominal 100MHz nominal 400MHz spread, no Intel spec 333.33MHz spread, no Intel spec 266.66MHz spread, no Intel spec
ns
TPERIOD
Average Period(3)
200MHz spread 166.66MHz spread 133.33MHz spread 100MHz spread
ns
tR tF d-tR d-tF dT3 tSK3 tJCYC-CYC
Rise Time(2) Fall Time(2) Rise Time Variation(2) Fall Time Variation(2) Duty Cycle(2)
VOL = 0.175V, VOH = 0.525V VOL = 0.175V, VOH = 0.525V
ps ps ps ps % ps ps
Measurement from differential waveform VT = 50% Measurement from differential waveform
45 -- --
Skew(2) Jitter, Cycle to Cycle(2)
NOTES: 1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
16
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - 3V66
Symbol ppm VOH VOL TPERIOD IOH IOL Parameter Long Accuracy(1,2) Output HIGH Voltage Output LOW Voltage Clock Period(2) Output HIGH Current Output LOW Current Edge Rate(1) tR1 tF1 tSK1 dT1 tJCYC-CYC Rise Time(1) Fall Time(1) Skew(1) Duty Cycle(1) Jitter(1) Test Conditions
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 30pF
Min. -300 2.4 -- 14.9955 14.9955 -33 -- 30 -- 1 0.5 0.5 -- 45 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 300 -- 0.55 15.0045 15.0799 -- -33 -- 38 4 2 2 250 55 250 V/ns ns ns ps % ps mA mA Unit ppm V V ns See Tperiod Min. - Max. values IOH = -1mA IOL = 1mA 66MHz output nominal 66MHz output spread VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising/Falling edge rate VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V VT = 1.5V VT = 1.5V, 3V66
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 30pF
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Long Accuracy(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tSK1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Skew(1) Jitter(1) Test Conditions See Tperiod Min. - Max. values 33.33MHz output nominal 33.33MHz output spread IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V VT = 1.5V VT = 1.5V Min. -- 29.991 29.991 2.4 -- -33 -- 30 -- 1 1 0.5 0.5 45 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 300 30.009 30.1598 -- 0.55 -- -33 -- 38 4 4 2 2 55 500 250 V/ns V/ns ns ns % ps ps mA V V mA Unit ppm ns
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
17
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Long Accuracy(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Jitter(1) Test Conditions See Tperiod Min. - Max. values 48MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V
ELECTRICAL CHARACTERISTICS, 48MHZ, USB AND VCH
Min. -- 20.8271 2.4 -- -33 -- 30 -- 1 1 1 1 45 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 300 20.8396 -- 0.55 -- -33 -- 38 2 2 2 2 55 350 V/ns V/ns ns ns % ps mA Unit ppm ns V V mA
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS, DOT 48MHZ
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Long Accuracy(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Jitter(1) Test Conditions See Tperiod Min. - Max. values 48MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Min. -- 20.8271 2.4 -- -33 -- 30 -- 2 2 0.5 0.5 45 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 300 20.8396 -- 0.55 -- -33 -- 38 4 4 1 1 55 350 V/ns V/ns ns ns % ps mA Unit ppm ns V V mA
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
18
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
PD#, POWER DOWN
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start without glitches.
PWRDWN# 1 0
CPU Normal IREF * 2 or float
CPU# Normal Float
SRC Normal IREF * 2 or float
SRC# Normal Float
PCIF/PCI 33MHz Low
USB 48MHz Low
3V66 66MHz Low
REF 14.318MHz Low
PD# should be sampled low by two consecutive CPU# rising edges before stopping clocks. All single-ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to `tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of interest is set to `0' the true clock will be driven high at 2 x IREF and the complementary clock will be tristated. If the control register is programmed to `1' both clocks will be tristated.
PD# ASSERTION
PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
19
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
PD# DE-ASSERTION
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate is programmed to `1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300s of PD# deassertion.
tSTABLE <1.8mS PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818 tDRIVE_PWRDWN# <300S, <200mV
20
IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX XXX CV Device Type Temp. Range XX Package X Grade Blank Commercial Temperature Range
PV
Small Shrink Outline Package
104B
Clock Generator for Desktop PC Platforms 0C to +70C
74
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
21

▲Up To Search▲

Price & Availability of IDTCV104B

	To Download IDTCV104B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .