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CMOS STATIC RAM 1 MEG (256K x 4-BIT)
Integrated Device Technology, Inc.
IDT71028S70
FEATURES:
* 256K x 4 CMOS static RAM * Equal access and cycle times -- Commercial: 70ns * One Chip Select plus one Output Enable pin * Bidirectional data Inputs and outputs directly TTL-compatible * Low power consumption via chip deselect * Available in 400 mil Plastic SOJ package
DESCRIPTION:
The IDT71028 is a 1,024,576-bit medium-speed static RAM organized as 256K x 4. It is fabricated using IDT's highperfomance, high-reliability CMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for your memory needs. The IDT71028 has an output enable pin which operates as fast as 30ns, with address access times as fast as 70ns. All bidirectional inputs and outputs of the IDT71028 are TTLcompatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71028 is packaged in 28-pin 400 mil Plastic SOJ package.
FUNCTIONAL BLOCK DIAGRAM
A0
ADDRESS DECODER
1,048,576-BIT MEMORY ARRAY
A17
I/O0 - I/O3
4
4
I/O CONTROL
CS WE OE
CONTROL LOGIC
3569 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
MAY 1996
3569/-
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IDT71028S70 CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
CS OE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. -0.5 to +7.0 Unit V
VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0
WE
VTERM
(2)
GND
1 28 27 2 3 26 25 4 5 24 23 6 SO28-6 7 22 21 8 20 9 10 19 11 18 17 12 16 13 15 14
TA TBIAS TSTG PT IOUT
0 to +70 -55 to +125 -55 to +125 1.25 50
C C C W mA
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SOJ TOP VIEW
NOTES: 3569 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
TRUTH TABLE(1,2)
CS OE WE
CAPACITANCE
I/O Function Read Data Write Data Output Disabled Deselected - Standby (ISB) Deselected - Standby (ISB1)
3569 tbl 01
(TA = +25C, f = 1.0MHz, SOJ package)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 8 8 Unit pF pF
L L L H VHC(3)
L X H X X
H L H X X
DATAOUT DATAIN High-Z High-Z High-Z
NOTE: 3569 tbl 03 1. This parameter is guaranteed by device characterization, but not production tested.
NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC.
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0 -- --
Max. 5.5 0 VCC+0.5 0.8
Unit V V V V
NOTE: 3569 tbl 04 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V 10%
IDT71028 Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min. -- -- -- 2.4 Max. 5 5 0.4 -- Unit A A V V
3569 tbl 05
2
IDT71028S70 CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71028S70 Symbol ICC Parameter Dynamic Operating Current, CS2 VIH and CS2 VIH and CS1 VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS1 VIH or CS2 VIL, Outputs Open, VCC = Max., f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS1 VHC, or CS2 VLC Outputs Open, VCC = Max., f = 0(2), VIN VLC or VIN VHC Com'l. Mil. 140 -- Unit mA
ISB
35
--
mA
ISB1
10
--
mA
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
3569 tbl 06
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
3569 tbl 07
5V
5V
480
480 DATAOUT 30pF 255
3569 drw 03
DATAOUT 5pF* 255
3569 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
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IDT71028S70 CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, Commercial Temperature Range)
Symbol Parameter 71028S70 Min. Max. Unit
Read Cycle tRC tAA tACS tCLZ
(2) (2)
Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid
(2) (2)
70 -- -- 3 0 -- 0 0 4 0 --
-- 70 70 -- 30 30 -- 30 -- -- 70
ns ns ns ns ns ns ns ns ns ns ns
tCHZ tOE tOLZ
Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time
tOHZ tOH tPU tPD
(2) (2)
Write Cycle tWC tAW tCW tAS tWP tWR tDW tDH tOW
(2) (2)
Write Cycle Time Address Valid to End-of-Write Chip Select to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Output Active from End-of-Write Write Enable to Output in High-Z
70 60 60 0 45 0 30 0 5 0
-- -- -- -- -- -- -- -- -- 30
ns ns ns ns ns ns ns ns ns ns
3569 tbl 08
tWHZ
NOTES: 1. 0C to +70C temperature range only. 2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
4
IDT71028S70 CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA
OE
tOE
CS
tOLZ (5) tACS tCLZ
(5) (3)
tCHZ
(5)
tOHZ (5)
DATAOUT
HIGH IMPEDANCE
DATAOUT VALID tPD
VCC SUPPLY ICC CURRENT ISB
tPU
3569 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
3569 drw 6
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
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IDT71028S70 CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,5) WE
tWC ADDRESS tAW
CS
tAS
WE
tWP(3)
tWR
tWHZ DATAOUT
(4)
(6)
tOW HIGH IMPEDANCE tDW tDH
(6)
tCHZ
(4)
(6)
DATAIN
DATAIN VALID
3569 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,5) CS
tWC ADDRESS tAW
CS
tAS
WE
tCW
tWR
tDW DATAIN DATAIN VALID
tDH
3569 drw 08
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state.
6
IDT71028S70 CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT 71028 Device Type S Power XX Speed XX Package X Process/ Temperature Range Blank Commercial (0C to +70C)
Y
400-mil Small Outline J-Bend (SO28-6)
70
Speed in nanoseconds
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