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74ACT843 9-Bit Transparent Latch
July 1988 Revised September 2000
74ACT843 9-Bit Transparent Latch
General Description
The ACT843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths.
Features
s TTL compatible inputs s 3-STATE outputs for bus interfacing
Ordering Code:
Order Number 74ACT843SC 74ACT843SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names D0-D8 O0-O8 OE LE CLR PRE Description Data Inputs Data Outputs Output Enable Latch Enable Clear Preset
FACT is a trademark of Fairchild Semiconductor Corporation
(c) 2000 Fairchild Semiconductor Corporation
DS009800
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74ACT843
Functional Description
The ACT843 consists of nine D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to the LE and OE pins, the ACT843 has a Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR.
Function Tables
Inputs CLR H H H H H H H L L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change
Internal LE H H L H H L X X X L L D L H X L H X X X X X X Q L H NC L H NC H L H L H
Outputs Function O Z Z Z L H NC H L H Z Z High Z High Z Latched Transparent Transparent Latched Preset Clear Preset Clear/High Z Preset/High Z
PRE H H H H H H L H L H L
OE H H H L L L L L L H H
Logic Diagram
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74ACT843
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC +0.5V -20 mA +20 mA -0.5V to VCC +0.5V 50 mA 50 mA -65C to +150C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC
-40C to +85C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 8.0 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 0.5 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 5.0 1.5 75 -75 80.0 A A mA mA mA A V V V V VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 A VIN = VIL or VIH V IO = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Units Conditions
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
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74ACT843
AC Electrical Characteristics
VCC Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPHL tPLH Parameter Propagation Delay Dn to On Propagation Delay Dn to On Propagation Delay LE to On Propagation Delay LE to On Propagation Delay PRE to On Propagation Delay CLR to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On Propagation Delay PRE to On Propagation Delay CLR to On
Note 4: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Typ 5.5 5.5 5.5 5.5 6.5 7.5 5.5 5.5 6.0 6.0 6.0 5.5 Max 9.5 9.5 9.0 9.0 14.0 15.5 9.5 9.5 10.5 10.5 10.5 9.5
TA = -40C to +85C CL = 50 pF Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Max 10.0 10.0 10.0 10.0 16.0 17.5 10.5 10.5 11.0 11.0 11.0 10.5 ns ns ns ns ns ns ns ns ns ns ns ns Units
(V) (Note 4) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
AC Operating Requirements
VCC Symbol Parameter (V) (Note 5) tS tH tW tW tW trec trec Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH PRE Pulse Width, LOW CLR Pulse Width, LOW PRE Recovery Time CLR Recovery Time 5.0 5.0 5.0 5.0 5.0 5.0 5.0 TA = +25C CL = 50 pF Typ -0.5 0.5 2.0 5.0 5.5 0.5 -0.5 0.5 2.0 3.5 8.5 9.5 2.0 1.0 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 1.0 2.0 3.5 10.0 11.0 2.0 1.0 ns ns ns ns ns ns ns Units
Note 5: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 44 Units pF pF Conditions VCC = OPEN VCC = 5.0V
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74ACT843
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
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74ACT843 9-Bit Transparent Latch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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