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INTEGRATED CIRCUITS
DATA SHEET
UAA1570HL Global Positioning System (GPS) front-end receiver circuit
Product specification File under Integrated Circuits, IC18 1999 May 10
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.10 7.10.1 7.10.2 7.10.3 7.10.4 7.10.5 7.10.6 7.11 7.12 7.13 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING INFORMATION FUNCTIONAL DESCRIPTION Low noise amplifiers LNA1 and LNA2 LNA1IN LNA1OUT LNA2IN LNA2OUT MX1IN General remarks and results Correlation of the UAA1570HL data sheet, application and test boards RF mixer with preamplifier VCO First IF filter Second IF mixer Second IF filter Time and amplitude quantization Clock inputs CMOS to ECL sample clock squaring circuit Time quantization (sampler) TTL output stage 1-bit delays Programmable synthesizer VCO prescaler Main synthesizer dividers (N-path) Second local oscillator dividers (L-path) Reference dividers (R-path) Serial interface p0 and p1 r5 r0, r1, r2, r3 and r4 n7 n0, n1, n2, n3, n4, n5 and n6 l0, l1, l2 and l3 The serial interface word The default frequency plan Phase detector, charge pump and loop filter 8 8.1 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19
UAA1570HL
OPERATING MODE SELECTION TABLES Manual selection operating modes LIMITING VALUES THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS CHARACTERIZATION TEST CIRCUIT DEFAULT APPLICATION AND DEMONSTRATION BOARD INTERNAL CIRCUITRY PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
1 FEATURES 2 GENERAL DESCRIPTION
UAA1570HL
* Complete single-chip programmable double-superheterodyne C/A-code GPS receiver * Programmable high IF frequencies supporting wideband/P-code GPS and Global Navigation Satellite System (GLONASS) applications * Supports frequency plans with a 2nd IF of 4 x f0(1.023 MHz) = 4.092 MHz * 48-pin LQFP package * -40 to +85 C operating temperature range * 2.7 V minimum supply voltage * Low DC power consumption [57 mA typical with both Low-Noise Amplifiers (LNAs) active] * Power-down mode (<900 A) * Typical receiver noise figure at 1.57542 GHz: 4.5 dB * Typical phase noise -72 dBc/Hz at 10 kHz offset * Simple microstrip LNA1/2 and first mixer matching * Single pin VCO with external varactor and resonator * Digital Phase Locked Loop (DPLL) synthesizer with programmable VCO, 2nd Local Oscillator (LO) and reference dividers * 3-bit synthesizer and power-down control input * Reference and independent sample clock input with internal squaring * 1-bit amplitude quantized and time sampled TTL/CMOS compatible output driver * High active gain supporting SAW filter applications * Configurable for external first LNA applications. 3 ORDERING INFORMATION TYPE NUMBER UAA1570HL
The UAA1570HL is a complete single-chip double-superheterodyne receiver front-end intended for GPS and GLONASS navigation systems. The IC includes a programmable on-chip DPLL synthesizer, VCO with external varactor and resonator, a 1-bit amplitude quantizer and a time sampled TTL/CMOS compatible SIGN output bit driver. It can be used with either an active or passive antenna system by disabling or enabling the on-chip LNAs and is ideally suited for low power GPS receiver applications because of its 3 V supply and the power management features through control pins. Programmable prescaler controls provide the flexibility of using different frequency schemes. The UAA1570HL is optimized to provide SIGN bit data to the companion Philips part, the SAA1575HL baseband digital signal processor. The SAA1575HL can provide the sample clock input to the UAA1570HL by dividing a TTL/CMOS level reference clock signal down to a programmable sampling clock output frequency. Both ICs can also be used independently. The UAA1570HL is supplied in a low profile, 48-pin LQFP package for excellent Radio Frequency (RF) performance and small size.
PACKAGE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm VERSION SOT313-2
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
4 QUICK REFERENCE DATA VCCA = VDDD = 3 V; Tamb = 25 2 C; unless otherwise specified. SYMBOL VCCA VDDD PARAMETER analog supply voltage digital supply voltage VCCA and VDDD = 2.7 V VCCA and VDDD = 5 V LNAs at 1.57542 GHz MX1 at 1.57542 GHz MX2 at 41.8 MHz limiter at 3.48 MHz f = 3.48 MHz f = 1.57542 GHz VCCA and VDDD = 3.3 to 5 V VCCA and VDDD = 3 to 5 V VCCA and VDDD = 2.7 to 5 V CONDITIONS MIN. 2.7 2.7 - - - - - - - - -40 -30 0
UAA1570HL
TYP. 3 3 55.1 61 31 17.7 21.4 78 100 4.5 +25 +25 +25
MAX. 5 5 62.3 69.3 - - - - - 5.2 +85 +85 +85
UNIT V V mA mA dB dB dB dBV V dB C C C
IVCCA + IVDDD analog supply current plus digital supply current GRF GIF1 GIF2 Gv(lim) Vlim(M) FRX Tamb available RF power gain available 1st mixer power gain available 2nd mixer power gain limiter voltage gain to 1st latch differential limiter sensitivity (peak value) receiver noise figure operating ambient temperature
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
5 BLOCK DIAGRAM
UAA1570HL
LNA1GND2
LNA1GND1
BIASGND1
handbook, full pagewidth
VCCA(LNA1)
LNA1OUT
P42GND
P41GND
P39GND
PLLGND
LNA1IN
COMP
48
47
46
45
44
43
42
41
40 PHASE FREQUENCY DETECTOR
39
38
LNA1 VCCA(LNA2) LNA2GND1 LNA2IN BIASGND2 LNA2GND2 LNA2OUT CLOCK 1 2 3 4 5 6 7 DIVIDE-BY-1 or 2 LNA2
SQUARING CIRCUIT 36
SCLK 37
UAA1570HL
DIVIDE-BY-1 or 2
35 33
VCCA(PLL) DGND VDDD VCCA(LIM)
DIVIDE-BY-2 DIVIDE-BY-N(1) (64 to 127) DATA REGISTER FOR PROGRAMMING
31
32
DATA
to data register SQUARING CIRCUIT
REFIN
8
DIVIDE-BY-R(1) (4 to 31)
DIVIDE-BY-3
34 30 29
SIGN BFCP LIMINP LIMINN BFCN LIMGND
VCCA(VCO) TANK VCOGND P12GND
9 10 11 12 DIVIDE-BY-L(1) (4 to 15) to data register 17 IF1P 18 IF1N 23 STROBE 19 VCCA(MX2) DIVIDE-BY-2 VCO DIVIDE-BY-2 QUANTIZER
28 27 26
MIXER 1 13 MXPGND 14 MX1IN 15 MX1GND 16 VCCA(MX1P)
MIXER 2 20 MX2GND 21 IF2INN 22 IF2INP 24
25
IF2N
MHB269
Shaded blocks are NOT active during synthesizer state. (1) The default values are: L = 10, N = 71 and R = 4.
Fig.1 Block diagram.
1999 May 10
5
IF2P
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
6 PINNING INFORMATION PIN VOLTAGE TYPICAL VALUES (V) VCC = 2.7 V VCCA(LNA2) LNA2GND1 LNA2IN BIASGND2 LNA2GND2 LNA2OUT CLOCK 1 2 3 4 5 6 7 2.7 0 0.815 0 0 1.48 CMOS level 5 0 0.807 0 0 3.629 CMOS level VCC = 5 V
UAA1570HL
SYMBOL
PIN
DESCRIPTION LNA2 power supply: DC operation range 2.7 to 5 V; use close proximity RF decoupling to pins 2, 4 and 5 LNA2 ground 1: minimize RF ground inductance LNA2 input: use external RF AC coupling LNA2 bias circuit ground: minimize RF ground inductance LNA2 ground 2: minimize RF ground inductance LNA2 output: use external RF AC coupling. The DC voltage is approximately 1.3 V below the VCCA(LNA2) supply on pin 1. Serial interface clock input: this DC coupled CMOS CLOCK input moves 20-bit programming words into the synthesizer DATA input register while the STROBE is LOW. A DC short-circuit to ground is recommended with the default frequency plan. Reference input: use external AC coupling. The DC voltage is approximately 1 V below the VCCA(PLL) supply on pin 36. VCO power supply: DC operation range 2.7 to 5 V; use critical close proximity RF decoupling to pin 11 VCO negative impedance resonator port: use the absolute minimum trace lengths and widths and keep the loop to the VCO ground pin 11 as short as possible, while centring the COMP output voltage at pin 40 within the charge pump output voltage range given in Chapter 11 by adjusting the resonator inductance and/or required AC coupling component. VCO ground: minimize RF ground inductance; use critical close proximity RF decoupling to VCO supply pin 9 this pin provides additional RF shielding and has to be connected to ground RF mixer preamplifier ground: minimize RF ground inductance RF mixer preamplifier input: use external AC coupling and RF matching RF mixer ground: minimize RF ground inductance; use critical close proximity RF decoupling to VCCA(MX1P) supply pin 16 RF preamplifier/mixer power supply: DC operation range 2.7 to 5 V; use critical close proximity RF decoupling to pin 15 RF mixer IF positive output: DC couple this output pin to the VCCA(MX1P) supply through first IF filter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced first mixer IF1 outputs are recommended. Prevent externally squared reference harmonics from entering the first IF signal path or components.
REFIN VCCA(VCO) TANK
8 9 10
1.69 2.7 1.92
3.99 5 1.92
VCOGND P12GND MXPGND MX1IN MX1GND VCCA(MX1P) IF1P
11 12 13 14 15 16 17
0 0 0 0.82 0 2.7 2.7
0 0 0 0.81 0 5 5
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
PIN VOLTAGE TYPICAL VALUES (V) VCC = 2.7 V IF1N 18 2.7 5 VCC = 5 V
UAA1570HL
SYMBOL
PIN
DESCRIPTION RF mixer IF negative output: DC couple this output pin to the VCCA(MX1P) supply through first IF filter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced first mixer IF1 outputs are recommended. Prevent externally squared reference harmonics from entering the first IF signal path or components. IF mixer power supply: if present, decouple the common VCC line sourcing the first and second mixer by placing a large decoupling capacitor between the two IF mixer ground: minimize IF ground inductance; use close proximity IF decoupling to the VCCA(MX2) supply pin 19 IF mixer negative input: use external AC coupling. Balanced IF1 second mixer inputs are recommended. Prevent externally squared reference harmonics from entering the first IF signal path or components. IF mixer positive input: use external AC coupling. Balanced IF1 second mixer inputs are recommended. Prevent externally squared reference harmonics from entering the first IF signal path or components. Serial interface strobe input: a LOW level on this DC-coupled CMOS STROBE input enables the CLOCK input to load the 20-bit programming word into the synthesizer input DATA register. A mandatory DC short-circuit to ground is required to ensure that the default frequency plan is invoked on power-up. IF mixer second IF positive output: DC couple this output pin to the VCCA(MX2) supply through second IF filter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced second mixer IF2 outputs are optional for many applications. Short the unused IF2P or IF2N output directly to the supply in single-ended applications. IF mixer second IF negative output: DC couple this output pin to the VCCA(MX2) supply through second IF filter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced second mixer IF2 outputs are optional for many applications. Short the unused IF2P or IF2N output directly to the supply in single-ended applications. Limiter ground: minimize ground inductance Negative limiter input DC feedback loop decoupling: AC couple this pin to ground in close proximity to the pin. The DC voltage is approximately 1 V below the VCCA(LIM) supply on pin 31. No DC coupling. Negative limiter input: AC couple this pin to the second IF filter output or to ground if unused with single-ended filter applications. The DC voltage is approximately 1 V below the VCCA(LIM) supply on pin 31. No DC coupling.
VCCA(MX2)
19
2.7
5
MX2GND IF2INN
20 21
0 0.983
0 0.98
IF2INP
22
0.983
0.98
STROBE
23
CMOS level
CMOS level
IF2P
24
2.7
5
IF2N
25
2.7
5
LIMGND BFCN
26 27
0 1.696
0 3.999
LIMINN
28
1.696
3.999
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
PIN VOLTAGE TYPICAL VALUES (V) VCC = 2.7 V LIMINP 29 1.696 VCC = 5 V 3.999
UAA1570HL
SYMBOL
PIN
DESCRIPTION Positive limiter input: AC couple this pin to the second IF filter output or to ground if unused with single-ended filter applications. The DC voltage is approximately 1 V below the VCCA(LIM) supply on pin 31. No DC coupling. Positive limiter input DC feedback loop decoupling: AC couple this pin to ground in close proximity to the pin. The DC voltage is approximately 1 V below the VCCA(LIM) supply on pin 31. No DC coupling. Limiter, sample clock squaring and sampler Emitter Coupled Logic (ECL) circuits power supply: decouple in close proximity to pins 26 and 31. If present, isolate from the common VCC line sourcing the first and second mixer by placing a large decoupling capacitor between this block and the mixers. Serial interface data input: this DC-coupled CMOS DATA input accepts 20-bit programming words into the synthesizer data input register, while the STROBE is LOW, on the rising edge of the CLOCK input. A DC short-circuit to ground is recommended with the default frequency plan.
BFCP
30
1.696
3.999
VCCA(LIM)
31
2.7
5
DATA
32
CMOS level
CMOS level
VDDD
33
2.7 5 SIGN bit TTL output driver power supply: critically isolate and (independent (independent separately decouple this digital VDDD supply from all other of VCC level) of VCC level) analog (VCCA) supplies. Maintain minimum trace lengths to decoupling components. Particular attention should be applied to prevent coupling into VCCA(LIM) pin 31. If SAA1575HL is used, use the digital supply from the back-end. TTL output TTL output Amplitude and time quantized second IF output signal: extreme care should be taken to isolate this sampled TTL output signal from all analog traces and components, particularly the second IF filter components at the limiter input. Avoid coupling into the reference oscillator signal trace. SIGN bit TTL output driver sink ground: critically isolate this digital supply ground from all other analog supplies and grounds. Maintain minimum trace lengths to decoupling components. Synthesizer power supply: decouple in close proximity to pin 38 Sample clock squaring input: accepts LOW-level AC coupled sample clock inputs directly from the PLL reference oscillator or DC-coupled externally squared digital clocks derived from the PLL reference oscillator after external frequency division. The maximum DC-coupled input level at pin 37 should not exceed 75% of the VCCA(LIM) supply value. The threshold level is set at half the supply value on VCCA(LIM) pin 31. PLL ground: minimize ground inductance; use close proximity decoupling to the VCCA(PLL) supply pin 36 this pin provides additional RF/IF shielding and has to be connected to ground
SIGN
34
DGND
35
0
0
VCCA(PLL) SCLK
36 37
2.7 1.34
5 2.5
PLLGND P39GND
38 39
0 0
0 0
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
PIN VOLTAGE TYPICAL VALUES (V) VCC = 2.7 V COMP 40 depends on VCO application VCC = 5 V depends on VCO application
UAA1570HL
SYMBOL
PIN
DESCRIPTION Charge pump phase frequency detector output: the PLL loop filter is connected in shunt and close proximity to this pin. The PLL loop filter tuning control voltage should be routed to the external VCO varactor circuit using minimal trace lengths in complete isolation from all potential coupling sources. this pin provides additional RF/IF shielding and has to be connected to ground this pin provides additional RF/IF shielding and has to be connected to ground LNA1 power supply: DC operation range 2.7 to 5 V; use close proximity RF decoupling to pins 44, 46 and 47. LNA1 ground 1: minimize RF ground inductance LNA1 input: use external RF AC coupling LNA1 bias circuit ground: minimize RF ground inductance LNA1 ground 2: minimize RF ground inductance LNA1 output: use external RF AC coupling. The DC voltage is approximately 1.3 V below the VCCA(LNA1) supply on pin 43.
P41GND P42GND VCCA(LNA1) LNA1GND1 LNA1IN BIASGND1 LNA1GND2 LNA1OUT
41 42 43 44 45 46 47 48
0 0 2.7 0 0.815 0 0 1.48
0 0 5 0 0.807 0 0 3.629
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
44 LNA1GND1
47 LNA1GND2
46 BIASGND1
handbook, full pagewidth
43 VCCA(LNA1)
48 LNA1OUT
38 PLLGND
41 P41GND
39 P39GND
42 P42GND
45 LNA1IN
40 COMP
VCCA(LNA2)
37 SCLK
1
36 VCCA(PLL) 35 DGND 34 SIGN 33 VDDD 32 DATA
LNA2GND1 2 LNA2IN 3 BIASGND2 4 LNA2GND2 5 LNA2OUT 6 CLOCK 7 REFIN 8 VCCA(VCO) 9 TANK 10 VCOGND 11 P12GND 12
UAA1570HL
31 VCCA(LIM) 30 BFCP 29 LIMINP 28 LIMINN 27 BFCN 26 LIMGND 25 IF2N
IF2INN 21
MXPGND 13
MX1IN 14
MX1GND 15
VCCA(MX1P) 16
VCCA(MX2) 19
MX2GND 20
IF2INP 22
IF1P 17
IF1N 18
STROBE 23
IF2P 24
MHB270
Fig.2 Pin configuration.
1999 May 10
10
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7 FUNCTIONAL DESCRIPTION
UAA1570HL
The programmability of the UAA1570HL and flexible interface definitions allow the device to be configured for a wide range of applications. To restrict the content of this document the functional description of the device will generally concentrate on the C/A-code application circuit based on the default frequency plan. The application circuit does not allow easy measurement, calibration and documentation of the many sub-block characteristics which ensure good system performance. Therefore, test boards have been developed which allow direct measurement of the sub-block characteristics. The tables and graphs reflect the UAA1570HL specification as derived from simulation and measured results in these characterization board environments. The tables and graphs do not directly specify application board expectations. The functional description however, focuses on the default application. The RF system diagram (see Fig.3) illustrates the default application of the UAA1570HL in the Philips GPS demonstration board. In this application the UAA1570HL is intended to be operated directly from a passive GPS antenna through a very short antenna cable. Any cable loss in this demonstrator adds directly to the system noise figure and should therefore be minimized.
LNA1 can be powered down in the UAA1570HL to accommodate applications built around external LNAs, typically where long antenna cable runs are required. The first LNA is assumed to be matched with a 2nd-order band-pass structure to provide some input selectivity, since no dielectric or SAW filter has been used in the demonstration board. It should be noted that low loss RF SAW filters now make it possible to significantly improve the jam immunity of this amplifier, by placing a SAW filter at the output of the antenna. On the demonstration board the first LNA is followed by a low loss RF SAW filter (<2.4 dB). On the demonstration board the second LNA has been matched to 50 using a simple transmission line structure. Finally, another identical RF SAW filter follows the second LNA into the first mixer.
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
C327 L = 1020 mils W = 8.8 mils C328 R307 VRF L = 900 mils W = 8.8 mils L = 376 mils W = 33 mils 50 line stretcher VRF VRF C346 OPTIMUM PERFORMANCE REQUIRES THAT THE GPS DIGITAL BASEBAND, SUPPLY REGULATORS, AND OTHER SOURCES OF DIGITAL NOISE BE PLACED IN THIS RELATIVE ORIENTATION TO THE UAA1570HL.
C326 J301 ISOLATE THE REFERENCE INPUT AND ITS HARMONICS FROM THE FIRST IF AND ITS FILTERING COMPONENTS
C325 C324 Vtune R315 L = 315 mils W = 6 mils 100 C341 C335 C340 R319
SC LK S, AL NM G RO . SI F NS S AL D IO IT N T IG U C D RO UN EGF ES ND RF TH , A OG TE IES AL LA L N OPA IS UP LL SA
L = 355 mils W = 6 mils 100 C321
VRF REFIN C334 1 L = 286 mils W = 6 mils 100
48
47
46
45
44
43
42
41
40
39
38
37 36
SAW C307
3 C323 4
34 C329 33 VDDD DATA C347
5 C306 C320 6 L = 412 mils W = 6 mils CLOCK 100
32
31
UAA1570HL
7 30
C337
SI
G
N
BPF301
2
35
C311 REFIN C331 VRF R314 C338 L305 R316 11 C339 D301 12 Vtune L = 217 mils W = 33 mils 50 line stretcher BPF302 SAW L = 386 mils W = 6 mils 100 R311 R310 C305 R306 L304 STROBE 13 14 15 16 C330 17 18 C313 19 C332 20 21 C319 22 23 24 25 C301 26 10 27 9 28 C336 8 29 C312 C310 R305
C303 L302 L301 C309
R301/C301
C304
C302
L309 R323 L308
C345
C322
C318 R322 analog ground C315 digital ground L306 L307 L303 C316 C314
C317
C308
MHB271
Fig.3 UAA1570HL RF system diagram (default application).
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.1 Low noise amplifiers LNA1 and LNA2
UAA1570HL
Two identical LNAs are provided on the IC although LNA1 need not be biased, if sufficient external gain is provided by an external LNA. The input stage of each amplifier consists of an unbalanced common emitter and a cascode stage. The AC-coupled output stage is a compound feedback bootstrap amplifier. Each stage is independently biased and regulated. LNA1 can be disabled by connecting the respective supply (pin 43) to ground. LNA2 has to be powered-up even if not used. Each LNA can supply a power matched gain of approximately 15.5 dB with an associated noise figure of 3.7 dB. Both LNAs have -1 dB input compression points of approximately -22 dBm from a 3 V supply. The 2nd and 3rd-order input intercepts are approximately -7.9 and -13 dBm, respectively, in a power matched environment. The RF match impedances at L1 (1.57542 GHz) are provided in Table 1 for all RF inputs and outputs. Table 1 PIN 45 48 3 6 14 RF matching impedances REAL PART () 31 77.5 24 74.5 33.5 IMAGINARY PART () -j32 +j6 -j25 -j0.5 -j25.5 FUNCTION LNA1 input LNA1 output LNA2 input LNA2 output 1st mixer input
These RF port impedances are marked on the following Smith charts (see Figs 4 to 8; normalized to 50 ) and suggested matching structure netlists are provided. They contain transmission lines defined by their characteristic impedance Z (in ohms), their electrical length E (in degrees) and the operating frequency f (in GHz). Capacitors C are given in pF. TLIN is a series transmission line and TLOC is an open-circuit stub transmission line. Node 1 is the UAA1570HL RF port being matched and Node 0 is ground. These matching networks are structurally identical to those illustrated on the GPS application block diagram, however, the component values in the application diagram are somewhat different to account for stray capacitances and other real world influences. The netlists are derived from EEZMATCH software (Besser Associates, Los Altos, CA, USA). Generally, we assume a minimum shunt capacitance, due to the IC pin pad and adjacent pin strays, of approximately 0.25 pF as an initial stray element in the netlist below, that will always be present in the matching structure design. This value should be re-estimated and matched if the layout introduces significant additional strays at the pin pads.
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.1.1 LNA1IN
UAA1570HL
CAP 1 0 C = 0.25 ! C1 C = PF TLIN 1 2 Z = 97.0 E = 34.5 F = 1.57542 ! TL1 Z = OH, E = DEG, F = GHZ CAP 2 0 C = 2.0 ! C3 C = PF Alternatively the 2 pF shunt capacitance at the input of the 97 matching line above might be replaced with a 25 microstrip open stub if space permits. TLOC 2 0 Z = 25.0 E = 26.1 F = 1.57542
handbook, full pagewidth
1 0.5 2
0.2
5 10
+j
0
0.2
0.5
1
2
5
10
-j
10
0.2
5
0.5 1
2
MHB318
Fig.4 LNA1 input impedance and matching network.
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.1.2 LNA1OUT
UAA1570HL
To facilitate matching of both LNA outputs, a small shunt capacitance should be placed as close as possible to the output pin pad increasing the assumed 0.25 pF lumped pin capacitance by approximately 0.5 pF to 0.75 pF. This ensures that a simple, short, high impedance transmission line will provide a good 50 match at high gain. A via to the opposite side of the board right at this output pin allows a stub or chip capacitance to be added without comprising the characteristics of the 97 matching line. CAP 1 0 C = 0.25 ! C22 C = PF IND 1 28 L = 0.7 ! L7 = NH CAP 28 0 C = 7.1658792e-1 ! C23 C = PF TLIN 28 29 Z = 97.0 E = 26.239010 F = 1.57542 ! TL15 If an open line stub is used, the latter components have to be replaced by: TLOC 28 0 Z = 20.0 E = 8.0 F = 1.57542 ! OTL7 Z = OH, E = DEG, F = GHZ TLIN 28 30 Z = 97.0 E = 26.2 F = 1.57542 ! TL16 Z = OH, E = DEG, F = GHZ
handbook, full pagewidth
1 0.5 2
0.2
5 10
+j
0
0.2
0.5
1
2
5
10
-j
10
0.2
5
0.5 1
2
MHB319
Fig.5 LNA1 output impedance and matching network.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.1.3 LNA2IN
UAA1570HL
CAP 1 0 C = 0.25 ! C13 C = PF TLIN 1 14 Z = 97.0 E = 30.0 F = 1.57542 ! TL9 Z = OH, E = DEG, F = GHZ CAP 14 0 C = 2.3309277 ! C14 C = PF
handbook, full pagewidth
1 0.5 2
0.2
5 10
+j
0
0.2
0.5
1
2
5
10
-j
10
0.2
5
0.5 1
2
MHB320
Fig.6 LNA2 input impedance and matching network.
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.1.4 LNA2OUT
UAA1570HL
CAP 1 0 C = 0.25 ! C22 C = PF IND 1 31 L = 0.1 ! L8 L = NH CAP 31 0 C = 0.5 ! C24 C = PF TLIN 31 32 Z = 97.0 E = 25.077020 F = 1.57542 ! TL17 Z = OH, E = DEG, F = GHZ In the event that the second capacitor is replaced by an open line stub, the last two components have to be changed: TLOC 31 0 Z = 20.0 E = 5.5 F = 1.57542 ! OTL8 Z = OH, E = DEG, F = GHZ TLIN 31 33 Z = 97.0 E = 24.460094 F = 1.57542 ! TL = 18 Z = OH, E = DEG, F = GHZ
handbook, full pagewidth
1 0.5 2
0.2
5 10
+j
0
0.2
0.5
1
2
5
10
-j
10
0.2
5
0.5 1
2
MHB321
Fig.7 LNA2 output impedance and matching network.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.1.5 MX1IN
UAA1570HL
CAP 1 0 C = 0.25 ! C5 C = PF TLIN 1 13 Z = 100.0 E = 31.083933 F = 1.57542 ! TL9 Z = OH, E = DEG, F = GHZ CAP 13 0 C = 1.673902 ! C6 C = PF Again an alternative open stub line is suggested which could be used to replace the 1.67 pF capacitance at this end of the previous netlist. TLOC 13 0 Z = 25.0 E = 23.0 F = 1.57542 ! OTL5 Z = OH, E = DEG, F = GHZ
handbook, full pagewidth
1 0.5 2
0.2
5 10
+j
0
0.2
0.5
1
2
5
10
-j
10
0.2
5
0.5 1
2
MHB322
Fig.8 MX1 input impedance and matching network.
1999 May 10
18
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.1.6 GENERAL REMARKS AND RESULTS
UAA1570HL
The RF match has an important effect on the gains, noise figure, and dynamic characteristics of the RF system blocks. Reflection coefficients better than -15 dB are easily attainable and can be improved to better than -25 dB with attention to details.
handbook, halfpage
20 output (dBm) 0
MHB272
-20 -40 -60 -80 -100 -90
(1)
(2)
(3)
(1) Fundamental output. (2) 3rd-order product output. (3) 2nd-order product output.
-70
-50
-30 -10 input (dBm)
Fig.9 Typical LNA fundamental, 2nd and 3rd-order product output levels as a function of input level.
In the following graph (see Fig.10) the solid trace GLNA (dB) represents the measured frequency response of the UAA1570HL LNAs as measured on a spectrum analyzer, while the dotted and dashed results were obtained using a noise figure meter over a more restricted frequency range.
handbook, halfpage
30
MHB273
GLNA (dB) 20
(2)
1575.42
15.3 (1)
10
3.68
0
(3)
(1) LNA gain (dB). (2) Power gain. (3) Noise figure.
-10
0
1000
2000
f (MHz)
3000
Fig.10 Typical LNA gain and noise figure as a function of frequency (50 power matched on the input and output).
1999 May 10
19
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.2 Correlation of the UAA1570HL data sheet, application and test boards
UAA1570HL
The application circuit does not allow easy measurement, calibration and documentation of the many sub-block characteristics which ensure good system performance. Therefore, test boards have been developed which allow direct measurement of the sub-block characteristics. These boards use a 1 : 16 ratio RF transformer to transform 50 to the more appropriate value of 800 at IF frequencies. The high-impedance side of these transformers is terminated with a physical resistor to adjust the UAA1570HL impedance at the port being measured, to approximately 800 . This ensures that a calibrated signal is applied or received in the 50 test environment. The transformer provides marginal performance at 41.8 MHz, so calibration results for this transformer are also included in this document. The 800 impedance environment is somewhat less than that used in the application board. The UAA1570HL Characteristic tables provided in this document are calibrated to this 800 environment as quantified in the notes at the end of the table. The effects of the transformer and associated termination losses have also been removed to some extent, so that specifications reflect the performance of the IC. The measured graph results were all derived from the test boards and corrected to again reflect part performance as much as possible. However, this was not always possible, so some discussion concerning the measurement limitations is provided where appropriate. Where possible, fundamental design relationships and limitations are indicated. The following two graphs (Figs 11 and 12) reflect the measured performance of the 1 : 16 ratio RF transformer used to test the IF functions. Two transformers were placed back-to-back to make these measurements. Figure 11 represents the transmission function of just one of these transformers over frequency. Figure 12 represents the associated return loss at one input with the second transformer terminated into 50 . In the actual UAA1570HL test board a single transformer is terminated in 800 .
In addition to the direct effects of power losses introduced by the transformer (approximately -1.3 dB at 41.82 MHz), which are reflected in the measured S21 results, the test board results may also be impacted by deficiencies in the transformer 1 : 4 voltage step-up ratio at 41.8 MHz; however, this has not been quantified. An additional correction must be made to the current test results to compensate for internal 4 pF shunt capacitors on each collector output of the first mixer, which have not been resonated out in the testing. The first mixer measurements also include a 3 dB loss due to the 800 transformer termination. This loss is also removed from the specification result. The second mixer has similar 2.1 dB input and 3 dB output transformer termination losses removed from the specification. For measurements made at 3.48 MHz in the second IF, 0.4 dB must be added to the measured results to reflect transformer losses at IF2, also. In summary the measured gain of the first mixer has been increased by 1.3 dB (transformer IL) + 1.4 dB (capacitive roll-off effects) + 0.2 dB (gain match) + 3 dB (output transformer termination loss) or 5.9 dB to calibrate out these losses in the specification. The measured gain of the second mixer has been increased by 1.3 dB (input transformer IL) + 1.7 dB (input term loss) + 0.4 dB (output transformer IL) and + 3 dB (output term loss) or 6.4 dB to calibrate out these losses in the specification.
1999 May 10
20
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
MHB274
handbook, halfpage
0 S21
(dB) -1
(1) (2)
-2
-3
(3)
-4
-5
0
20
40
60
80
100 f (MHz)
(1) S21; Tamb = -40 C. (2) S21; Tamb = +25 C. (3) S21; Tamb = +85 C.
Fig.11 S21 for the test measurement transformer.
MHB275
handbook, halfpage
20 S11 10
(dB)
0
-10
(1) (2) (3)
-20
-30
0
20
40
60
80
100 f (MHz)
(1) S11; Tamb = -40 C. (2) S11; Tamb = +25 C. (3) S11; Tamb = +85 C.
Fig.12 S11 for the test measurement transformer.
1999 May 10
21
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.3 RF mixer with preamplifier
UAA1570HL
The 1st mixer (the RF mixer) consists of an RF preamplifier followed by a Gilbert cell mixer. The RF preamplifier consists of the same unbalanced common emitter and cascode stage as used in the LNAs, but without the compound feedback bootstrap output stage. The cascode output is AC-coupled into one side of the lower tree of the Gilbert cell mixer. The other side is internally AC-coupled to mixer ground via a 20 pF decoupling capacitor. The Gilbert mixer RF input is degenerated with low loss inductive emitter feedback to increase the effective -1 dB compression point and intercept points. Referenced to the preamplifier input, the -1 dB compression point and 3rd-order intercept point are -25.4 dBm and -16.3 dBm, respectively. Another important first mixer parameter is its 2nd-order input intercept point, which will extrapolate to approximately 1.38 V (peak value) differential or +12.8 dBm in the 50 mixer input environment. The differential output of the Gilbert cell mixer is open-collector to allow optimization of conversion gain and matching to the first IF filter over a wide range of frequencies and filter options. The total conversion gain is therefore determined by the real part of the effective output load, which is given by the IF filter input impedance and loss and/or fixed filter input matching networks, if present. The voltage conversion gain can be estimated by multiplying the effective single-ended to differential transconductance value for the first mixer (0.0531 A/V) by the total effective differential output resistance. The total power conversion gain to a differential load can be estimated from the voltage conversion gain by subtracting diff_load 10 log --------------------- . The total power delivered by the mixer to 50 the output resistance is distributed between the fixed output termination, the IF filter input impedance, as well as equivalent loss impedances associated with the finite Q of filter components. The assumption has also been made that the output impedance which the mixer sees is real, at least in the IF band. Note: The open-collector outputs of the first mixer each include internal 4 pF capacitors to ground. These capacitors should be included in the design of the first IF filter by removing 2 pF from the differential input capacitance for balanced filters and 4 pF from single-ended designs.
Therefore, the test circuit voltage conversion gain is estimated at 0.0531 A/V times the effective differential loading of approximately 440 . This results in a voltage conversion gain of approximately 27.4 dBV. Subtracting 9.4 dB to convert from power in a 50 environment to power into 440 , we see that the first mixer delivers a total power conversion gain of approximately 18.0 dB in the test circuit. It is important to note that approximately 3 dB of this available power gain is lost in the test circuit output transformer termination and that much of this power can be recovered in application circuits. The peak differential output voltage swing of the mixer should be limited to less than approximately 1 V (peak value) or 2 V (p-p) differential or 0.5 V (peak value) single-ended to prevent clipping by the internal output ESD protection diodes and to prevent mixer output saturation. This implies that effective differential output loads of approximately 2.5 k could result in clipping at the output of the mixer. The first mixer output structure also supports single-ended first IF filter applications. By taking one of the mixer outputs to the supply rail, the other can drive a single-ended first IF filter, thereby reducing external component cost in some applications. Maintaining the same single-ended loading impedance, as in the differential case (i.e. double the effective single-ended load) results in the same peak voltage across the same load, even with only half the transconductance 12(0.0531 A/V) available. Therefore the same power is delivered to the same filter load and the conversion gain remains the same. However, an effective load of 1.25 k would also bring this single-ended mixer output to the same clipping point as the full differential equivalent load of 2.5 k. The maximum recommended first mixer single-sided voltage conversion gain (input to one output) is therefore approximately 32 for both single-ended and differential output applications. The power matched Double-Side Band (DSB) noise figure of the RF mixer with preamplifier is approximately 12 dB at 1.57542 GHz from a 3 V supply.
1999 May 10
22
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, halfpage
20 output (dBm) 0
MHB276
-20 -40 -60 -80 -100 -90
(1)
(2)
(3)
-70
-50
-30 -10 input (dBm)
(1) Fundamental output. (2) 3rd-order product output. (3) 2nd-order product output.
Fig.13 Typical first mixer fundamental, 2nd and 3rd-order product output levels as a function of input level.
MHB277
handbook, halfpage
20
FDSB (dB)
(3)
16
12
(2)
8
(1)
4
0 2 3 4 VCC (V) 5
(1) FDSB; Tamb = -40 C. (2) FDSB; Tamb = +25 C. (3) FDSB; Tamb = +85 C.
Fig.14 Typical RF mixer noise figure as a function of temperature and supply voltage (test board).
1999 May 10
23
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.4 VCO
UAA1570HL
The VCO consists of a single transistor in common collector configuration with internal positive feedback realized by capacitors connected from emitter to ground and emitter to base. Together with the external resonator/inductor, this is a typical Colpitts circuit. With the transistor's base connected to pin 10 (TANK), the internal circuit arrangement produces a large negative input impedance at this pin. At VCCA = 3 V and Tamb = 27 C the oscillator transistor is initially biased with approximately 1.5 mA of start-up current. This value is relatively constant varying from approximately 1.56 mA at Tamb = +120 C to 1.4 mA at Tamb = -55 C. During operation, the average currents are higher due to the large amplitudes involved leading to rectification and bias point shifting. The VCO operates as a negative impedance oscillator with a suitable external inductive resonator.
Series or parallel resonators can be used, while tuning is achieved by an external varactor diode. VCO gain as well as the out-of-loop bandwidth phase noise are dependent on the choice of external elements used here. Consequently, they should be selected with great care; their quality factor is especially important and should be as high as possible. Finally, the VCO is followed by a differential buffer stage with emitter follower inputs splitting the signal to the divider and LO driver stage path to increase isolation between mixer and synthesizer and their wanted or unwanted signals. This first buffer stage is followed by two other specialized buffer amplifier stages in the individual signal paths bringing the signal to the required levels for driving a mixer or a divider.
MHB278
handbook, full pagewidth
100
(1)
R () 0
(2) (3)
-100 4 C (pF) 2
(1) (3) (2)
0 0 0.5 1 1.5 2 2.5 f (GHz) 3
(1) Tamb = -55 C. (2) Tamb = +27 C. (3) Tamb = +120 C.
Fig.15 Simulated VCO small signal negative resistance (top diagram) and capacitance (below), without strays.
1999 May 10
24
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, halfpage
2.4
MHB279
2.0
(1)
1.6
(2)
1.2
0.8
0.4 0.4
0.6
0.8
1
2 f (GHz)
3
(1) Corrected for strays. (2) Raw data 3 V supply voltage.
Fig.16 Magnitude of the reflection coefficient of VCO negative resistance tank pin (measured).
handbook, halfpage
0
MHB280
(deg)
-40
-80
(2)
(1)
-120
-160
-200 0.4
0.6
0.8
1
2 f (GHz)
3
(1) Corrected for strays. (2) Raw data 3 V supply voltage.
Fig.17 Phase of the reflection coefficient of VCO negative resistance tank pin (measured).
1999 May 10
25
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.5 First IF filter Rs = 331
UAA1570HL
The first IF filter provides four functions: 1. It provides selectivity to protect the 2nd mixer (the IF mixer) from high level spurious RF signals which pass through the wide band-pass envelope of the RF filters, typically 40 to 60 MHz. 2. The filter attenuates thermal noise and spurious signals in the 2nd mixer image band. 3. It can provide impedance matching/transformation from the RF mixer output to the IF mixer input. 4. It can reject spurious common mode and/or differential signals generated by high level local sources such as harmonics of the reference clock or sample clock. The first IF can be structured to support a wide range of single-ended or balanced filters including LC or SAW realizations. High RF gain provides first IF signal levels high enough to accommodate first IF filter losses of 15 dB with optimum RF matching and conversion gain in the first mixer. The Philips application board uses a 6th-order coupled resonator filter based on the butterworth response. The design method is described in the "Handbook of FILTER SYNTHESIS" by Anatol Zverev. The handbook tables formulate single-ended filter designs which we later convert to a balanced form. The initial centre frequency and bandwidth were 41.82 and 4.5 MHz, respectively. The following list illustrates the tabular design 3 dB down k and q parameters from Zverev that were developed for the initial single-ended structure. Rs = 331.4 RL = 689.6 q0 = 5.0; insertion loss = 4.742; q1 = 0.8226; qn = 1.7115; k12 = 0.6567; k23 = 0.7060. This tabular listing was chosen based on the desired selectivity and minimal insertion loss, which could be realized with available surface mount inductors operating with quality factors (Q) in the range of 40 to 50. The impedance level is determined by the choice of design inductance (165 nH), with foresight given to eventual balancing of the design. Maximizing the load presented to the first mixer was also a consideration. With some frequency plans stability in both the first and second IF will also need to be considered when choosing the impedance level of the design. The handbook calculations result in a preliminary single-ended three shunt tank structure with a coupling capacitor between each tank as follows: 1999 May 10 26
Tank 1 = 165 nH in parallel with 81.6 pF Coupling capacitor 1 = 6.2 pF Tank 2 = 165 nH in parallel with 74.9 pF Coupling capacitor 2 = 6.7 pF Tank 3 = 165 nH in parallel with 81.1 pF RL = 690 . To convert this filter to a balanced design it can be mirrored in the ground plane which would result in the following balanced structure. It should be noted that the tank design inductances have doubled while the tank capacitances have halved, which can be seen by removing the virtual ground plane. The series elements remain unchanged in the balanced design, while the differential source and load have of course doubled. Rs = 663 Tank 1 = 330 nH in parallel with 40.8 pF Coupling capacitor 1 = 6.2 pF Tank 2 = 330 nH in parallel with 37.5 pF Coupling capacitor 2 = 6.7 pF Tank 3 = 330 nH in parallel with 40.6 pF RL = 1380 . To optimize the power developed by the first mixer its load was maximized by driving the 1380 side of this filter. It was also decided to bias the output of the first mixer through Tank 3 components by breaking the former differential 330 nH inductor back into two 165 nH inductors connected to the supply which also acts as a virtual ground. The filter was then resimulated in `SPICE' to optimize against available discrete surface mount component values with finite quality factors. All filters must be driven by their design impedances to produce their prescribed response. Since the finite quality factors of the filter inductors emulate an equivalent shunting load of approximately 2 x x f x L x Q, the source and load terminating impedances can be increased to compensate for this parasitic element while maintaining ideal filter response and minimizing losses. In the default application, R322/306 in conjunction with the equivalent parallel resistance at the respective filter input and output give the desired terminating impedance.
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
The limitation imposed by image noise is illustrated in Fig.18 where the ideal calculated filter response is compared against the measured noise density at the output of the first IF filter. The single sided FET probe measured result was corrected by +6 dB to account for 50 balanced processing and 10 log --------------663 or -11.2 dB to accommodate power conversion losses. The IF noise density selectivity is seen to be limited by the available RF gain and noise figure of the first mixer. At the image frequency, 34.86 MHz, the measured noise floor is approximately 13 dB below the desired IF level at 41.82 MHz. This will result in an image contribution to the noise figure of the system of approximately 0.2 dB.
UAA1570HL
The in-band noise density can be estimated based on the single-ended voltage gain to the output of the IF filter. With the antenna thermal input level at approximately -174 dBm/Hz, noise figure of approximately 4 dB and voltage gain from the antenna to the IF filter output of approximately 47 dBV (at 5 V supply voltage), we can expect the differential noise power density to be approximately -174 dBm + 4 dB + 47 dBV + 6 dB 663 (conversion to balanced) - 10 log --------------50 or -129 dBm/Hz. The final term converts the measured power using a high impedance FET probe, calibrated to a 50 environment, to the actual 663 differential filter output environment.
handbook, halfpage 34.86 x 106/sec
-120
MHB281
Nd (dBm/Hz) -130
41.82 x 106/sec
-140
(2)
(1)
-150
-160 30 34 38 42 46 f (MHz) 50
(1) Ideal calculated filter response. (2) Measured filter noise density.
Fig.18 First IF filter output noise power density (application board).
1999 May 10
27
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.6 Second IF mixer
UAA1570HL
The second mixer is a standard Gilbert cell mixer operating with a total tail current of 4.3 mA, which is Proportional To Absolute Temperature (PTAT). The RF input, or lower tree of the mixer, is not internally terminated other than by 5 k biasing resistors to each input. With no significant emitter degeneration, the real part of the RF port input impedance is dominated by the two differential junction Rs in parallel with the bias elements. The differential output of the Gilbert cell mixer is open-collector to allow the conversion gain and matching to the second IF filter to be optimized over a wide range of frequencies and to many types of IF filters. The conversion voltage gain is determined by the tuned real part of the effective output load. This load may consist of the IF filter input impedance as well as fixed filter input matching compensation terminations and losses. The voltage conversion gain can be estimated by multiplying the effective differential conversion transconductance value (0.0294 A/V) by the total effective differential load at the output of the mixer. The conversion power gain is best described relative to specified mixer input and output impedance environments. The power conversion gain is calculated by subtracting output resistance environment 10 log ------------------------------------------------------------------------------- from the dBV value input resistance environment of the voltage conversion gain of the mixer. It should be noted that differential second mixer input terminations may be DC-coupled. We can simplify and estimate the second mixer conversion gain in the default application by noting that the input impedance environment is approximately 663 , while the output environment is approximately 1394 . With effective output loading of 854 (2.2 k in parallel with 0.7 x 2 x 996 ) the voltage conversion gain can therefore be expected to be approximately 25.1 V/V or 28 dBV. The power correction from 663 at the input to 1394 (0.7 x 2 x 996 ) at the output is -3.2 dB, so the resulting power conversion gain is approximately 24.8 dB. The factor of 0.7 in the calculation of the impedance level is explained in Section 7.7. It should be noted that a balanced coupled k filter can be converted to a single-ended equivalent with a single-ended input impedance exactly equal to that of the full differential filter by keeping the same tank resonator components, but placing the series coupling capacitors in single-ended series (i.e. halving the differential value) and AC grounding one side of the tanks.
The demonstration board was converted from a balanced second IF filter in this manner. To optimize the noise figure of the second mixer the input termination admittance should be reduced. However, this will be at the expense of the mixers input compression and 3rd-order intercept characteristics. Since the RF input of the IF mixer is a simple differential stage, the input -1 dB compression point and 3rd-order intercept points are relatively fixed at approximately 67 and 215 mV (peak value), respectively, in the second mixer. This results from noting that an undegenerated differential input can be expected to have an input -1 dB compression point of approximately 36.6 mV (peak value) differential. With a small additional extrinsic emitter degeneration the -1 dB compression point is raised to approximately 67 mV (peak value) differential. This is approximately -24.7 dBm in the 663 second mixer GPS application input environment with the 3rd-order intercept point being approximately 10 dB higher at -14.6 dBm. Another important second mixer parameter is its 2nd-order input intercept point, which will extrapolate to approximately 79.8 V (peak value) differential or 36.8 dBm in the 663 mixer input environment. The peak output voltage swing of the IF mixer should be limited to a peak differential swing of less than approximately 1 V (peak value) or 2 V (p-p) differential to prevent clipping by the internal output ESD protection diodes and to prevent mixer output saturation. This implies that an effective differential output load of approximately 3.2 k could result in clipping at the output of the mixer. The IF mixer supports single-ended first and second IF filter applications. A single-ended input is implemented by AC bypassing one side of the IF mixer input to ground and accepting an associated drop in mixer conversion voltage gain. It should be noted that single-ended input terminations can still be DC-coupled to the mixer input pins by using the above mentioned bypass capacitor. The IF mixer output can be made single-ended by connecting the unused mixer output to the supply rail. Extra care should be taken to characterize single-ended first IF applications. Using a single-ended second IF filter in combination with a balanced first IF filter may help reject common mode signals not rejected by the first IF filter. However, it should be noted that the differential tank capacitors of the fully differential IF filters can be replaced by common mode capacitors by doubling the differential value and connecting two of these capacitors to ground. Any distribution between these two extremes is also acceptable.
1999 May 10
28
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
As with the RF mixer maintaining the same single-ended load as an effective differential load would result in the same voltage applied to the equivalent resistance. However, a single-ended effective load of 1.6 k could also bring this mixer output to its clipping point. The maximum recommended second mixer single-sided voltage conversion gain (one input to one output) is therefore approximately 16 for both single-ended and differential output applications. The estimated Single-Side Band (SSB) noise figure of the IF mixer is approximately 7.5 dB at Tamb = 27 C from a 3 V supply with an input termination matching resistor of 2 k. Removing the termination results in an expected noise figure of 4.9 dB from a 1 k source. This degradation is distributed between the input termination input loss and approximately a 1.6 dB increase in the actual mixer noise figure. The conversion gain is expected to be relatively supply independent, increasing by only approximately 0.5 dB from a supply value of 2.7 to 5.5 V. The IF mixer RF bandwidth is also expected to only increase by approximately 4%, while the mixer noise figure is expected to decrease by less than 0.1 dB as the supply is increased over the same supply range. The IF mixer RF bandwidth, if not resonated, is dominated by the mixer differential input capacitance of approximately 1 pF.
UAA1570HL
With tuned inputs, the IF mixer RF input bandwidth can be extended quite high, but practical consideration warrant that the RF filter terminating the input should provide band limiting, thereby restricting the RF high frequency roll-off to less than 200 MHz without special characterization efforts. This is also, generally, the upper limit that the programmable synthesizer supports. The noise figure of the IF mixer as well as the limiter can be expected to degrade as the operating frequencies are increased. For example, at 200 MHz in a terminated 100 system the DSB noise figure of the IF mixer will increase by at least 10 dB to approximately 18 dB. If stability permits low impedance first IF filters can be matched into the IF mixer using step-up matching circuits such as baluns or transformer like tuned networks, to minimize the degradations. The input compression point and noise figure of the IF mixer, as measured in the characterization test board, are plotted against temperature and supply voltage in Figs 19 and 20. The characterization test board employs the 1 : 16 ratio transformers to provide a 50 match to the 800 test environment. The losses of the input and output transformers, as well as transformer insertion losses at 41.82 and 3.48 MHz, have been removed before plotting. Therefore, this graph correlates to specification and expected performance of the second mixer in the referenced 800 environment.
handbook, halfpage
-24
MHB282
CP-1dB (dBm) -26
(3)
(2)
-28
(1)
(1) Tamb = -40 C. (2) Tamb = +25 C. (3) Tamb = +85 C.
-30
2
3
4
VCC (V)
5
Fig.19 IF mixer -1 dB input compression point (800 test circuit).
1999 May 10
29
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
MHB283
handbook, halfpage
6
FDSB (dB) 5
(3)
(2)
(1)
4
3 2 3 4 VCC (V) 5
(1) Tamb = -40 C. (2) Tamb = +25 C. (3) Tamb = +85 C.
Fig.20 IF mixer DSB noise figure (800 test circuit).
handbook, halfpage
20 output (dBm) 0
MHB284
-20
(1)
-40 -60 -80 -100 -90 (1) Fundamental output. (2) 3rd-order product output. (3) 2nd-order product output.
(2) (3)
-70
-50
-30 -10 input (dBm)
Fig.21 Typical second mixer fundamental, 2nd and 3rd-order product output levels as a function of input level (800 environment).
1999 May 10
30
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.7 Second IF filter
UAA1570HL
The second IF filter provides five functions: 1. It provides selectivity to protect the limiter input from spurious signals which pass through the first IF band-pass filter envelope, typically 5 MHz wide. 2. The filter attenuates undesired second mixer output products, such as the LO leak, to levels which will not block/capture the following limiter stage. 3. The filter defines and shapes the noise bandwidth to be amplitude quantized. 4. It can provide impedance matching/transformation from the IF mixer output to the limiter input while maintaining stability. 5. It can reject spurious common mode and/or differential signals generated by high level local sources such as harmonics of the reference clock or sample clock and digital processing noise from associated devices such as the SAA1575HL. The second IF can be structured to support a wide range of single-ended or balanced filters including LC or ceramic realizations. The available system gain can provide second IF signal levels sufficient to accommodate high second IF filter losses. The Philips application board again uses a 6th-order coupled resonator filter based on the butterworth response. The design method is described in the "Handbook of FILTER SYNTHESIS" by Anatol Zverev. Initially a skewed centre frequency and bandwidth were input at 3.1 and 1.75 MHz, respectively, to help overcome the asymmetry which is intrinsic in geometric low frequency band-pass filter designs as they approach DC. The following table design 3 dB down k and q parameters were used: Rs = 548 RL = 996 q0 = 20.0; insertion loss = 0.958; q1 = 0.8041; qn = 1.4156; k12 = 0.7687; k23 = 0.6582. This filter was originally mirrored by a virtual ground to convert it to a balanced form, but later the balanced components were converted back to a single-ended form (to reduce component count) simply by placing the balanced series capacitors in series on one side of the filter (effectively halving the capacitance value) and grounding the opposite side of the tanks where these series capacitors were removed. This effectively maintains the differential power gain while only using a single-sided output.
The filter was then resimulated in `PSPICE' to optimize against available discrete surface mount component values. Finally the filters input and output direction were reversed to ensure that the highest impedance side was placed at the mixer output to maximize the available power developed. A 909 termination was used at the output of the filter to terminate the 4.87 k limiter input. This effective 766 termination is somewhat lower than the initial design value of 2 x 548 or 1096 and therefore develops approximately -1.56 dB less power with respect to second mixer loading. The reduction of the impedance level by 30% (or a factor of 0.7) was done in order to have a large safety margin against instability of the limiter/quantizer path. Instability can be caused here by the large small-signal gain associated with this signal path in conjunction with the high signal levels present at the SIGN output. Furthermore, due to the strong non-linearities present in this signal path, LO2 leakage in conjunction with the IF2 itself can produce signals at the IF1 frequency and thus enter the IF1 filter together with the wanted signal. This impedance level reduction is passed through the second IF filter and consequently lowers the mixer 2 conversion gain by approximately 30%, too. The filter design was determined to be sufficiently tolerant to this adjustment by observing the effect on the filter's output noise response with respect to unstable peaking and maintaining the desired selectivity response. Care must be taken not to induce instability while observing the IF2 filter noise response by using a 10 : 1 divider in conjunction with a very low capacitance RF FET probe (<0.5 pF). In the default application, R323/305 in conjunction with the equivalent parallel resistance at the respective filter input and output give the desired terminating impedance. The frequency of the mixed down third harmonic of the reference oscillator is usually the most significant spurious product which is generated in the default frequency plan and must be kept at least 13 dB below the integrated noise response of the filter. For example, typical true power noise densities (Dn) for a nominal GPS demonstration board operating at 3 V are expected to be approximately -100 dBm/Hz differential at the input of the limiter and reflect the importance of designing a well matched RF system. Assuming that a somewhat lower gain variation has been realized with a noise density of approximately -105 dBm/Hz over an estimated 2 MHz noise equivalent bandwidth, it is possible to evaluate and measure the associated spurious product level that would result in a -13 dB jammer-to-noise (J/N) and 0.2 dB system noise figure degradations as follows:
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
The true power of a product at the output of the second IF filter in a 1 k environment should be no more than -105 dBm/Hz + 63 dB - 13 dB or approximately -55 dBm. The equivalent single-sided measurement with 548 a 50 calibrated probe would be - 55 dBm + 10 log --------50 or -44.6 dBm. Figure 22 illustrates the true noise power density as measured points for this lower gain case. The filter response of the first IF filter is translated to the second IF and superimposed at the second IF to show that the 3rd harmonic reference spur at 43.2 MHz, is not filtered by this response.
UAA1570HL
Also shown is the second IF filter response and the combined first and second IF filter selectivities, which account for total observed selectivity noise response. For difficult applications which require higher losses in the IF filters, self jamming can be minimized by choosing a reference and frequency plan which places the harmonics of the reference exactly at the second LO frequency, where they are benign.
handbook, halfpage x 106/sec 3.48
-90
MHB285
4.86 x 106/sec
Nd (dBm/Hz) -110
(1)
-130
(4)
(2) (3)
-150
0
4
8
12
f (MHz)
16
(1) IF1 filter response superimposed on IF2 filter response. (2) IF2 filter response (calculated). (3) IF2 filter noise density (measured). (4) IF1 filter response translated to IF2 frequency.
Fig.22 Second IF filter output noise density frequency response on the application board.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.8 Time and amplitude quantization
UAA1570HL
After frequency conversion in the double-superheterodyne portion of the UAA1570HL and filtering to approximately a 2 MHz bandwidth in the second and final IF filter, the frequency translated thermal noise from the GPS pass-band around the L1 carrier is ready to be converted to a digital signal for processing by the companion GPS chip-set part (SAA1575HL). First the thermal noise's sign is determined by amplitude quantization in a 1-bit hard limiter. This asynchronous information is then time quantized by latching in a master/slave D-flip-flop to complete the analog-to-digital conversion process. Finally, this ECL digital SIGN bit data is translated to TTL levels and sent to the SAA1575HL. Four differential stages are used to hard limit the thermal noise in the final IF. The total gain is approximately 63.9 dBV with a bandwidth of roughly 66 MHz and a noise figure of approximately 11.3 dB in a 1 k environment. The parallel equivalent differential input impedance of the limiter is 4.87 k in parallel with 0.3 pF. Offset control is provided through 42.5 k feedback resistors from each balanced output back to the inputs. External decoupling capacitors cut the feedback loop for AC signals. Limiter inputs as low as 25 V (peak value differential) are resolved at the output master flip-flop DFF1 in its transparent mode. As the master flip-flop is latched positive feedback resolves metastable states. While the master flip-flop is in its transparent state the positive feedback in the slave flip-flop will resolve the remaining metastable states as it is latched. Three forms of LO leakage can block the limiter if they capture the device.
The first is LO leakage from the first mixer output which will couple into the package die pad through internal 4 pF common mode capacitors at the output of the 1st mixer. This leakage signal is effectively filtered at the 2nd IF filter output, but reappears internally on all down-bonded grounds. It appears at a level of approximately 0.5 mV (peak value differential) across the limiter input transistor bases with an assumed 1st mixer input RF offset of approximately 1 mV. The second is LO leakage from the second mixer. Assuming 1.5 mV RF input offset, the leakage at the output of the second IF filter is expected to be approximately 500 V (peak value differential) (-69 dBm into 1 k) and sets the worst case nominal process blocking level. With a nominal -50 dBm IF thermal level at this point there is a 19 dB margin to blocking. To prevent blocking, IF filter losses should be minimized and the selectivity of the single-ended or differential second IF filter has to be designed and characterized to maintain this leakage product at least 11 dB below the integrated second IF filter thermal noise signal. The third form of blocking can occur if LO1 leakage is sufficiently high (greater than 15 mV (peak value) on the die pad) to be injected into the 2nd mixer regulators and all down-bonded IF grounds. This results in burst of LO1 leakage at the 2nd mixer LO2 zero transition points which increase LO2 leakage peaks by factors of 10. The gain response of the limiter from a low impedance source with no input strays is illustrated from the input to the output of each stage in Fig.23.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
80
MHB286
(4) (3) (2) (1)
G (dB)
0
-80
-160 10-2
10-1
1
10
102
103
f (MHz)
104
(1) (2) (3) (4)
Limiter input. 1st stage gain response. 2nd stage gain response. 3rd stage gain response.
Fig.23 Limiter input, 1st, 2nd and 3rd stage gain response as a function of frequency (simulated).
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
8
MHB287
R i(diff) (k) 6
(3) (2) (1)
4
2
0 10-2
10-1
1
10
102
103
f (MHz)
104
(1) Tamb = -55 C. (2) Tamb = +27 C. (3) Tamb = +120 C.
Fig.24 Limiter differential input resistance as a function of frequency (simulated).
7.8.1
CLOCK INPUTS
Both the reference and the sample clock input can be driven by a Temperature Compensated Crystal Oscillator (TCXO). Typical TCXOs produce 0.5 to 1.0 V (p-p) clipped sine wave outputs. The drive capability is typically 20 k in parallel with 5 pF or 10 k in parallel with 10 pF. Some TCXOs are even capable of driving loads as low as 1 k without buffering. Alternatively, cost can be reduced by designing a simple discrete crystal oscillator reference, paying careful attention to temperature tolerance (6 ppm) as well as shock and vibration characteristics. Both UAA1570HL clock inputs, the synthesizer reference input REFIN (pin 8), and the sample clock input SCLK (pin 37), accept low level inputs and provide internal gain/squaring circuits. The reference clock input has a high impedance with 20 k in parallel with 0.07 pF. A high stability, low phase noise crystal reference source should be AC-coupled to this port. Reference inputs up to 35 MHz and levels between 50 to 500 mV (peak value) are acceptable. This source can be externally squared and attenuated before 1999 May 10 35
being applied. Direct sinusoidal inputs should be as large as possible within the prescribed range to optimize phase noise performance. The sample clock input also features a high impedance of 23.3 k. The sample clock input can be AC-coupled directly to the reference if the system sampling objectives are met. Alternatively, the TCXO/XO reference can be externally squared to CMOS input levels and applied to the SAA1575HL RCLK input (pin 98) and divided under firmware control to produce a signal commensurate with the sampling objective. Due to the wide range of programmable frequency plans and sampling rates supported by the UAA1570HL, it is not possible to predict the frequencies and levels of the associated spurious products that will be generated. One significant source of potential spurs are the harmonics of the reference and sampling signals. The availability of on-chip squaring circuits provide some freedom to minimize large digital signal effects in sensitive RF circuit areas. In most cases digital sampling signal levels are acceptable as long as careful attention is paid to avoid injecting these signals or their harmonics into the pass bands of the IF filters.
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
The SCLK input of the UAA1570HL is self-biased at 50% of the analog supply voltage (VCCA) near the internal threshold level. It is therefore possible to operate this input with levels as low as 10 mV (peak value) in order to avoid large digital signal flow on the Printed-Circuit Board (PCB) runners. This is done in the default application with a 6.8 and 3.9 k resistive divider followed by a 10 pF AC coupling series capacitor in between the SAA1575HL and the UAA1570HL. However, when it is nevertheless intended to use full CMOS or TTL levels, some attenuation is required so that the peak sample clock input does not exceed 75% of the UAA1570HL analog supply voltage. This is especially important while the UAA1570HL is operating from a lower supply (3 V) than the SAA1575HL (5 V). A resistive divider can help in these cases, but the AC coupling method described above should be preferred. 7.8.2 CMOS TO ECL SAMPLE CLOCK SQUARING CIRCUIT
UAA1570HL
Since the TTL/CMOS output stage is transparent the SIGN bit output is updated on the rising edge of the CLK with the master latched and the slave transparent. This implies the DSP can expect SIGN bit data to be latched on the LOW CLK state. 7.8.4 TTL OUTPUT STAGE
The TTL output stage is a variation of a totem pole modified to operate from an independent isolated supply voltage from 2.7 to 5.5 V. This supply voltage is also independent of other supply voltages used in the UAA1570HL. Circuits to minimize cross-conductance and short-circuit currents are provided. Operating from a 2.7 V supply, VOL and VOH are nominally 132 mV and 1.95 V, respectively. Operating from a 5.5 V supply, VOL and VOH are nominally 195 mV and 4.6 V, respectively. Typical rise times of 8 ns and fall times of 10 ns can be expected from this output driving CMOS loads. 7.8.5 1-BIT DELAYS
The UAA1570HL internal sample clock squaring circuit allows single-ended sinusoidal clock inputs as low as 10 mV (peak value) over a frequency range from 5 to 35 MHz. The rise time of the clock output should be in the order of 25% of the maximum sampling frequency to ensure that aperture losses are less than approximately 1 dB (0.91 dB). The period of a 35 MHz clock is 28.57 ns. To keep the sampling aperture on the order of one fourth 28.57 ns this period implies a rise time of 5.7 ns ---------------------- is 4 x 1.25- required and should also be kept with lower sampling clock rates. Using a 14.4 MHz sampling rate test signal into the SCLK input results in good TTL eye pattern characteristics over a measured input range down to at least -25 dBm. At -35 dBm the effects of slew rate limiting begin to appear with the eye pattern closing beyond -40 dBm. 7.8.3 TIME QUANTIZATION (SAMPLER)
The rise and fall times of the TTL output with a 15 pF load are approximately 8 ns and are relatively independent of supply and temperature. A small decrease (1 to 2 ns) in rise and fall times is seen at Tamb = -55 C and a small increase at Tamb = 120 C (2 to 4 ns). Typical propagation delay times through the time quantization circuitry while switching amplitude quantization states from a 5.5 V supply are: SCLK input to TTL SIGN output 16 ns (rising edge) SCLK input to TTL SIGN output 17.6 ns (falling edge). 7.9 Programmable synthesizer
Two clocked D flip-flops are connected in a master/slave configuration to implement the sampling function of the 1-bit sampler. With the internal DFF clock (CLK) LOW the master flip-flop DFF1 is in its transparent mode and continuously follows the amplitude quantized limiter output. As the clock (CLK) goes HIGH the data is latched in the master flip-flop and the slave DFF2 becomes transparent to the latched output from the master flip-flop. The falling edge of the CLK signal latches the slave and again loads the limiter output into the master flip-flop. These stages also provide additional limiting gain for marginal input signals from the limiter. 1999 May 10 36
The UAA1570HL includes a programmable synthesizer allowing the main, second LO and reference dividers to be programmed under external control via a three-wire serial control bus. Alternatively, a LOW on the STROBE input on power-up will load a 20-bit default frequency plan word and power-on options into the synthesizer registers. Frequency plans with a 2nd IF of 4 x f0(1.023 MHz) = 4.092 MHz can be implemented. 7.9.1 VCO PRESCALER
After the VCO signal leaves its single-ended-to-balanced cascode buffer it is again amplified on its way to a high speed fixed divide-by-2 prescaler using a super buffer such as that described for the first mixer (see Section 7.3).
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
7.9.2 MAIN SYNTHESIZER DIVIDERS (N-PATH) 7.10.2 r5
UAA1570HL
The main synthesizer divider path includes an additional fixed divide-by-3 prescaler preceding a programmable variable N-divider which can be programmed over a range from 64 to 127. The output of the programmable divider passes through a fixed divide-by-2 and finally an optional divide-by-1 or divide-by-2 before being applied to the phase frequency detector. 7.9.3 SECOND LOCAL OSCILLATOR DIVIDERS (L-PATH)
Next a post reference scaler bit, r5, is set to program a divide-by-1 or divide-by-2 following the variable reference divider. With this bit set LOW the divide-by-2 post scaler is enabled and the phase frequency detector receives equal mark/space ratio reference port signals. This is the default state for this bit (r5 = 0). In the HIGH state the mark/space ratio is a function of the variable reference divider value, and the range of the reference divider is extended to lower division ratios. 7.10.3 r0, r1, r2, r3 AND r4
The second LO signal is divided down from the VCO prescaler output, first by a programmable L-divider and then by a fixed divide-by-2 before being buffered and applied to the second mixer. 7.9.4 REFERENCE DIVIDERS (R-PATH)
After squaring (limiting), the reference signal is divided down first by a variable R-divider. The divide ratio ranges from 4 to 31. The variable divider is followed by an optional divide-by-1 or divide-by-2 before being applied to the phase/frequency detector. 7.10 Serial interface
The three-wire serial bus consists of DC-coupled DATA, CLOCK and STROBE CMOS level inputs. The DATA input loads serial 20-bit programming words into the synthesizer data input register on each rising edge of the CLOCK input, while the strobe line is held LOW. The CLOCK signal should be set-up HIGH for at least 30 ns before the STROBE state is changed. Each DATA bit should be set-up for at least 30 ns before being clocked into the register and then held for at least 30 ns. The CLOCK rate should not exceed 10 MHz and the CLOCK pulse width should be at least 30 ns. The 20-bit DATA word definition follows in the order in which they are to be read (clocked) into the DATA register. 7.10.1 p0 AND p1
The next five bits clocked into the DATA register are the binary equivalent value of the variable reference divider ratio. The programmable range of this divider is 4 to 31, continuous. The default value is set to 4 (r0, r1, r2, r3, r4 = 0, 0, 1, 0, 0) with the Most Significant Bit (MSB) clocked into the DATA register first. The total reference division ratio is set by these five bits if r5 is set to the HIGH state. The range can be optionally doubled to even values from 8 to 62 if r5 is set LOW. This option is set in the default case, resulting in equal mark/space ratios as described above. The total default reference division ratio is therefore 8 with (r0, r1, r2, r3, r4, r5 = 0, 0, 1, 0, 0, 0). 7.10.4 n7
As in the reference divider case the main synthesizer divider includes an optional post scaler divider following the main programmable divider. This divide-by-1 or divide-by-2 is controlled by program word bit n7. With this bit set LOW the divide-by-2 post scaler is enabled and the phase frequency detector receives equal mark/space ratio signals at its main synthesizer port. The default state for this bit is (n7 = 1) which does NOT double the total main synthesizer divide ratio as described below. 7.10.5 n0, n1, n2, n3, n4, n5 AND n6
The first bit read into the synthesizer should be the power-down bit, p1, which enables one of two power-down states if set HIGH. The second bit read into the register, p0, defines the type of power-down. A complete power-down of the UAA1570HL is performed if this bit is set HIGH and a partial power-down with the synthesizer remaining on if this bit is set LOW. For normal operation of the UAA1570HL both of these bits are set LOW, which are also the default values for p0,p1 = 0,0. The final p0,p1 = 1,0 state is undefined.
The next seven bits clocked into the DATA register are the binary equivalent value of the variable main synthesizer divider ratio. The programmable range of this divider is 64 to 127, continuous. The default value is set to 71 (n0, n1, n2, n3, n4, n5, n6 = 1, 1, 1, 0, 0, 0, 1) with the MSB clocked into the DATA register first. The output of the main programmable divider includes a fixed divide-by-2 which modifies the previous range to all even values from 128 to 254, inclusive. The programmable portion of the main synthesizer division ratio is set by these seven bits if n7 is set to the HIGH state as described above for the default case.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
This ratio can again be optionally doubled by setting n7 LOW. The range is then extended to values from 256 to 508, inclusive, in increments of 4. Equal mark/space-ratio signals are always fed to the main synthesizer port of the phase frequency detector since the fixed divide-by-2 post scaler is always present. The main synthesizer path divisions ratio range, including the fixed divide-by-2 and divide-by-3 prescalers, is increased by a factor of 6 from 768 to 1524 in increments of 12 when n7 is set HIGH or from 1536 to 3048 in increments of 24 if n7 is set LOW. The total default main synthesizer path division ratio from the VCO is 12 x 71 or 852 with (n0, n1, n2, n3, n4, n5, n6, n7 = 1, 1, 1, 0, 0, 0, 1, 1). 7.10.6 l0, l1, l2 AND l3 7.12 The default frequency plan
UAA1570HL
The default synthesizer programming produces the following frequency plan: Table 2 Frequency plan PARAMETER RF input frequency VCO frequency RF image frequency First IF frequency Second LO division ratio Second LO frequency Second image frequency Second IF frequency Reference frequency Total main synthesizer division ratio Total reference division ratio Phase comparison frequency 7.13 VALUE 1.57542 GHz 1.5336 GHz 1.49178 GHz 41.82 MHz 2 x 10 x 2 = 40 38.34 MHz 34.86 Hz 3.48 MHz 14.4 MHz 2 x 3 x 71 x 2 = 852 2x4=8 1.8 MHz
The last four bits clocked into the DATA register set the programmable division ratio for the 2nd local oscillator. Again the MSB is read in first with the binary word set to a number between 4 and 15. The default values are set to 10 (l0, l1, l2, l3 = 0, 1, 0, 1). Again a post scaler is provided with a fixed divide-by-2 value to ensure that the LO signal exhibits equal mark/space ratios driving the second mixer. The programmable divider and fixed post scaler provide division between 8 and 30 in even increments. Since the 2nd local oscillator path from the VCO includes the divide-by-2 prescaler common to both the L-divider and N-divider paths, the total programmable 2nd local oscillator division range, relative to the VCO, is 16 to 60 in increments of 4. With the 20-bit programming word completely clocked into the DATA register the STROBE signal is returned to a HIGH state after a minimum delay of 30 ns to latch and effect the parallel loading of the programmed word states. 7.11 The serial interface word
Phase detector, charge pump and loop filter
The phase detector is of a phase and frequency sensitive digital type. In conjunction with the charge pump, it operates without a `dead zone'. The charge pump itself has a single-ended output delivering or sinking current pulses with a maximum amplitude of 240 A into the external loop filter. The layout for the connection between the loop filter and the VCO input should be made with utmost care in order to avoid other signals entering this path. The loop filter as chosen on the demonstration board yields a loop bandwidth of approximately 100 kHz, with a damping constant of 1. It consists of a 3.9 nF capacitor and a series resistor of 20 k, both in parallel with a 150 pF capacitor.
The complete default program word once serially loaded or loaded by default on power-up with the STROBE held LOW realizes the following frequency plan in the UAA1570HL. It should be noted that the MSB for the complete 20-bit program word is l0 and the Least Significant Bit (LSB) is p1 with the latter the first loaded into the DATA register. This is in contrast to the sequence in which the different bits determining the individual divider ratios are structured. The resulting default 20-bit word is: l0, l1, l2, l3, n0, n1, n2, n3, n4, n5, n6, n7, r0, r1, r2, r3, r4, r5, p0, p1 = 0, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
8 OPERATING MODE SELECTION TABLES Programmable operating modes MODE Normal Partial power-down Undefined Complete power-down 8.1 p0 0 0 1 1 p1 0 1 0 1 LNA1 yes no - no LNA2 yes no - no VCO yes yes - no MX1, MX2, 1-BIT yes no - no
UAA1570HL
Table 3
2nd LO yes no - no
DPLL yes yes - no
Manual selection operating modes
Some applications of the UAA1570HL may require the use of an external LNA. Since LNA1 is self contained and includes independent bias circuitry, it can be powered down simply by not connecting the respective supply pin or tying it to ground. Some considerations apply to optimize performance when using an external LNA. Generally the UAA1570HL has been optimized with approximately 15 dB of gain in the first LNA. To prevent degradation of the system noise figure or dynamic range in subsequent system functions, such as the first mixer or synthesizer, some limitations on the nominal effective gain and noise figure of external devices should be taken into account. The following values are not specified, since exceeding the recommended ranges may still result in adequate dynamic performance in some 1-bit GPS system applications. Note: LNA2 has to be powered-up under all circumstances, i.e. its supply pin has to be connected to VCC under all circumstances due to biasing constraints. Table 4 Operation with external LNAs MAXIMUM RECOMMENDED EXTERNAL GAIN INCLUDING CABLE AND FILTER LOSSES 10 dB 25 dB MINIMUM RECOMMENDED EXTERNAL GAIN INCLUDING CABLE AND FILTER LOSSES -3.5 dB 8 dB MAXIMUM RECOMMENDED EXTERNAL NOISE FIGURE INCLUDING CABLE AND FILTER LOSSES 3.5 dB 4 dB
MODE
VCC(LNA1) VCC(LNA2)
INTERNAL CURRENT REDUCTION
Normal LNA1 replacement; note 1 LNA1/LNA2 replacement; notes 1 and 2 Notes
yes no
yes yes
- 6.5 mA
no
yes
41 dB
21 dB
4 dB
6.5 mA
1. The maximum external noise figure listed is that which will produce approximately a 1 dB degradation in system noise figure using the minimum recommended external gain. The maximum recommended external gain listed results in approximately 1 dB compression in the second mixer input with an in-band continuous wave jammer present (J/S = 35 dB) for nominal processed parts. 2. If a high gain external LNA is used, both LNA1 and LNA2 should be removed from the signal path. However, the LNA2 supply pin has to be connected to VCC to retain power to the first mixer.
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All ground pins are tied together. SYMBOL Vmax VCCA VDDD Tstg Tj Tamb Ves Note 1. Human body model: Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 74 UNIT K/W PARAMETER maximum voltage at any pin with respect to ground analog supply voltage digital supply voltage storage temperature junction temperature operating ambient temperature electrostatic handling VCCA = VDDD = 5 V note 1 CONDITIONS MIN. -0.5 -0.5 -0.5 -65 - -40 -2000 MAX. VCC + 0.5 V +5.5 +5.5 +150 150 +85 +2000 V V C C C V UNIT
11 DC CHARACTERISTICS Tamb = 25 2 C; test circuit see Fig.25; unless otherwise specified. SYMBOL Supplies ICCA(LNA1) LNA1 analog supply current VCCA = 2.7 V VCCA = 3 V VCCA = 5 V ICCA(LNA2) LNA2 analog supply current VCCA = 2.7 V VCCA = 3 V VCCA = 5 V ICCA(VCO) VCO analog supply current VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ibias(MX1) MX1 bias current VCCA = 2.7 V VCCA = 3 V VCCA = 5 V IO(MX1) MX1 output current (pins 17 and 18) VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ibias(MX2) MX2 bias current VCCA = 2.7 V VCCA = 3 V VCCA = 5 V 4.27 4.79 5.3 5 5.22 5.68 2.85 2.86 2.89 5.18 5.36 5.61 3.84 3.89 4.06 1.67 1.69 1.71 6.4 6.54 7.15 7.1 7.26 7.92 3.74 3.77 3.82 7.49 7.63 8.02 4.97 5.06 5.39 2.36 2.39 2.44 8.23 8.04 8.73 8.9 9.01 9.83 4.64 4.69 4.76 9.03 9.13 9.63 5.77 5.9 6.33 2.88 2.92 2.98 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999 May 10
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Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
SYMBOL IO(MX2) PARAMETER MX2 output current (pins 24 and 25) CONDITIONS VCCA = 2.7 V VCCA = 3 V VCCA = 5 V ICCA(LIM) LIM analog supply current VCCA = 2.7 V VCCA = 3 V VCCA = 5 V ICCA(PLL) PLL analog supply current VCCA = 2.7 V VCCA = 3 V VCCA = 5 V IDDDL LOW TTL digital current 5 k DC load; VDDD = 2.7 V 5 k DC load; VDDD = 3 V 5 k DC load; VDDD = 5 V IDDDH HIGH TTL digital current 5 k DC load; VDDD = 2.7 V 5 k DC load; VDDD = 3 V 5 k DC load; VDDD = 5 V Itot(wake) total current (wake state) VCCA = VDDD = 2.7 V VCCA = VDDD = 3 V VCCA = VDDD = 5 V Itot(sleep) total current (sleep state) VCCA = VDDD = 2.7 V VCCA = VDDD = 3 V VCCA = VDDD = 5 V Itot(synth) total current (synthesizer state) VCCA = VDDD = 2.7 V VCCA = VDDD = 3 V VCCA = VDDD = 5 V LNA1 and LNA2 VLNAIN DC operating point LNA1IN and LNA2IN (pins 45 and 3) VCCA = VDDD = 2.7 V VCCA = VDDD = 3 V VCCA = VDDD = 5 V VLNAOUT DC operating point LNA1OUT and LNA2OUT (pins 48 and 6) VCCA = VDDD = 2.7 V VCCA = VDDD = 3 V VCCA = VDDD = 5 V Reference input; pin 8 VREFIN DC operating point REFIN VCCA = 2.7 V VCCA = 3 V VCCA = 5 V 1.56 1.87 3.84 1.69 1.99 3.99 781 784 780 1.02 1.284 3.115 815 811 807 1.48 1.75 3.629 MIN. 2.41 2.46 2.53 0.9 0.97 1.39 11.45 11.67 12.2 2.9 3.02 3.49 0.13 0.2 0.47 46.36 47.54 51.04 - - - 14.36 14.98 15.72 TYP. 3.73 3.79 3.93 1.31 1.41 2 14.3 14.98 15.85 3.75 3.9 4.58 0.44 0.5 0.88 55.1 56.66 61.02 116.2 182.7 648.4 18.08 19.02 20.37
UAA1570HL
MAX. 4.56 4.62 4.81 1.53 1.65 2.34 16.07 17.06 18.13 4.6 4.77 5.94 0.65 0.7 1.15 62.3 64.26 69.33 223.5 323.2 900.9 20.4 21.54 23.27
UNIT mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A mA mA mA
856 843 839 1.71 1.983 3.886
mV mV mV V V V
1.87 2.15 4.19
V V V
1999 May 10
41
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
SYMBOL VCO; pin 10 VTANK DC operating point TANK VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Mixer 1; pin 14 VMX1IN DC operating point MX1IN VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Mixer 2; pins 21 and 22 VIF2IN DC operating point IF2INN and IF2INP VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Limiter VBFC DC operating point BFCN and BFCP (pins 27 and 30) VCCA = 2.7 V VCCA = 3 V VCCA = 5 V VLIMIN DC operating point LIMINN and LIMINP (pins 28 and 29) VCCA = 2.7 V VCCA = 3 V VCCA = 5 V SIGN bit output (TTL); pin 34 VOL(SIGN) LOW-level DC operating point output SIGN 5 k DC load; VCCA = 2.7 V 5 k DC load; VCCA = 3 V 5 k DC load; VCCA = 5 V VOH(SIGN) HIGH-level DC operating point output SIGN 5 k DC load; VCCA = 2.7 V 5 k DC load; VCCA = 3 V 5 k DC load; VCCA = 5 V SCLK input (CMOS to ECL); pin 37 Vth(SCLK) DC operating point SCLK threshold [0.5 x VCCA(LIM) (pin 31)] VCCA = VDDD = 2.7 V VCCA = VDDD = 3 V VCCA = VDDD = 5 V VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Icp(max) maximum current sinked or sourced by the charge pump VCCA = 2.7 V VCCA = 3 V VCCA = 5 V 1.329 1.479 2.478 1.341 1.491 2.499 - - - 240 240 240 45 42 - 1.589 1.794 3.566 130.6 127 71.8 1.876 2.168 4.1 1.276 1.578 3.579 1.276 1.578 3.579 1.696 1.998 3.999 1.696 1.998 3.999 939 937 936 983 981 980 800 797 792 818 814 810 1.825 1.822 1.818 1.918 1.916 1.918 PARAMETER CONDITIONS MIN. TYP.
UAA1570HL
MAX.
UNIT
2.01 2.011 2.018
V V V
846 839 837
mV mV mV
1011 1009 1008
mV mV mV
1.831 2.133 4.134 1.831 2.133 4.134
V V V V V V
160.8 157 - 1.956 2.273 4.251
mV mV mV V V V
1.353 1.503 2.519
V V V
COMP; pin 40 VO(COMP) charge pump output voltage swing 0.2 0.2 0.2 - - - 2.1 2.4 4.4 - - - V V V A A A
1999 May 10
42
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
12 AC CHARACTERISTICS Tamb = 25 2 C; default frequency plan; test circuit see Fig.25; unless otherwise specified. S-parameters given below (S11, S22 and S12) are design goals which should be achieved in order to reach the other given values. They are depending on application. SYMBOL System performance FRX S LNA 1; note 3 S21LNA1 power gain 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V S11LNA1 input reflection coefficient 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V S12LNA1 reverse isolation 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V S22LNA1 output reflection coefficient 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V IP3LNA1 3rd-order input intercept point 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V IP2LNA1 2nd-order input intercept point 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V - - - 7.7 7.9 8.6 - - - dBm dBm dBm -17 -16.8 -16.6 -13.4 -13.2 -12.6 - - - dBm dBm dBm - - - -21.2 -18 -10.8 -12.7 -13.4 -8.7 dB dB dB - - - -38.9 -38 -35.6 -29.9 -29 -26.6 dB dB dB - - - -18 -18 -18 -16.3 -16.2 -16.2 dB dB dB 12.3 12.4 12.9 15.4 15.7 16.6 18.1 18.5 19.7 dB dB dB receiver noise figure (LNA1 input to SIGN bit output) sensitivity f = 1.57542 GHz; VCCA = 3 V; note 1 -3 dB; note 2 3.8 -103 4.5 -106 5.2 -109 dB dBm PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999 May 10
43
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
SYMBOL CP-1dB(LNA1) PARAMETER -1 dB input compression point CONDITIONS 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V FLNA1 noise figure LNA1 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V LNA 2; note 3 S21LNA2 power gain 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V S11LNA2 input reflection coefficient 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V S12LNA2 reverse isolation 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V S22LNA2 output reflection coefficient 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V IP3LNA2 3rd-order input intercept point 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V IP2LNA2 2nd-order input intercept point 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V - - - 7.7 7.9 8.6 -28.6 -16.9 -16.3 -13.5 -12.8 -12 - - - -18.4 -18 -15.7 - - - -35.8 -34.9 -32.5 - - - -18.5 -18 -17.1 11.4 12.1 11.6 14.8 15.3 15.9 - - - 3.6 3.6 3.6 -26.6 -26.6 -28.2 -22.2 -22.2 -22 MIN. TYP.
UAA1570HL
MAX.
UNIT
- - -
dBm dBm dBm
4.7 4.3 4.2
dB dB dB
18.2 18.5 20.3
dB dB dB
-14.2 -13.5 -12.6
dB dB dB
-26.8 -25.9 -23.5
dB dB dB
-14.9 -15 -14.1
dB dB dB
- - -
dBm dBm dBm
- - -
dBm dBm dBm
1999 May 10
44
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
SYMBOL CP-1dB(LNA2) PARAMETER -1 dB input compression point CONDITIONS 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V FLNA2 noise figure LNA2 50 matched input and output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Mixer 1 Y21MX1 conversion transconductance 50 matched input and 800 matched output; note 4 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Gconv(v) voltage conversion gain 50 matched input and output; note 5 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Gconv(p) power conversion gain 50 matched input and 800 matched output; note 6 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V S11MX1 input reflection coefficient 50 matched input and 800 matched output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V CP-1dB(MX1) -1 dB input compression point 50 matched input and 800 matched output; note 6 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V -29.7 -31.2 -31 -25.4 -25.4 -25.4 - - - -17.8 -18 -18.9 14.5 14.8 16.2 17.7 18 18.9 23.9 24.3 25.7 27.1 27.5 28.4 0.032 0.0334 0.0403 0.0513 0.0531 0.0593 - - - 3.7 3.7 3.8 -28.1 -27.1 -26.6 -22.4 -22.6 -22.2 MIN. TYP.
UAA1570HL
MAX.
UNIT
- - -
dBm dBm dBm
4.4 4.3 6.3
dB dB dB
0.0813 0.0837 0.0889
A/V A/V A/V
32.1 32.4 32.7
dBV dBV dBV
22.6 22.9 23.2
dB dB dB
-15.9 -16.2 -16.6
dB dB dB
- - -
dBm dBm dBm
1999 May 10
45
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
SYMBOL FDSB(MX1) PARAMETER double-side band noise figure MX1 CONDITIONS 50 matched input and 800 matched output; note 6 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Mixer 2 Y21MX2 conversion transconductance 800 matched input and output; note 7 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Gconv(v) voltage conversion gain 800 matched input and output; note 8 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Gconv(p) power conversion gain 800 matched input and output; note 9 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ri(dif) differential input resistance note 10 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ci(dif) differential input capacitance note 10 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V CP-1dB(MX2)(M) -1 dB differential input compression point 800 matched input and output (peak value); note 9 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V FDSB(MX2) double-side band noise figure MX2 800 matched input and output; note 9 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V - - - 4.8 4.8 4.8 50 44 44.6 67.2 67.2 67.2 0.9 0.9 0.9 1 1 1 1.6 1.6 1.6 2.05 2.05 2.05 17.8 17.8 18 21.4 21.4 21.6 17.8 17.8 18 21.4 21.4 21.6 0.0252 0.0171 0.0258 0.0293 0.0294 0.03 - - - 12.8 12 10 MIN. TYP.
UAA1570HL
MAX.
UNIT
16.8 15.8 12.7
dB dB dB
0.0344 0.0438 0.0352
A/V A/V A/V
25.5 25.6 25.8
dBV dBV dBV
25.6 25.6 25.8 2.45 2.45 2.45 1.1 1.1 1.1
dB dB dB k k k pF pF pF
84.3 90.3 89.8
mV mV mV
6.1 5.5 7
dB dB dB
1999 May 10
46
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
SYMBOL Limiter Gv(lim) small signal limiting voltage gain 800 matched limiter input to internal limiter output VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ri(dif) differential input resistance note 10 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ci(dif) Flim differential input capacitance note 10 limiter noise figure referred to 800 800 matched source; note 11 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Slim(M) differential limiter sensitivity 800 matched source (peak value); note 11 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V SCLK (sample clock conditioning) Gv(SCLK) small signal voltage gain 50 terminated SCLK input to internal DFF clock input VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ri(SCLK) input resistance note 10 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ci(SCLK) input capacitance note 10 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V BSCLK small signal bandwidth 50 terminated source - - - - 0.86 0.84 0.74 42.5 - - - 23.2 23.4 23.7 - - - 38.9 39.0 39.6 46 68.8 46 100 100 100 - 12.0 - 16.5 15.0 11.0 4.10 4.11 4.15 0.25 4.85 4.87 4.92 0.28 - 61.8 - 64.5 65.7 66.0 PARAMETER CONDITIONS MIN. TYP.
UAA1570HL
MAX.
UNIT
- 69.5 - 6.67 6.69 6.76 0.31
dB dB dB k k k pF
- 17.0 -
dB dB dB
154 131.2 154
V V V
- - - - - - - - - -
dB dB dB k k k pF pF pF MHz
1999 May 10
47
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
SYMBOL SSCLK(M) PARAMETER SCLK sensitivity CONDITIONS 50 terminated source (peak value) VCCA = 2.7 V VCCA = 3 V VCCA = 5 V VCO Ri(1.4GHz)(seqn) series equivalent negative resistance at 1.4 GHz (only for reference) series equivalent capacitance at 1.4 GHz (only for reference) VCCA = 2.7 V VCCA = 3 V VCCA = 5 V VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ri(1.5GHz)(seqn) series equivalent negative resistance at 1.5 GHz (only for reference) series equivalent capacitance at 1.5 GHz (only for reference) VCCA = 2.7 V VCCA = 3 V VCCA = 5 V VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Ri(1.6GHz)(seqn) series equivalent negative resistance at 1.6 GHz (only for reference) series equivalent capacitance at 1.6 GHz (only for reference) VCCA = 2.7 V VCCA = 3 V VCCA = 5 V VCCA = 2.7 V VCCA = 3 V VCCA = 5 V VVCO(M) first LO signal level (peak value) note 12 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V KVCO(av) average VCO gain in typical application VCCA = 2.7 V VCCA = 3 V VCCA = 5 V Synthesizer fi(ref) Pi(ref) Zi(ref) PN10kHz reference input frequency reference input level reference input impedance PLL phase noise 10 kHz offset note 12 VCCA = 2.7 V VCCA = 3 V VCCA = 5 V - - - 72 72 72 relative to 50 1 -32.27 - 14.4 +5 20 - - - - 61.7 - - - - 84.84 96.62 67.15 - - - - - - - - - - - - - - - - - - -14.5 -14.7 -15.0 2.61 2.56 2.47 -12.1 -12.3 -12.6 3.06 3.00 2.90 -10.4 -10.7 -11.0 2.94 2.89 2.78 10 10 10 - - - MIN. TYP.
UAA1570HL
MAX.
UNIT
- - - - - - - - - - - - - - - - - - - - - 0.9 0.9 0.9 - 101 -
mV mV mV pF pF pF pF pF pF pF pF pF V V V MHz/V MHz/V MHz/V
Ci(1.4GHz)(seq)
Ci(1.5GHz)(seq)
Ci(1.6GHz)(seq)
35 +9.75 - - - -
MHz dBm k dBc/Hz dBc/Hz dBc/Hz
1999 May 10
48
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
Notes
UAA1570HL
1. The noise figure of the GPS application board is estimated from the -3 dB sensitivity testing by substitution using a 10 dB external LNA with a noise figure of less than 2 dB. 2. The sensitivity of the GPS application board is measured by recording the RF level required to observe a 3 dB drop in the sampled L1 signal, after sampling to 1.32 MHz product [3.48 MHz(IF2) - 4.8 MHz (fsample)] in the SIGN bit output. 3. At L1 (1.57542 GHz) with a -35 dBm input with matching components tuned at 3 V at Tamb = 25 C. 4. From the matched single-ended RF mixer preamplifier input to the differential IF output of MX1. 5. From the matched single-ended RF mixer preamplifier input to the differential IF output of MX1 across an equivalent 400 loading of an 800 termination and transformer differential load (4 : 1 ratio to a 50 measurement termination). 6. From the matched single-ended RF input to the differential IF output of MX1 into an equivalent 400 differential load. Half of the delivered conversion gain power is delivered to an 800 termination, with the remaining power transformed (z-ratio 16 : 1) down and delivered to a 50 termination. The available tabulated power is 3 dB higher than the power delivered to the 50 termination. 7. From the differential transformer matched RF input to the differential IF output of MX2. 8. From the differential transformer matched RF input to the differential IF output of MX2 across an equivalent 400 loading of an 800 termination and transformer differential load (4 : 1 ratio to a 50 measurement termination). 9. From the differential transformer matched RF input to the differential IF output of MX2 into an equivalent 400 differential load. Half of the delivered conversion gain power is delivered to an 800 termination, with the remaining power transformed (z-ratio 16 : 1) down and delivered to a 50 termination. The available tabulated power is 3 dB higher than the power delivered to the 50 termination. The back-to-back 50 : 800 : 800 : 50 response characteristics of mini circuits RF transformer T16-6T are provided in Fig.11. 10. Simulated values without external pin strays. 11. Due to test time constraints the sensitivity of the limiter is measured indirectly in the current ATE test definition. Bench characterization using a 1 : 16 ratio transformer established -3 dB limiting sensitivity at 100 V (peak value) across the 800 terminated transformer output at the limiter input. This sensitivity is not due to gain limitations, but rather intrinsic complex broadband noise characteristics over an estimated 800 MHz equivalent sampled spectral bandwidth. However, the measured -82 dBm sensitivity of the device in an 800 operating environment defines the minimum level which can be detected in the sampling quantizer. The ATE test method results perform about 8.2 dBV better than bench characterization using conventional -3 dB limiting. The specification results represent the ATE results degraded by 8.2 dB. The limiter noise figure test is being degraded by 800 transformer termination loss. Only a weak and remote correlation exist between highly non-linear noise figure measurements made on a time sampled quantizer output and linear simulation results. 12. The peak VCO tank swing and phase noise are measured in the default application board. With high Q resonators the peak voltage swing at the resonator pin should be limited to <0.8 V (peak value). A de-biasing resistor can be added from the TANK pin to ground.
1999 May 10
49
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book, full pagewidth
TRACE
TRACE
1999 May 10 50
J5 3WB VCC
13 CHARACTERIZATION TEST CIRCUIT
Philips Semiconductors
Global Positioning System (GPS) front-end receiver circuit
LNA1IN J13 SMA
TRACE X
L16 5.6 nH C52
TRACE C51 1.2 pF Y
TRACE Z L15 33 nH
R18 Vtune
C46 C45 0.1 F C44 C42 0.01 F C43 R17 51 SCLK J12 SMA AGND
5.1 k 0.047 F C47 100 pF
LNA1OUT J14 SMA
TRACE X
L17 4.7 nH C53 1.2 pF
TRACE Y C50
TRACE Z
C49 0.01 F
C48 100 pF
48 L1 33 nH 1 C1 0.01 F C2 100 pF 2 LNA2IN J1 SMA TRACE X L2 4.7 nH C3 TRACE C4 1.5 pF Y TRACE 3 Z
47
46
45
44
43
42
41
40
39
38
37 36
100 pF AGND L14 220 nH 35 C39 100 pF 34 5.1 k L13 VDDD POST C41 2.2 F C40 0.01 F R16 SIGN J11 SMA
4
33
33 nH DATA
5 LNA2OUT J2 SMA TRACE X C6 1.2 pF L3 0 nH J4 JUMPER C7 R1 51 8 0.01 F 9 L4 33 nH C9 0.01 F C8 100 pF 10 R2 G VCC 10 C11 100 nF L5 5.6 nH Vtune R5 2.4 k C12 4.7 pF Y C100 STROBE DATA CLOCK C56 10 pF C13 SELECT X MIXIN J6 SMA TRACE SMV1204-133 R3 10 k C14 1.0 pF L6 3.9 nH 12 13 14 15 C15 100 pF C16 0.01 F R6 820 16 17 C17 18 19 20 C19 100 pF C20 0.01 F L9 0 nH L7 33 nH L10 220 nH L11 L8 220 nH T1 T16-6T R7 C18 IF1P J7 SMA C21 1 nF C22 0.01 F 220 nH C23 100 pF C25 1 nF R8 1.2 k C24 T2 T16-6T 21 22 23 24 TCXO Out G Johnstech International jti-TS048QFP07-0.50 Giga 3 socket C5 TRACE Y TRACE 6 Z CLOCK 7
32
L12 31
UAA1570HL
30 C35 29 0.1 F
C36 0.01 F R13 820
C37 100 pF
220 nH C38 0.01 F R14 LIMINP J10 SMA
EXT REFIN J3 SMA
C32 28 0.1 F C31 0.01 F 26
C33 T4 T16-6T
R15
C34
R12
27
11
25
TXS1134M C10 15 pF
Z
R9 STROBE 820 MIX2IN J9 SMA
R4 2.4 k VR1 R19 100 R20 100 R21 100
C30
R11
LENGTH (MILS) C28 LNA1IN LNA1OUT LNA2IN C26 0.01 F C27 100 pF R10 LNA2OUT T3 T16-6T MIX1IN
X
Y (50 ) 894 568 932 1005 311
(VIA) 125 125 125 125 125
Z (62 ) 75 45 89 85
C54 10 pF
C55 10 pF
1500 1261 586 345 1565
UAA1570HL
69
Product specification
C57 2.2 F
C29
IF2P J8 SMA
4 LAYER FR4 BOARD 125 MILS THICK 50 COPLANAR MICROSTRIP H = 12 MILS W = 20 MILS G = 10 MILS 62 COPLANAR MICROSTRIP H = 12 MILS W = 12 MILS G = 11.5 MILS
MHB288
Fig.25 Characterization test circuit.
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
Table 5 Component list for Fig.25
UAA1570HL
COMPONENT CHARACTERISTICS COMPONENT VALUE C1, C7, C9, C16, C20, C22, C26, C31, C36, C38, C40, C42 and C49 C2, C8, C15, C19, C23, C27, C37, C39, C43, C47 and C48 C3, C5, C50 and C100 C4 C6, C51 and C53 C10 C11(1) C12 C13 C14 C17, C18, C24, C28, C29 and C30 C21 and C25 C32, C35 and C45 C33, C34 and C44 C41 and C46 C52 C54 to R2(4) R3 R4 and R5 R6, R9 and R13 R7, R10 and R11 R8 R12 R14 R15 R16(5) R18 R19, R20 and R21 L1, L4, L7, L13 and L15 L2 and L17 L3 L5 L6 L8, L10, L11, L12 and L14 L9 1999 May 10 51 C56(3) R1 and R17 C57(2) 0.01 F 100 pF not loaded 1.5 pF 1.2 pF 15 pF not loaded 4.7 pF short 1.0 pF not loaded 1000 pF 0.1 F not loaded 2.2 F 0.047 F not loaded 10 pF 51 not loaded 10 k 2.4 k 820 not loaded 1.2 k not loaded not loaded not loaded 5.1 k 5.1 k 100 33 nH 4.7 nH short 5.6 nH 3.9 nH 220 nH short TOLERANCE 10% 5% - 0.25 pF 0.25 pF 5% - 0.25 pF - 0.25 pF - 5% 10% - 10% 10% - 5% 1% - 1% 1% 1% - 1% - - - 1% 1% 5% 10% 0.3 nH - 0.3 nH 0.3 nH 10% - PACKAGE 603 603 - 805 805 603 - 603 - 805 - 603 603 - - 603 - 603 603 - 603 603 603 - 603 - - - 603 603 603 805 (Coilcraft) 805 (Toko) - 603 (Toko) 805 (Toko) 805 (Coilcraft) -
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
COMPONENT CHARACTERISTICS COMPONENT VALUE L16 VR1 T1 to T4 TCXO(6) Notes 1. 0.1 F, 10%, 603 if used. 2. 16 V voltage rating. 3. For default frequency plan: short. 4. 10 , 5%, 603 if used. 5. For AC characterization, terminate with 50 to ground and use a 50 input test instrument. 6. TXS1134MTEW if used. 5.6 nH TOLERANCE 0.3 nH PACKAGE 805 (Toko)
SMV1204-133 low capacitance varactor (Alpha) transformer Mini circuits T16-6T-KK81/W38, 16 : 1 impedance ratio not loaded - -
1999 May 10
52
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
14 DEFAULT APPLICATION AND DEMONSTRATION BOARD
UAA1570HL
handbook, full pagewidth
VRTC VBB BATT_ON BATT_OFF
VRTC VBB BATT_ON BATT_OFF
RCLK SCLK SIGN RFDATA RFCLK RFLE
RCLK SCLK SIGN RFDATA RFCLK RFLE RF FRONT-END
MHB492
POWER SUPPLY
DIGITAL PROCESSOR
Fig.26 Overall schematic.
1999 May 10
53
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
VCC R207 470 U206 ZM33064 VCC VCC 2 1 GND GND GND TP216 C207 GND 10 pF TP229 C208 GND 10 pF C205 GND 27 pF Y202 32.678 kHz R201 0 TP230 VCC TP207 R202 10 M Y201 30 MHz R203 180 TP211 TP210 TP209 TP208 VCC TP214 R204 1 M TP213 TP212 TP217 PWRFAIL PWRDN TP215 XTAL1 XTAL2 XTAL3 XTAL4 TxD0 RxD0 TxD1 RxD1 TP4 n.c. n.c. n.c. TEST1 TEST2 JP202 GND 1 2 3 4 5 6 7 8 9 10 HEADER 10 VCC TP2 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO7 GPIO6 GPIO5 74 52 41 14 15 76 75 83 84 81 82 4 8 9 97 99 100 42 96 95 94 88 87 5 6 7 73 47 46 45 40 39 36 35 34 33 32 29 28 27 24 23 22 21 20 19 18 11 10 70 69 68 67 64 63 62 59 58 57 56 55 54 53 49 48 89 90 91 16 25 37 51 61 86 12 30 66 72 80 44 TP1 PMCS DMCS RD WRL WRH A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RFDAT RFCLK RFLE VCC(P) VCC(P) VCC(P) VCC(P) VCC(P) VCC(P) TP222 TP223 TP224 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 GND TP218 TP225 TP219 TP220 TP221 C209 10 F (6.3 V) 3 OUT VCC 2 1 GND R206 10 k R205 10 k U204 D201 BAS16 U207 ZM33164 3 OUT VCC VCC
C206 GND 27 pF
JP201 JMP3
GND
SAA1575HL
TP201 TP202 TP203 VCC T1S_OUT BATT_ON BATT_OFF SIGN
RCLK SCLK IF1 IF2 TP3
98 1 93 92 3
RCLK SCLK SIGN BATT_ON BATT_OFF
RCLK SCLK SIGN BATT_ON BATT_OFF
TP204 TP205 TP206 VCC
T1S PWRB
2 77
PWRM 78 RSTIME 43 VSS 13 VSS 17 VSS 26 VSS 31 VSS 38 VSS 50 VSS 60 VSS 65 VSS 71 VSS 79 VSS 85
VCC(core) VDD1 VCC(core) VDD2 VCC(core) VDD3 VCC(R) VCC(B) VRTC1 VBB1
GND
VDD1
VDD2
VDD3
VBB1
VRTC1
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC
C210 33 nF
C211 33 nF
C212 33 nF
C213 33 nF
C214 33 nF
C215 33 nF
C216 33 nF
C217 33 nF
C218 33 nF
C219 33 nF
C220 33 nF
C221 33 nF
C222 33 nF
C223 33 nF
C224 33 nF
MHB290
GND
Fig.27 Baseband circuitry (continued in Fig.28).
1999 May 10
54
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
J201 5 9 4 8 3 7 2 6 1 DB9
C201 100 nF (50 V)
C202 U201 100 nF (50 V) C1+ 12 C1- 14 C2+ 15 C2- 16 T1OUT 2 T2OUT 3 T3OUT 1 T4OUT 28 /R1IN /R2IN /R3IN /R4IN /R5IN 9 4 27 23 18 V+ V- C203 13 17 100 nF (50 V) C204 /T1IN /T2IN /T3IN /T4IN R1OUT R2OUT R3OUT R4OUT R5OUT EN /SHDN TXD0 TXD1 100 nF (50 V) GND VCC RXD0 RXD1 VCC
7 6 20 21 8 5 26 22 19 24 25
J202 5 9 4 8 3 7 2 6 1 DB9 GND VCC
U202 VCC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 /DMCS /RD /WRH A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 /CE /OE /WE 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 20 22 27 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
MAX213EAI
RFD
R224 220
RFDATA RFDATA R210 open TP226
28 14
VBB GND
RFC
R223 220
RFCLK RFCLK R209 open TP227
M5M5256BVP
U203 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 /DMCS /RD /WRL C225 47 F (6.3 V) GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 /CE /OE /WE 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 20 22 27 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
RFL
R222 220
RFLE RFLE R208 open TP228
GND
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VDD1 VDD2 VDD3 R213 1 R212 1 R211 1 VDD VRTC R216 1 VCC
28 14
VBB GND
M5M5256BVP
U205 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VCC /PMCS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 /CE /OE 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 41 42 44 3 22 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 12 34 2 43 27C202 GND
MHB291
C226 47 F (6.3 V) GND
VRTC1 VBB1
VBB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D11 D12 D13 D14 D15 D16 GND VPP /PGM VCC
Fig.28 Baseband circuitry (continued from Fig.27).
1999 May 10
55
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
VRF handbook, full pagewidth
VRF
L306 180 nH R322 12 k M1BIASP
L307 180 nH
R324 open
C345 1 F (16 V) AGND
C308 open
L308 27 H R323
L309 open
R304 0 C343 4700 pF
AGND
2.21 k M2BIASP M2BIASN VRF R317 10 k VRF X301 TCO-987Q R326 10 k 7 R327 10 k 1 4 6 8 5 C344 10 nF (50 V) AGND R320 2.21 k R321 2.21 k R318 10 k AGND AGND AGND C342 4700 pF R314 2.7 k R315 2.7 k C338 L305 6.8 nH AGND REFIN P39GND COMP P12GND TANK DATA CLOCK STROBE SIGN R313 C348 R312 3.9 k AGND C336 10 pF C337 33 nF SCLK BFCP LIMINP LIMINN BFCN VCCA(LNA1) VCCA(LNA2) VCCA(PLL) VCCA(LIM) 2 VRF VCCA
M1BIASN
+ -
1 8 6 45
U302 MAX903ESA 7 RCLK
3
AGND DGND
8 39 40 12 10 32 7 23 34 37 30 29 28 27 43 1 36 31
C341 3.9 nF R319 20 k
C340 150 pF
AGND
3 RFDATA RFCLK
15 pF
D301 SMV1233-004
2
1 AGND
RFLE SIGN SCLK 6.8 k
R316 10 k AGND
C339 4.7 pF AGND
UAA1570HL
VCC C333 33 nF
VRF C346 33 nF
C335 33 nF 33 nF C334 33 nF C347
AGND
open C332 C330 33 nF 33 nF C331 33 nF C329 33 nF DGND AGND R310 18 R311 18 VRF R309 VDDD VCCD open R325
MHB292
VCCA(MX2) 19 VCCA(MX1P) P41GND VCCA(VCO) VDDD 16 41 9 33
1
Fig.29 RF front-end circuit (continued in Fig.30).
1999 May 10
56
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
L = 900 mils W = 8.8 mils R303 VRF 9 R307 9 C328 33 nF (50 V) AGND C327 10 pF (50 V) AGND C325 L = 315 mils (8.1 mm) W = 6 mils 100 C324 1.5 pF AGND 27 pF L = 367 mils (9.3 mm) W = 33 mils 50 C326 0.56 pF AGND AGND J301 SMA-F L = 1020 mils W = 8.8 mils
L = 355 mils (9 mm) W = 6 mils 100 I/O C321 0.27 pF 45 48 3 6 14 17 18 21 22 24 25 LNA1IN LNA1OUT LNA2IN LNA2OUT MX1IN IF1P IF1N IF2INN IF2INP IF2P IF2N C315 C317 8.2 pF L303 330 nH C316 M1BIASN 6.8 pF C314 36 pF C318 8.2 pF C320 1.2 pF AGND C306 0.47 pF AGND L = 386 mils (10 mm) W = 6 mils 100 L = 412 mils (10.5 mm) W = 6 mils 100 L = 217 mils (5.5 mm) W = 33 mils 50 I/O AGND AGND L = 286 mils (7.3 mm) W = 6 mils 100 C307 open 2
BPF301 MF1012S-1 5 1 3 4 6 I/O C323 2.2 pF AGND
AGND
BPF302 MF1012S-1 2 1 3 4 6 5 I/O C322 2.2 pF AGND
AGND
UAA1570HL
44 46 47 5 4 2 42 38 26 20 13 15 11 35 LNA1GND1 BIASGND1 LNA1GND2 LNA2GND2 BIASGND2 LNA2GND1 P42GND PLLGND LIMGND MX2GND MXPGND MX1GND M2BIASP VCOGND DGND M2BIASN 47 pF C301 82 pF C304 open C309 18 pF L301 22 H R301 0 47 pF L302 22 H C310 68 pF 1000 pF R305 820 C312 LIMINN 1000 pF R302 0 AGND
MHB293
M1BIASP
6.8 pF C313 36 pF
L304 330 nH
C319 39 pF
R306 909
C305 open AGND
C302
C303
C311 LIMINP
DGND AGND
Fig.30 RF front-end circuit (continued from Fig.29).
1999 May 10
57
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
PL101 JMP3
D101 LL4007 U101 IN ADJ 3 2 1 LM317T(3) OUT R118 270 D102 LL4007 C102 1 nF C101 1 nF C107 1 F (20 V) GND C109 10 F (10 V) GND R119 820 GND GND R101 1 VCC TP101 VCC
C108 22 F (5 V)
GND
GND
GND
D103 LL4007 U102 IN ADJ 3 2 1 LM317T(3) OUT R120 240 D104 LL4007 C104 1 nF R102 1 VRF VBAT R117 1 k B101 3V 170 mAh GND TP102 VRF
C103 1 nF
C115 1 F (20 V)
C116 10 F (10 V)
JP101 R121 390 1 2 R122 3 V/5 V 330
C110 22 F (5 V)
VCC VCC R111 1 M R113 47 k R109 470 R110 BATT_OFF 1 M C112 470 nF R114 GND GND GND 47 k V101 BC848 VDD V104 BC858 V102 BC848 R112 1 M V103 BC858
VBAT V105 BC858 C114 22 F (6.3 V) GND VBAT V106 BC858 C113 22 F (6.3 V) GND R116 10 M VRTC R115 BATT_ON 10 M VBB
U103 LP2951CM VCC IN SD FB 8 3 7 4 C105 100 nF 1 5 2 6 GND R108 12 k GND GND GND GND GND OUT ERR SNSE VTAP R106 18 k C106 100 nF
TP103 VDD(IN) R103 1 VDD
C111 10 F (6.3 V)
GND
MHB294
Fig.31 Power supply circuitry.
1999 May 10
58
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
The GPS system application demonstration board consists of 6 layers with a total final thickness of 1.5 mm. The PCB material is FR4.
handbook, full pagewidth
U101 + R118 R119 C102 R101 1 C109 VDD IN R103 C107 C101 VCC IN
3 V/170 mAh
RS232 #1 C223
PL101
GPS DEMO BOARD Version 1.3
U205
U102 C116
C115 C103 R120 R121 R102 RFDATA RFCLK RFLE R208 R222 R209 R223 R210 R224
R216 C220 R211 C213
VRF IN X301 R326
+ JP101 R122 C327 R303 C328 R307
C212 C214
SIGN DAC RCLK SCLK T1S_OUT C210
BATT_ON RXD0 U204
DMCS PWRFAIL
BATT_OFF U201 RXD1 TXD1 TXD0
RS232 #0 R205
R327
R213 R212
C215 C324 C325 C341 U301 R319 C216 C329 C311 R302 L302 R305 R301 C310 C303 R325 1 R309 JP202 C211 C217 PMCS
C219 C213 WRH WRL RD PWRDN C209
C326
* R314
C334 C320 L305
C306 C338 R316 BPF302
*
D301
R306
C312 C301 C319 C302 R310 L304 C317 C314
L301 C309
PTEST
R206 U206 GND/VCC 1
R311 C322 C318 C305 L303
U207
MHB295
Fig.32 Demonstration board top layer plus components (real size 88.9 mm x 88.9 mm).
1999 May 10
59
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
MHB296
Fig.33 Demonstration board 2nd layer.
1999 May 10
60
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
MHB297
Fig.34 Demonstration board 3rd layer.
1999 May 10
61
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
MHB298
Fig.35 Demonstration board 4th layer.
1999 May 10
62
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
MHB299
Fig.36 Demonstration board 5th layer.
1999 May 10
63
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
handbook, full pagewidth
U101 + R118 R119 C102 R101 1 C109 VDD IN R103 C107 C101 VCC IN
3 V/170 mAh
RS232 #1 C223
PL101
GPS DEMO BOARD Version 1.3
U205
U102 C116
C115 C103 R120 R121 R102 RFDATA RFCLK RFLE R208 R222 R209 R223 R210 R224
R216 C220 R211 C213
VRF IN X301 R326
+ JP101 R122 C327 R303 C328 R307
C212 C214
SIGN DAC RCLK SCLK T1S_OUT C210
BATT_ON RXD0 U204
DMCS PWRFAIL
BATT_OFF U201 RXD1 TXD1 TXD0
RS232 #0 R205
R327
R213 R212
C215 C324 C325 C341 U301 R319 C216 C329 C311 R302 L302 R305 R301 C310 C303 R325 1 R309 JP202 C211 C217 PMCS
C219 C213 WRH WRL RD PWRDN C209
C326
* R314
C334 C320 L305
C306 C338 R316 BPF302
*
D301
R306
C312 C301 C319 C302 R310 L304 C317 C314
L301 C309
PTEST
R206 U206 GND/VCC 1
R311 C322 C318 C305 L303
U207
MHB300
Fig.37 Demonstration board bottom layer plus components.
1999 May 10
64
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
Table 6 Component list for GPS demonstration board
UAA1570HL
COMPONENT CHARACTERISTICS COMPONENT B101 C101 to C104, C311 and C312 C105, C106, C201 to C204 C107 and C115 C108 and C110 C109 and C116 C111 and C209 C112 C113 and C114 C205, C206 and C325 C207, C208, C327 and C348 C210 to C224, C328 to C337 and C346 C225 and C226 C301 C302 and C303 C304, C305, C307, C308 and C347 C306 C309 C310 C313 and C314 C315 and C316 C317 and C318 C319 C320 C321 C322 and C323 C324 C326 C338 C339 C340 C341 C342 and C343 C344 C345 D101 to D104 D201 TYPE VALUE Lithium battery ceramic capacitor ceramic capacitor ceramic capacitor tantalum capacitor tantalum capacitor tantalum capacitor ceramic capacitor tantalum capacitor ceramic capacitor ceramic capacitor ceramic capacitor tantalum capacitor ceramic capacitor ceramic capacitor - ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor tantalum capacitor LL4007 diode, equivalent to 1N4007 SMD diode BAS 16 3 V/170 mAh 1 nF/50 V 100 nF/50 V 1 F/63 V 22 F/16 V 10 F/16 V 10 F/6.3 V 470 nF/63 V 22 F/6.3 V 27 pF/50 V 10 pF/50 V 33 nF/63 V 47 F/6.3 V 82 pF/50 V 47 pF/50 V not loaded 0.47 pF/50 V 18 pF/50 V 68 pF/50 V 36 pF/50 V 6.8 pF/50 V 8.2 pF/50 V 39 pF/50 V 1.2 pF/50 V 0.27 pF/50 V 2.2 pF/50 V 1.5 pF/50 V 0.56 pF/50 V 15 pF/50 V 4.7 pF/50 V 150 pF/50 V 3.9 nF/50 V 4.7 nF/50 V 10 nF/50 V 1 F/16 V - - TOLERANCE - 10% 20% 20% 20% 20% 20% 20% 20% 5% 5% 10% 20% 5% 5% - 0.1 pF 5% 5% 5% 0.25 pF 0.25 pF 5% 0.25 pF 0.1 pF 0.25 pF 0.25 pF 0.1 pF 5% 0.25 pF 5% 10% 5% 10% 20% - - PACKAGE CR1/3 603 603 1210 - - - 1206 - 603 603 603 - 603 603 - 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 - - SOT23
1999 May 10
65
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
COMPONENT CHARACTERISTICS COMPONENT D301 L301 and L302 L303 and L304 L305 L306 and L307 L308 L309 R101, R102, R103, R211, R212, R213, R216 and R325 R106 R108 and R322 R109 and R207 R110, R111, R112 and R204 R113 and R114 R115, R116 and R202 R117 R118 R119 and R305 R120 R121 R122 R201, R301, R302 and R304 R203 R205, R206, R316, R317, R318, R326 and R327 R208, R209, R210, R309 and R324 R222 to R224 R303 and R307 R306 R310 and R311 R312 R313 R314 and R315 R319 R320, R321 and R323 U101 and U102(1) U103 TYPE VALUE Alpha SMV1204-133 varactor SMD inductor SMD inductor SMD inductor SMD inductor SMD inductor - SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor - SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor LM317T voltage regulator LP2951CM voltage regulator (National) - 22 H 330 nH 6.8 nH 180 nH 27 H not loaded 1 18 k 12 k 470 1 M 47 k 10 M 1 k 270 820 240 390 330 0 180 10 k not loaded 220 9.1 910 18 3.9 k 6.8 k 2.7 k 20 k 2.2 k - - TOLERANCE - 5% 5% 5% 5% 5% - 5% 5% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% - 5% 1% - 5% 5% 1% 1% 1% 1% 1% 5% 1% - - PACKAGE SOT23 1008 1008 603 1008 1008 - 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 - 603 603 603 603 603 603 603 603 603 TO220 SO8
1999 May 10
66
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
UAA1570HL
COMPONENT CHARACTERISTICS COMPONENT U201 U202 and U203 TYPE VALUE MAX213EAIRS2312 transceiver (Maxim) SRAM M5M5256BFP-70LL 32k x 8 (Mitsubishi) 27C202 EPROM ZM33064 power monitor ZM33164 power monitor MAX903ESA comparator (Maxim) BC848 or BC847C NPN transistor BC858 PNP transistor TCXO TCO-987Q 30 MHz crystal, 16 pF load capacitance SMD crystal MF1012S-1 saw filter - - TOLERANCE - - PACKAGE SSOP28 SO28
U205 U206 U207 U302 V101 and V102 V103 to V106 X301 Y201 Y202 BPF301 and BPF302 Note
- - - - - - - - 32.768 kHz -
- - - - - - - - 30 ppm -
PLCC44 - - SO8 SOT23 SOT23 - - - -
1. With heat sink depending on input voltage.
1999 May 10
67
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
15 INTERNAL CIRCUITRY PIN VOLTAGE TYPICAL VALUES (V) VCC = 2.7 V 1 2 3 VCCA(LNA2) LNA2GND1 LNA2IN 2.7 0 0.815 5 0 0.807
3 2
UAA1570HL
PIN
SYMBOL
EQUIVALENT CIRCUIT WITHOUT ESD PROTECTION CIRCUITS
VCC = 5 V
MHB301
4 5 6
BIASGND2 LNA2GND2 LNA2OUT
0 0 1.48
0 0 3.629
6
5
MHB302
7
CLOCK
CMOS level
CMOS level
7
MHB303
8
REFIN
1.69
3.99
8
MHB304
9 10
VCCA(VCO) TANK
2.7 1.92
5 1.92
10
11
MHB305
1999 May 10
68
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
PIN VOLTAGE TYPICAL VALUES (V) VCC = 2.7 V 11 12 13 14 VCOGND P12GND MXPGND MX1IN 0 0 0 0.82 0 0 0 0.81
14 13
UAA1570HL
PIN
SYMBOL
EQUIVALENT CIRCUIT WITHOUT ESD PROTECTION CIRCUITS
VCC = 5 V
MHB306
15 16 17 18
MX1GND VCCA(MX1P) IF1P IF1N
0 2.7 2.7 2.7
0 5 5 5
17 18
MHB307
19 20 21 22
VCCA(MX2) MX2GND IF2INN IF2INP
2.7 0 0.983 0.983
5 0 0.98 0.98
21 22
MHB308
23
STROBE
CMOS level
CMOS level
23
MHB309
24 25
IF2P IF2N
2.7 2.7
5 5
24
25
MHB310
26
LIMGND
0
0
1999 May 10
69
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
PIN VOLTAGE TYPICAL VALUES (V) VCC = 2.7 V 27 28 29 30 31 32 BFCN LIMINN LIMINP BFCP VCCA(LIM) DATA 1.696 1.696 1.696 1.696 2.7 CMOS level VCC = 5 V 3.999 3.999 3.999 3.999 5 CMOS level
32 27 28 29
UAA1570HL
PIN
SYMBOL
EQUIVALENT CIRCUIT WITHOUT ESD PROTECTION CIRCUITS
30
MHB311
MHB312
33
VDDD
2.7 (independent of VCC level) TTL output
5 (independent of VCC level) TTL output
34
SIGN
34
MHB313
35 36 37
DGND VCCA(PLL) SCLK
0 2.7 1.34
0 5 2.5
37
MHB314
38 39
PLLGND P39GND
0 0
0 0
1999 May 10
70
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
PIN VOLTAGE TYPICAL VALUES (V) VCC = 2.7 V 40 COMP depends on VCO application VCC = 5 V depends on VCO application
40
UAA1570HL
PIN
SYMBOL
EQUIVALENT CIRCUIT WITHOUT ESD PROTECTION CIRCUITS
MHB315
41 42 43 44 45
P41GND P42GND VCCA(LNA1) LNA1GND1 LNA1IN
0 0 2.7 0 0.815
0 0 5 0 0.807
45 44
MHB316
46 47 48
BIASGND1 LNA1GND2 LNA1OUT
0 0 1.48
0 0 3.629
48
47
MHB317
1999 May 10
71
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
16 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
UAA1570HL
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 94-12-19 97-08-01
1999 May 10
72
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
17 SOLDERING 17.1 Introduction to soldering surface mount packages
UAA1570HL
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 17.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 17.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 May 10
73
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
17.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE HLQFP, HSQFP, HSOP, SMS PLCC(3), SQFP SSOP, TSSOP, VSO Notes SO LQFP, QFP, TQFP not suitable(2) suitable not not recommended(3)(4) recommended(5) not suitable suitable suitable suitable suitable suitable
UAA1570HL
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 18 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 19 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 May 10
74
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end receiver circuit
NOTES
UAA1570HL
1999 May 10
75
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 64
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
285002/00/01/pp76
Date of release: 1999 May 10
Document order number:
9397 750 04463

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