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TS4984
2 x 1W Stereo audio power amplifier with active low standby mode
Operating from VCC=2.2V to 5.5V 1W output power per channel @ VCC=5V, THD+N=1%, RL=8 10nA standby current 62dB PSRR @ 217Hz with grounded inputs High SNR: 100dB(A) typ. Near-zero pop & click Available in QFN16 4x4 mm, 0.5mm pitch, leadfree package
Pin Connections (top view)
TS4984IQ -- TQFN16 4x4mm
Description
The TS4984 has been designed for top of the class stereo audio applications. Thanks to its compact and power dissipation efficient QFN package, it suits various applications. With a BTL configuration, this Audio Power Amplifier is capable of delivering 1W per channel of continuous RMS output power into an 8 load @ 5V. An externally controlled standby mode control reduces the supply current to less than 10nA per channel. The device also features an internal thermal shutdown protection. The gain of each channel can be configured by external gain setting resistors.
IN- L IN+ L BYPASS L NC VO-L VO+L VCC1 VCC2
16 15 1 2 3 4 5 6
14
13 12 11 10 9 STBY BYPASS R IN+ R IN- R
7
8
GND1 GND2 VO+R VO-R
Applications
Cellular mobile phones Notebook computers & PDAs LCD monitors & TVs Portable audio devices
Order Codes
Part Number TS4984IQT Temperature Range -40, +85C Package QFN Packaging Tape & Reel Marking K984
January 2005
Revision 1
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TS4984 1 Typical Application
Typical Application
Figure 1 shows a schematic view of a typical audio amplification application using the TS4984. Table 1 describes the components used in this typical application. Figure 1: Typical application schematic
Cfeed-L
Rfeed-L 22k
VCC + 14 13
Cs 1u
U1
VCC1
1
Input L GND
Cin-L 100n
Rin-L 22k
IN-L
VO-L
16
2
IN+L
+
VCC
1 2 3
VCC2 -
12
Standby Bypass L
Bias AV = -1 +
Neg. Output L
VO+L
15
Pos. Output L
3 +
Cb 1u
Wire optional Internal connection Cin-R Input R GND 100n 22k
10
IN+R
+ VO-R
8
Rin-R
9
IN-R
-
AV = -1
11
Neg. Output R
VO+R
7
Pos. Output R
Bypass R
+
GND1
GND2
TS4984
5
Cfeed-R
Rfeed-R 22k
Table 1: External component descriptions
Components RIN L,R CIN L,R RFEED L,R CS CB AV L, R Functional Description Inverting input resistors which sets the closed loop gain in conjunction with Rfeed. These resistors also form a high pass filter with CIN (fc = 1 / (2 x Pi x RIN x CIN)). Input coupling capacitors which blocks the DC voltage at the amplifier input terminal. Feedback resistors which sets the closed loop gain in conjunction with RIN. Supply Bypass capacitor which provides power supply filtering. Bypass pin capacitor which provides half supply filtering. Closed loop gain in BTL configuration = 2 x (RFEED / RIN) on each channel.
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6
Absolute maximum ratings and operating conditions 2 Absolute maximum ratings and operating conditions
TS4984
Table 2: Key parameters and their absolute maximum ratings
Symbol VCC Vi Toper Tstg Tj Rthja Pd ESD ESD Supply voltage
2 1
Parameter
Value 6 GND to VCC -40 to + 85 -65 to +150 150 120 Internally Limited 2 200 200mA
Unit V V C C C C/W
Input Voltage Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Ambient QFN16 Power Dissipation Human Body Model3 Machine Model Latch-up Immunity
kV V
1) All voltages values are measured with respect to the ground pin 2) The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V 3) The voltage value is measured with respect from pin to supply
Table 3: Operating conditions
Symbol VCC VICM VSTB RL TSD RTHJA Supply Voltage Common Mode Input Voltage Range Standby Voltage Input: Device ON Device OFF Load Resistor Thermal Shutdown Temperature Thermal Resistance Junction to Ambient QFN161 QFN162 Parameter Value 2.2 to 5.5 1.2V to VCC 1.35 VSTB VCC GND VSTB 0.4 Unit V V V
4 1
150 45 85
M C C/W
ROUTGND Resistor Output to GND (VSTB = GND)
1) When mounted on a 4-layer PCB with via 2) When mounted on a 2 layer PCB
3/29
TS4984 3 Electrical characteristics
Electrical characteristics
Table 4: Electrical characteristics for VCC = +5V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Pout THD + N Supply Current No input signal, no load Standby Current 1 No input signal, Vstdby = GND, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, F = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 1Wrms, Av = 2, 20Hz F 20kHz, RL = 8 Power Supply Rejection Ratio2 RL = 8, Av = 2, Vripple = 200mVpp, Input Grounded F = 217Hz F = 1kHz Channel Separation, RL = 8 F = 1kHz F = 20Hz to 20kHz Wake-Up Time (Cb = 1F) Standby Time (Cb = 1F) Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8 65 15 1.5 0.8 Parameter Min. Typ. 7.4 10 Max. 12 1000 Unit mA nA mV W %
1 1 0.2
10
PSRR
55 55
62 64 -92 -70 90 10 1.3 0.4 130
dB
Crosstalk TWU TSTDB VSTDBH VSTDBL
dB ms s V V Degrees dB MHz
M
GM GBP
1) Standby mode is activated when Vstdby is tied to Gnd. 2) All PSRR data limits are guaranteed by production sampling tests Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc.
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Electrical characteristics
TS4984
Table 5: Electrical characteristics for VCC = +3.3V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Pout THD + N Supply Current No input signal, no load Standby Current 1 No input signal, Vstdby = GND, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, F = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 400mWrms, Av = 2, 20Hz F 20kHz, RL = 8 Power Supply Rejection Ratio2 RL = 8, Av = 2, Vripple = 200mVpp, Input Grounded F = 217Hz F = 1kHz Channel Separation, RL = 8 F = 1kHz F = 20Hz to 20kHz Wake-Up Time (Cb = 1F) Standby Time (Cb = 1F) Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8 65 15 1.5 300 Parameter Min. Typ. 6.6 10 Max. 12 1000 Unit mA nA mV mW %
1 450 0.1
10
PSRR
55 55
61 63 -94 -68 110 10 1.2 0.4 140
dB
Crosstalk TWU TSTDB VSTDBH VSTDBL
dB ms s V V Degrees dB MHz
M
GM GBP
1) Standby mode is activated when Vstdby is tied to Gnd 2) All PSRR data limits are guaranteed by production sampling tests Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc.
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TS4984
Electrical characteristics
Table 6: Electrical characteristics for VCC = +2.6V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Supply Current No input signal, no load Standby Current 1 No input signal, Vstdby = GND, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, F = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 200mWrms, Av = 2, 20Hz F 20kHz, RL = 8 Power Supply Rejection Ratio2 RL = 8, Av = 2, Vripple = 200mVpp, Input Grounded F = 217Hz F = 1kHz Channel Separation, RL = 8 F = 1kHz F = 20Hz to 20kHz Wake-Up Time (Cb = 1F) Standby Time (Cb = 1F) Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8 65 15 1.5 200 Parameter Min. Typ. 6.2 10 Max. 12 1000 Unit mA nA mV mW %
1 250 0.1
10
Pout
THD + N
PSRR
55 55
60 62 -95 -68 125 10 1.2 0.4 150
dB
Crosstalk TWU TSTDB VSTDBH VSTDBL
dB ms s V V Degrees dB MHz
M
GM GBP
1) Standby mode is activated when Vstdby is tied to Gnd 2) All PSRR data limits are guaranteed by production sampling tests Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc.
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Electrical characteristics
Figure 2: Open loop frequency response
60 40 20
Gain (dB)
TS4984
Figure 5: Open loop frequency response
0 100 80 -40
Phase ()
0 Gain
Gain Phase -80
-40
Phase () Phase () Phase ()
60
Gain (dB)
40 Phase 20 0
-80
0 -120 -20 -40 -60 0.1 Vcc = 5V RL = 8 Tamb = 25C 1 10 100 1000 -160
-120
-20 -200 10000 -40 0.1
Vcc = 5V CL = 560pF Tamb = 25C 1 10 100 1000
-160
-200 10000
Frequency (kHz)
Frequency (kHz)
Figure 3: Open loop frequency response
60 Gain 40 20
Gain (dB)
Figure 6: Open loop frequency response
0 100 80 -40 60
Gain (dB)
0 Gain
-40
Phase
-80
Phase ()
40 Phase 20 0
-80
0 -120 -20 -40 -60 0.1 Vcc = 3.3V RL = 8 Tamb = 25C 1 10 100 1000 -160
-120
-20 -200 10000 -40 0.1
Vcc = 3.3V CL = 560pF Tamb = 25C 1 10 100 1000
-160
-200 10000
Frequency (kHz)
Frequency (kHz)
Figure 4: Open loop frequency response
60 Gain 40 20
Gain (dB)
Figure 7: Open loop frequency response
0 100 80 -40 60
Gain (dB)
0 Gain
-40
Phase
-80
Phase ()
40 Phase 20 0
-80
0 -120 -20 -40 -60 0.1 Vcc = 2.6V RL = 8 Tamb = 25C 1 10 100 1000 -160
-120
-20 -200 10000 -40 0.1
Vcc = 2.6V CL = 560pF Tamb = 25C 1 10 100 1000
-160
-200 10000
Frequency (kHz)
Frequency (kHz)
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TS4984
Figure 8: Power supply rejection ratio (PSRR) vs. frequency
0 -10 -20
PSRR (dB)
Electrical characteristics
Figure 11: Power supply rejection ratio (PSRR) vs. frequency
0
-30 -40 -50 -60 -70
PSRR (dB)
Vripple = 200mVpp Av = 2 Input = Grounded Cb = Cin = 1F RL >= 4 Tamb = 25C
-10 Vcc : 2.2V 2.6V 3.3V 5V -20 -30 -40 -50 -60
Vripple = 200mVpp Av = 2 Input = Grounded Cb = 0.1F, Cin = 1F RL >= 4 Tamb = 25C
Vcc = 5, 3.3, 2.5 & 2.2V
100
1000 10000 Frequency (Hz)
100000
100
1000 10000 Frequency (Hz)
100000
Figure 9: Power supply rejection ratio (PSRR) vs. frequency
0 -10 -20 -30 -40 -50 -60 Vripple = 200mVpp Av = 5 Input = Grounded Cb = Cin = 1F RL >= 4 Tamb = 25C Vcc : 2.2V 2.6V 3.3V 5V
Figure 12: Power supply rejection ratio (PSRR) vs. frequency
0 -10 -20
PSRR (dB)
PSRR (dB)
-30 -40 -50 -60 -70
Vripple = 200mVpp Rfeed = 22k Input = Floating Cb = 1F RL >= 4 Tamb = 25C
Vcc = 2.2, 2.6, 3.3, 5V
100
1000 10000 Frequency (Hz)
100000
-80
100
1000 10000 Frequency (Hz)
100000
Figure 10: Power supply rejection ratio (PSRR) vs. frequency
0 Vripple = 200mVpp Av = 10 Input = Grounded Cb = Cin = 1F RL >= 4 Tamb = 25C Vcc : 2.2V 2.6V 3.3V 5V
Figure 13: Power supply rejection ratio (PSRR) vs. frequency
0 -10 -20
PSRR (dB)
-10
PSRR (dB)
-20
-30 -40 -50 -60 -70
Vripple = 200mVpp Rfeed = 22k Input = Floating Cb = 0.1F RL >= 4 Tamb = 25C
Vcc = 2.2, 2.6, 3.3, 5V
-30
-40
-50 100 1000 10000 Frequency (Hz) 100000
-80
100
1000 10000 Frequency (Hz)
100000
8/29
Electrical characteristics
Figure 14: Power supply rejection ratio (PSRR) vs. DC output voltage
0 -10 -20
PSRR (dB)
TS4984
Figure 17: Power supply rejection ratio (PSRR) vs. DC output voltage
0
PSRR (dB)
-30 -40 -50 -60 -70 -5
Vcc = 5V Vripple = 200mVpp RL = 8 Cb = 1F AV = 2 Tamb = 25C
-10 -20 -30 -40 -50 -60
Vcc = 3.3V Vripple = 200mVpp RL = 8 Cb = 1F AV = 2 Tamb = 25C
-4
-3 -2 -1 0 1 2 3 Differential DC Output Voltage (V)
4
5
-70 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Differential DC Output Voltage (V)
Figure 15: Power supply rejection ratio (PSRR) vs. DC output voltage
0 -10 -20 -30 -40 -50 -60 -5 Vcc = 5V Vripple = 200mVpp RL = 8 Cb = 1F AV = 5 Tamb = 25C
Figure 18: Power supply rejection ratio (PSRR) vs. DC output voltage
0 -10 -20 -30 -40 -50 -60 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Differential DC Output Voltage (V) Vcc = 3.3V Vripple = 200mVpp RL = 8 Cb = 1F AV = 5 Tamb = 25C
PSRR (dB)
-4
-3 -2 -1 0 1 2 3 Differential DC Output Voltage (V)
4
5
Figure 16: Power supply rejection ratio (PSRR) vs. DC output voltage
0 Vcc = 5V Vripple = 200mVpp RL = 8 Cb = 1F AV = 10 Tamb = 25C
Figure 19: Power supply rejection ratio (PSRR) vs. DC output voltage
0 Vcc = 3.3V Vripple = 200mVpp RL = 8 Cb = 1F AV = 10 Tamb = 25C
PSRR (dB) PSRR (dB)
-10
-10
PSRR (dB)
-20
-20
-30
-30
-40
-40
-50 -5
-4
-3 -2 -1 0 1 2 3 Differential DC Output Voltage (V)
4
5
-50 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Differential DC Output Voltage (V)
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TS4984
Figure 20: Power supply rejection ratio (PSRR) vs. DC output voltage
Electrical characteristics
Figure 23: Power supply rejection ratio (PSRR) at f=217Hz vs. bypass capacitor
0 -10 -20 Vcc = 2.6V Vripple = 200mVpp RL = 8 Cb = 1F AV = 2 Tamb = 25C
-30
PSRR at 217Hz (dB)
-40
Av=10 Vcc: 2.6V 3.3V 5V
PSRR (dB)
-30 -40 -50 -60
-50 Av=2 Vcc: 2.6V 3.3V 5V
-60
-70
Av=5 Vcc: 2.6V 3.3V 5V 1 Bypass Capacitor Cb ( F)
Tamb=25C
-70 -2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
2.5
-80 0.1
Differential DC Output Voltage (V)
Figure 21: Power supply rejection ratio (PSRR) vs. DC output voltage
0 -10 -20 -30 -40 -50 Vcc = 2.6V Vripple = 200mVpp RL = 8 Cb = 1F AV = 5 Tamb = 25C
Figure 24: Output power vs. power supply voltage
2.00 RL = 4 1.75 F = 1kHz BW < 125kHz 1.50 Tamb = 25C 1.25
Pout (W)
THD+N=10%
PSRR (dB)
1.00 0.75 0.50 0.25 THD+N=1%
-60 -2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.00
2.5
3.0
3.5
Differential DC Output Voltage (V)
4.0 Vcc (V)
4.5
5.0
5.5
Figure 22: Power supply rejection ratio (PSRR) vs. DC output voltage
0 Vcc = 2.6V Vripple = 200mVpp RL = 8 Cb = 1F AV = 10 Tamb = 25C
Figure 25: Output power vs. power supply voltage
1.75 RL = 8 1.50 F = 1kHz BW < 125kHz 1.25 Tamb = 25C
Pout (W)
-10
THD+N=10%
PSRR (dB)
-20
1.00 0.75 0.50
-30
-40
0.25
-50 -2.5 -2.0 -1.5 -1.0 -0.5
THD+N=1%
0.0
0.5
1.0
1.5
2.0
2.5
0.00
2.5
3.0
3.5
Differential DC Output Voltage (V)
4.0 Vcc (V)
4.5
5.0
5.5
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Electrical characteristics
Figure 26: Output power vs. power supply voltage
1.0 RL = 16 F = 1kHz 0.8 BW < 125kHz Tamb = 25C 0.7 0.9
Pout (W)
TS4984
Figure 29: Output power vs. load resistor
0.7 0.6 THD+N=10% 0.5
Pout (W)
THD+N=10%
Vcc = 3.3V F = 1kHz BW < 125kHz Tamb = 25C
0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 THD+N=1%
0.4 0.3 0.2 0.1 0.0 THD+N=1%
4
8
12
16 20 Load resistance
24
28
32
Figure 27: Output power vs. power supply voltage
0.60 0.55 RL = 32 F = 1kHz 0.50 BW < 125kHz 0.45 Tamb = 25C 0.40
Pout (W)
Figure 30: Output power vs. load resistor
0.40 THD+N=10% 0.35 0.30 0.25
Pout (W)
THD+N=10%
Vcc = 2.6V F = 1kHz BW < 125kHz Tamb = 25C
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 2.5 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 THD+N=1%
0.20 0.15 0.10 0.05 0.00 4 THD+N=1%
8
12
16 20 Load resistance
24
28
32
Figure 28: Output power vs. load resistor
1.75 1.50 THD+N=10% 1.25
Pout (W)
Figure 31: Power dissipation vs. output power
Power Dissipation (W)
Vcc = 5V F = 1kHz BW < 125kHz Tamb = 25C
Vcc=5V 2.4 F=1kHz THD+N<1% 2.0 RL=4 1.6 1.2 0.8 0.4 0.0 0.0 RL=8
1.00 0.75 0.50 0.25 0.00 THD+N=1%
RL=16 0.2 0.4 0.6 0.8 1.0 Output Power (W) 1.2
4
8
12
16 20 24 Load Resistance (W)
28
32
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TS4984
Figure 32: Power dissipation vs. output power
Electrical characteristics
Figure 35: Clipping voltage vs. power supply voltage and load resistor
0.9 Tamb = 25 C
Vout1 & Vout2 Clipping Voltage Low side (V)
1.2 Vcc=3.3V F=1kHz 1.0 THD+N<1% 0.8 0.6 0.4 0.2 RL=16 0.0 0.0 0.1 0.2 0.3 0.4 Output Power (W) 0.5 0.6 RL=8 RL=4
0.8 0.7 RL = 4 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3.0 RL = 16 3.5 Vcc (V) 4.0 4.5 5.0 RL = 8
Power Dissipation (W)
Figure 33: Power dissipation vs. output power
Figure 36: Current consumption vs. power supply voltage
0.7 Vcc=2.6V 0.6 F=1kHz THD+N<1% 0.5 0.4 0.3 0.2 0.1 0.0 0.00 RL=8 RL=4
No Loads Tamb=25C
Power Dissipation (W)
RL=16 0.04 0.08 0.12 0.16 0.20 0.24 Output Power (W) 0.28
Figure 34: Clipping voltage vs. power supply voltage and load resistor
1.0 Tamb = 25 C
Vout1 & Vout2 Clipping Voltage High side (V)
Figure 37: Current consumption vs. standby voltage at Vcc=5V
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 2.5 3.0 3.5 Vcc (V) 4.0 4.5 5.0 RL = 16 Vcc = 5V No Loads Tamb=25C RL = 8 RL = 4
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Electrical characteristics
Figure 38: Current consumption vs. standby voltage at Vcc=3.3V Figure 41: THD+N vs. output power
TS4984
10 RL = 4 F = 20Hz Av = 2 Cb = 1F BW < 125kHz Tamb = 25C Vcc=2.2V Vcc=2.6V
1
THD+N (%)
Vcc=3.3V Vcc=5V
0.1
Vcc = 3.3V No Loads Tamb=25C
0.01
1E- 3
0.01 Pout (W)
0.1
1
Figure 39: Current consumption vs. standby voltage at Vcc=2.6V
Figure 42: THD+N vs. output power
10 RL = 8 F = 20Hz Av = 2 Cb = 1F BW < 125kHz Tamb = 25C Vcc=2.2V Vcc=2.6V Vcc=3.3V Vcc=5V 0.01
Vcc = 2.6V No Loads Tamb=25C
1
THD+N (%)
0.1
1E- 3 1E- 3
0.01 Pout (W)
0.1
1
Figure 40: Current consumption vs. standby voltage at Vcc=2.2V
Figure 43: THD+N vs. output power
10 RL = 16 F = 20Hz Av = 2 Cb = 1F BW < 125kHz Tamb = 25C Vcc=2.2V Vcc=2.6V Vcc=3.3V Vcc=5V 0.01
Vcc = 2.2V No Loads Tamb=25C
1
THD+N (%)
0.1
1E- 3 1E- 3
0.01 Pout (W)
0.1
1
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TS4984
Figure 44: THD+N vs. output power
10 RL = 4 F = 1kHz Av = 2 1 Cb = 1F BW < 125kHz Tamb = 25C 0.1 Vcc = 2.2V Vcc = 2.6V
THD+N (%)
Electrical characteristics
Figure 47: THD+N vs. output power
10 RL = 4 F = 20kHz Av = 2 Cb = 1F BW < 125kHz Tamb = 25C 1 Vcc = 2.2V Vcc = 2.6V Vcc = 3.3V Vcc = 5V
THD+N (%)
Vcc = 3.3V Vcc = 5V
0.01 0.1 1E- 3
1E- 3
0.01
Pout (W)
0.1
1
0.01
Pout (W)
0.1
1
Figure 45: THD+N vs. output power
10 RL = 8 F = 1kHz Av = 2 1 Cb = 1F BW < 125kHz Tamb = 25C 0.1 Vcc = 2.2V Vcc = 2.6V
Figure 48: THD+N vs. output power
10 RL = 8 F = 20kHz Av = 2 Cb = 1F BW < 125kHz Tamb = 25C Vcc = 2.2V Vcc = 2.6V Vcc = 3.3V Vcc = 5V
THD+N (%)
THD+N (%)
Vcc = 3.3V Vcc = 5V
1
0.01
0.1 0.01
Pout (W)
1E- 3
0.1
1
1E- 3
0.01
Pout (W)
0.1
1
Figure 46: THD+N vs. output power
10 RL = 16 F = 1kHz Av = 2 1 Cb = 1F BW < 125kHz Tamb = 25C 0.1 Vcc = 2.2V Vcc = 2.6V
Figure 49: THD+N vs. output power
10 RL = 16 F = 20kHz Av = 2 Cb = 1F BW < 125kHz 1 Tamb = 25C Vcc = 2.2V Vcc = 2.6V Vcc = 3.3V Vcc = 5V
THD+N (%)
Vcc = 3.3V Vcc = 5V
THD+N (%)
0.1 0.01
1E- 3
0.01
Pout (W)
0.1
1
1E- 3
0.01
Pout (W)
0.1
1
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Electrical characteristics
Figure 50: THD+N vs. frequency
TS4984
Figure 53: SIgnal to noise ratio vs. power supply
with unweighted filter (20Hz to 20kHz)
100
Vcc=5V, Po=1W
Signal to Noise Ratio (dB)
THD + N (%)
RL=4 Av=2 0.1 Cb = 1F Bw < 125kHz Tamb = 25C
95 RL=16 RL=8 90 RL=4 Av = 2 Cb = 1F THD+N < 0.7% Tamb = 25C 3.5 4.0 4.5 5.0
Vcc=2.2V, Po=40mW
0.01 20 100 1000 Frequency (Hz) 10000 20k
85
2.5
3.0
Power Supply Voltage (V)
Figure 51: THD+N vs. frequency
Figure 54: SIgnal to noise ratio vs. pwr supply with unweighted filter (20Hz to 20kHz)
Vcc=5V, Po=O.8W
Signal to Noise Ratio (dB)
THD + N (%)
RL=8 0.1 Av=2 Cb = 1F Bw < 125kHz Tamb = 25C
85
80 RL=8 75 RL=4
RL=16
Vcc=2.2V, Po=70mW
0.01
Av = 10 Cb = 1F THD+N < 0.7% Tamb = 25C 3.5 4.0 4.5 5.0
70
20 100 1000 Frequency (Hz) 10000 20k
2.5
3.0
Power Supply Voltage (V)
Figure 52: THD+N vs. frequency
Figure 55: SIgnal to noise ratio vs. power supply with A weighted filter
Vcc=5V, Po=O.5W
Signal to Noise Ratio (dB)
THD + N (%)
RL=16 0.1 Av=2 Cb = 1F Bw < 125kHz Tamb = 25C
105
100 RL=8 95 RL=4
RL=16
Vcc=2.2V, Po=70mW
0.01
Av = 2 Cb = 1F THD+N < 0.7% Tamb = 25C 3.5 4.0 4.5 5.0
90
20 100 1000 Frequency (Hz) 10000 20k
2.5
3.0
Power Supply Voltage (V)
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TS4984
Figure 56: SIgnal to noise ratio vs. power supply with A weighted filter
95
Electrical characteristics
Figure 59: Crosstalk vs. frequency
0 Vcc = 2.6V -20 Av = 2 Pout = 180mW RL = 8 -40 BW < 125kHz Tamb = 25 C -60 -80 -100 -120 100 1000 Frequency (Hz) 10000
Signal to Noise Ratio (dB)
90 RL=16 85 RL=4 80 RL=8
Crosstalk (dB)
L to R
R to L
Av = 10 Cb = 1F THD+N < 0.7% Tamb = 25C 3.5 4.0 4.5 5.0
2.5
3.0
Power Supply Voltage (V)
Figure 57: Crosstalk vs. frequency
0 Vcc = 5V -20 Av = 2 Pout = 1W RL = 8 -40 BW < 125kHz Tamb = 25 C -60 -80 -100 -120 100 1000 Frequency (Hz) 10000
Figure 60: Crosstalk vs. frequency
0 Vcc = 2.2V Av = 2 Pout = 70mW RL = 8 -40 BW < 125kHz Tamb = 25 C -60 -20 -80 -100 -120 100 1000 Frequency (Hz) 10000
Crosstalk (dB)
L to R
R to L
Crosstalk (dB)
L to R
R to L
Figure 58: Crosstalk vs. frequency
0
Figure 61: Output noise voltage, device ON
50
Output Noise Voltage ( Vrms)
Crosstalk (dB)
Vcc = 3.3V -20 Av = 2 Pout = 300mW RL = 8 -40 BW < 125kHz Tamb = 25 C -60 -80 -100 -120
45 40 35
Vcc = 2.2V to 5V Cb = 1F RL = 8 Tamb = 25C Unweighted Filter
L to R
R to L
30 25 20 15 10 2 4 6
Closed Loop Gain
A Weighted Filter
100
1000 Frequency (Hz)
10000
8
10
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Electrical characteristics
Figure 62: Output noise voltage, device in standby
Output Noise Voltage ( Vrms)
TS4984
Figure 63: Power derating curves
QFN16 Package Power Dissipation (W)
3.5 3.0 2.5 Mounted on 2-layer PCB 2.0 1.5 1.0 0.5 0.0 Mounted on 4-layer PCB with via
3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 Vcc = 2.2V to 5V 0.50 Cb = 1F RL = 8 0.25 Tamb = 25C 0.00 2 4 A Weighted Filter Unweighted Filter
No Heat sink 0 25 50 75 100 Ambiant Temperature ( C) 125 150
6
Closed Loop Gain
8
10
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TS4984 4 Application Information
Application Information
The TS4984 integrates two monolithic power amplifiers with a BTL (Bridge Tied Load) output type (explained in more detail in Section 4.1). For this discussion, only the left-channel amplifier will be referred to. Referring to the schematic in Figure 64, we assign the following variables and values: Vin = IN-L Vout1 = VO-L, Vout2 = VO+R Rin = Rin-L, Rfeed = Rfeed-L Cfeed = Cfeed-L Figure 64: Typical application schematic - left channel
Cfeed = Cfeed-L
VCC
+
Rfeed = Rfeed-L Cs 1u
TS4984 VCC1 Input L Cin = Cin-L Vin- = IN-L Rin = Rin-L GND Vin+= IN+L + RL Standby Bypass
+
-
VCC2
Vout 1= VO-L
Bias AV = -1 + Vout 2 = VO+L
Cb 1u
4.1 BTL configuration principle BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended output amplifiers. Thus, we have: Single-ended output 1 = Vout1 = Vout (V), Single-ended output 2 = Vout2 = -Vout (V), Vout1 - Vout2 = 2Vout (V) The output power is: 2 ( 2V outRMS ) P out = -----------------------------------RL For the same power supply voltage, the output power in a BTL configuration is four times higher than the output power in a single-ended configuration.
18/29
Application Information
4.2 Gain in typical application schematic The typical application schematic (Figure 64) is shown on page 18. In the flat region (no Cin effect), the output voltage of the first stage is: R feed V ou t1 = ( - V in ) --------------R in For the second stage: Vout2 = -Vout1 (V) The differential output voltage is: R feed V out2 - V ou t1 = 2V in --------------R in The differential gain, referred to as Gv for greater convenience, is: V out2 - V out1 R feed G v = ----------------------------------- = 2 --------------R in V in (V) (V)
TS4984
Vout2 is in phase with Vin and Vout1 is phased 180 with Vin. This means that the positive terminal of the loudspeaker should be connected to Vout2 and the negative to Vout1. 4.3 Low and high frequency response In the low frequency region, Cin starts to have an effect. Cin forms with Rin a high-pass filter with a -3dB cut-off frequency: 1 F CL = ------------------------- (Hz) 2R in C in In the high frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in parallel with Rfeed. It forms a low-pass filter with a -3dB cut-off frequency. FCH is in Hz. 1 F CH = --------------------------------------2R feed C feed (Hz)
19/29
TS4984
Application Information
The following graph (Figure 65) shows an example of Cin and Cfeed influence. Figure 65: Frequency response gain versus Cin & C feed
10 5 0
Gain (dB)
Cfeed = 330pF Cfeed = 680pF Cin = 470nF Cin = 22nF Cin = 82nF Rin = Rfeed = 22k Tamb = 25C 10000 Cfeed = 2.2nF
-5 -10 -15 -20 -25 10
100 1000 Frequency (Hz)
4.4 Power dissipation and efficiency Hypotheses:
l Voltage and current in the load are sinusoidal (Vout and Iout). l Supply voltage is a pure DC source (Vcc).
Regarding the load we have: V out = V PEAK sint and V out I out = ------------RL and V PE AK 2 P out = -----------------------2R L (W) (A) (V)
Therefore, the average current delivered by the supply voltage is: V PEAK I CC = 2 -----------------(A)
AV G
R L
The power delivered by the supply voltage is: P su pply = V CC I CC A VG (W)
20/29
Application Information
Then, the power dissipated by each amplifier is: P diss =P sup ply - P out (W)
TS4984
2 2 V CC P d iss = ----------------------- RL and the maximum value is obtained when:
P out - P out
(W)
P d iss --------------------- = 0 P out and its value is:
2 2V cc P dissmax = -----------2RL
(W)
Note:
This maximum value is only depending on power supply voltage and load values.
The efficiency, , is the ratio between the output power and the power supply:
V PEAK P o ut = -------------------- = -----------------------P supply 4V CC
The maximum theoretical value is reached when VPEAK = VCC, so that: ---- = 78.5% 4 The TS4984 has two independent power amplifiers, and each amplifier produces heat due to its power dissipation. Therefore, the maximum die temperature is the sum of the each amplifier's maximum power dissipation. It is calculated as follows: Pdiss L = Power dissipation due to the left channel power amplifier. Pdiss R = Power dissipation due to the right channel power amplifier. Total Pdiss = P diss L + Pdiss R (W) In most cases, Pdiss L = Pdiss R, giving: Total P or, stated differently: 4 2 V CC Total P diss = ----------------------- P out - 2P out RL d iss = 2P dissL (W)
(W)
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TS4984
4.5 Decoupling the circuit
Application Information
Two capacitors are needed to correctly bypass the TS4984. A power supply bypass capacitor CS and a bias voltage bypass capacitor CB. CS has particular influence on the THD+N in the high frequency region (above 7 kHz) and an indirect influence on power supply disturbances. With a value for CS of 1 F, you can expect similar THD+N performances to those shown in the datasheet. For example:
l In the high frequency region, if CS is lower than 1 F, it increases THD+N and disturbances on the
power supply rail are less filtered.
l On the other hand, if CS is higher than 1 F, those disturbances on the power supply rail are more
filtered. Cb has an influence on THD+N at lower frequencies, but its function is critical to the final result of PSRR (with input grounded and in the lower frequency region), in the following manner:
l If C b is lower than 1F, THD+N increases at lower frequencies and PSRR worsens. l If C b is higher than 1F, the benefit on THD+N at lower frequencies is small, but the benefit to PSRR
is substantial. Note that C in has a non-negligible effect on PSRR at lower frequencies. The lower the value of Cin, the higher the PSRR. 4.6 Wake-up time, TWU When the standby is released to put the device ON, the bypass capacitor C b will not be charged immediately. As Cb is directly linked to the bias of the amplifier, the bias will not work properly until the Cb voltage is correct. The time to reach this voltage is called wake-up time or TWU and specified in electrical characteristics table with Cb = 1 F. If Cb has a value other than 1 F, please refer to the graph in Figure 66 to establish the wake-up time value. Due to process tolerances, the maximum value of wake-up time could be establish by the graph in Figure 67. Figure 66: Typical wake-up time vs. Cb
600 500
Startup Time (ms)
Figure 67: Maximum wake-up time vs. Cb
600 Tamb=25C Vcc=3.3V
Tamb=25C
Max. Startup Time (ms)
Vcc=3.3V
500 Vcc=2.6V 400 300 200 Vcc=5V 100 0 0.1
400 300 200
Vcc=2.6V
Vcc=5V 100 0
0.1
1
2 3 Bypass Capacitor Cb ( F)
4
4.7
1
2 3 Bypass Capacitor Cb ( F)
4
4.7
Note:
Bypass capacitor Cb as also a tolerance of typically +/-20%. To calculate the wake-up time with this tolerance, refer to the previous graph (considering for example for Cb = 1 F in the range of 0.8 F 1 F 1.2 F).
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Application Information
4.7 Shutdown time
TS4984
When the standby command is set, the time required to put the two output stages in high impedance and the internal circuitry in shutdown mode is a few microseconds. Note:
In shutdown mode, Bypass pin and Vin- pin are short-circuited to ground by internal switches. This allows for the quick discharge of the Cb and Cin capacitors.
4.8 Pop performance Pop performance is intimately linked with the size of the input capacitor Cin and the bias voltage bypass capacitor Cb. The size of Cin is dependent on the lower cut-off frequency and PSRR values requested. The size of Cb is dependent on THD+N and PSRR values requested at lower frequencies. Moreover, Cb determines the speed with which the amplifier turns ON. In order to reach near zero pop and click, the equivalent input constant time is: tin = (Rin + 2 k) x Cin (s) with Rin 5 k must not reach the in maximum value as indicated in the graph below in Figure 68. Figure 68: in max. versus bypass capacitor
160 Tamb=25C Vcc=3.3V 120
in max. (ms)
Vcc=2.6V
80
40
Vcc=5V
0
1
2 3 Bypass Capacitor Cb ( F)
4
By following previous rules, the TS4984 can reach near zero pop and click even with high gains such as 20 dB. Example calculation With R in = 22 k and a 20 Hz, -3 db low cut-off frequency, Cin = 361 nF. So, Cin =390 nF with standard value which gives a lower cut-off frequency equal to 18.5 Hz. In this case, (Rin + 2 k) x Cin = 9.36 ms. When referring to the previous graph, if Cb =1 F and Vcc = 5 V, we read 20 ms max. This value is twice as high as our current value, thus we can state that pop and click will be reduced to its lowest value. Minimizing both Cin and the gain benefits both the pop phenomena, and the cost and size of the application.
23/29
TS4984
4.9 Application example: Differential-input BTL power stereo amplifier
Application Information
The schematic in Figure 69 shows how to design the TS4984 to work in differential-input mode. For this discussion, only the left-channel amplifier will be referred to. Let: R1R = R2L = R1, R2R = R2L = R2 CinR = C inL = Cin The gain of the amplifier is: R2 G vdif = 2 x ------R1 In order to reach the optimal performance of the differential function, R1 and R2 should be matched at 1% maximum. Figure 69: Differential input amplifier configuration
R2L
Neg. Input LEFT CinL
VCC
+
R1L VCC1 VCC2
TS4984
Cs
IN-L
Pos. Input LEFT
VO-L
CinL
R1L IN+L +
R2L
LEFT Speaker StandBy Control
StandBy BypassL
Bias AV = -1 + VO+L
8 Ohms
R2R
Pos. Input RIGHT
CinR
R1R
IN+R
+ VO-R
IN-R
Neg. Input RIGHT
-
CinR
R1R
RIGHT Speaker
AV = -1 BypassR
+
8 Ohms
VO+R
+
Cb
GND1 R2R
24/29
GND2
Application Information
TS4984
The value of the input capacitor CIN can be calculated with the following formula, using the -3dB lower frequency required (where FL is the lower frequency required):
C IN 1 (F ) 2 R 1 FL
Note:
This formula is true only if: 1 (Hz ) FCB = 2 (R 1 + R 2 ) C B is 5 times lower than FL.
The following bill of materials is provided as an example of a differential amplifier with a gain of 2 and a -3 dB lower cut-off frequency of about 80 Hz. Table 7: Example of a bill of material
Designator R1L = R1R R2L = R2R CinR = CinL Cb=CS U1 Part Type 20k / 1% 20k / 1% 100nF 1F TS4984
25/29
TS4984 4.10 Demoboard
A demoboard for the TS4984 is available.
Application Information
For more information about this demoboard, please refer to Application Note AN2049, which can be found on www.st.com. Figure 70 shows the schematic of the demoboard. Figure 71, Figure 72 and Figure 73 show the component locations, top layer and bottom layer respectively. Figure 70: Demoboard schematic
C1
R1
VCC Vcc GND Cn1
+
C7 1u
C9 100nF
14
13
U1
VCC1
R2 1
Neg. Input L GND Cn2
C2
IN-L
VO-L
16
C3 Pos. Input L GND Cn3 VCC Cn8
R3
2 R4
IN+L
+
Jumper J1
1 2 3
VCC2
12 3
+
Standby Bypass L
Bias AV = -1 + VO+L
15
Cn4 Neg. Output L Pos. Output L
C8 1u R7
Pos. Input R GND Cn5
C4
R5
10
IN+R
+ VO-R
8
C5 Neg. Input R GND Cn6
R6
9
IN-R
-
AV = -1
11
Cn7
VO+R
Neg. Output R 7 Pos. Output R
Bypass R
+
GND1
GND2
5
C6
R8
26/29
6
*
Application Information
Figure 71: Components location Figure 72: Top layer
TS4984
Figure 73: Bottom layer
27/29
TS4984 5 Package Mechanical Data
Package Mechanical Data
5.1 Dimensions of QFN16 package
DIMENSIONS REF mm MIN.
0.8
TYP.
0.9 0.02 0.20
MAX.
1.0 0.05 0.30 4.15 2.6 4.15 2.6
*
* The Exposed Pad is connected to Ground.
A A1 A3 b D D2 E E2 e K L r
0.18 3.85 2.1 3.85 2.1
0.25 4.0 4.0 0.50
0.2 0.30 0.11 0.40 0.50
5.2 Footprint recommended data
A
FOOTPRINT DATA mm
E
A B C D
5.0 5.0 0.5 0.35 0.45 2.70 0.22
B
F
G
D
C
E F G
28/29
TS4984 6 Revision History
Date 01 Jan 2005 Revision 1 First Release Description of Changes
Revision History
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved 2005
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