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TH58NVG1S3AFT05
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2GBIT (256M DESCRIPTION
8BITS) CMOS NAND E2PROM
The TH58NVG1S3A is a single 3.3-V 2G-bit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048+64) bytes x 64 pages x 2048 blocks. The device has a 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4Kbytes: 2112 bytes x 64 pages). The TH58NVG1S3A is a serial-type memory device which utilizes the I/O pins for both address and data input / output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density nonvolatile memory data storage.
FEATURES
Organization Memory cell allay 2112 64K 8 2 Register 2112 8 Page size 2112bytes Block size (128K 4K) bytes Modes Read Reset Auto Page Program Auto Block Erase Status Read Mode control Serial input output Command control
Powersupply VCC 2.7 V to 3.6 V Program/Erase Cycles 1E5 Cycles(With ECC) Access time Cell array to register 25 s max Serial Read Cycle 50 ns min Operating current Read (50 ns cycle) 10 mA typ. Program (avg.) 10 mA typ. Erase (avg.) 10 mA typ. Standby 50 A max Package TSOP I 48-P-1220-0.50 (Weight : 0.53 g typ.)
PIN ASSIGNMENT (TOP VIEW)
NC NC NC NC NC GND RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC
PIN NAMES
I/O1 to I/O8 I/O port
CE
WE RE CLE ALE WP RY / BY GND VCC VSS
Chip enable
Write enable Read enable Command latch enable Address latch enable Write protect Ready / Busy Ground Input Power supply Ground
000707EBA1
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.
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TH58NVG1S3AFT05 BLOCK DIAGRAM
Status register
VCC VSS
I/O1
Address register I/O Control circuit
Column buffer Column decoder
to
I/O8
Command register
Data register Sense amp
Row address decorder
CE
Row address buffer decoder
CLE ALE WE RE WP RY / BY RY / BY HV generator Logic control Control circuit
Memory cell array
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC VIN VI/O PD TSOLDER TSTG TOPR Power Supply Voltage Input Voltage Input /Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE 0.6 to 4.6 0.6 to 4.6 0.6 V to VCC 0.3 V ( 0.3 260 -55 to 150 0 to 70 4.6 V) UNIT V V V W C C C
CAPACITANCE *(Ta 25C, f 1 MHz)
SYMB0L CIN COUT Input Output PARAMETER CONDITION VIN VOUT 0V 0V MIN MAX 20 20 UNIT pF pF
* * This parameter is periodically sampled and is not tested for every device.
The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice.
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TH58NVG1S3AFT05 VALID BLOCKS (1)
SYMBOL NVB PARAMETER Number of Valid Blocks MIN. 2008 TYP. MAX 2048 UNIT Blocks
(1) The TH58NVG1S3A occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. (2) The first block (block address #00) is guaranteed to be a valid block at the time of shipment.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL VCC VIH VIL
*
PARAMETER Power Supply Voltage High Level input Voltage Low Level Input Voltage
MIN 2.7 2.0 0.3*
TYP. 3.3
MAX 3.6 VCC 0.8 0.3
UNIT V V V
2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS (Ta 0 to 70 , VCC 2.7V ~ 3.3 V)
SYMBOL IIL ILO ICCO1 ICCO7 ICCO8 ICCS1 ICCS2 VOH VOL PARAMETER Input Leakage Current Output Leakage Current Reading Programming Current Erasing Current Standby Current Standby Current High Level Output Voltage Low Level Output Voltage CE CE VIH , WP VCC 0V/VCC 0V/VCC 2.4 0.4 8 VIN VOUT CE CONDITION 0 V to VCC 0 V to VCC VIL, IOUT 0 mA, tcycle 50 ns 10 10 10 MIN TYP. MAX 10 10 30 30 30 1 50 UNIT A A mA mA mA mA A V V mA
0.2 V, WP 400 A
Vcc, IOH Vcc, IOL
2.1 mA
IOL ( RY / BY ) Output current of RY / BY pin VOL
0.4 V
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TH58NVG1S3AFT05 AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta 0 to 70
SYMBOL tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tWW tRR tRW tRP tRC tREA tCEA tCLEA tALEA tREAID tOH tRHZ tCHZ tREH tIR tRSTO tCSTO tCLSTO tRHW tWHC tWHR tR tWB tRST CLE Setup Time CLE Hold Time
CE Setup Time CE Hold Time
, VCC
2.7V ~ 3.6V)
PARAMETER MIN 0 10 0 10 25 0 10 20 10 50 15 100 20 20 35 50 35 45 45 45 35 10 30 20 15 0 35 45 45 30 30 30 25 200 6/10/500 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s
NOTES
Write Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time
WE High Hold Time WP High to WE Low
Ready to RE Falling Edge Ready to WE Falling Edge Read Pulse Width Read Cycle Time
RE Access Time (Serial Data Access) CE Access Time
CLE Access Time ALE Access Time
RE Access Time (ID Read)
Data Output Hold Time
RE High to Output High Impedance CE High to Output High Impedance RE High Hold Time
Output-High-impedance-to- RE Falling Edge
RE Access Time (Status Read) CE Access Time (Status Read)
CLE Access Time (Status Read)
RE High to WE Low WE High to CE Low WE High to RE Low
Memory Cell Array to Starting Address
WE High to Busy
Device Reset Time (Read/Program/Erase)
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TH58NVG1S3AFT05 AC TEST CONDITIONS
PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load CONDITION 2.4 V, 0.4 V 3ns 1.5 V, 1.5 V 1.5 V, 1.5 V CL (100 pF) 1 TTL
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta 0 to 70 , VCC 2.7V ~ 3.6V)
PARAMETER Average Programming Time Number of Programming Cycles on Same Page N (per 512+16 bytes) tBERASE Block Erasing Time 2 4 ms 2 (1) MIN TYP. 200 MAX 700 UNIT s NOTES
SYMBOL tPROG
(1) Refer to Application Note (12) toward the end of this document.
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TH58NVG1S3AFT05 TIMING DIAGRAMS
Latch Timing Diagram for Command/Address /Data
CLE ALE CE RE
Setup Time
Hold Time
WE tDS tDH
I/O
: VIH or VIL
Command Input Cycle Timing Diagram
CLE
tCLS tCS
tCLH tCH
CE tWP
WE tALS tALH
ALE tDS tDH
I/O
: VIH or VIL
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TH58NVG1S3AFT05
Address Input Cycle Timing Diagram
tCLS
CLE tCS tWC tWC tWC tWC
CE tWP tWH tWP tWH tWP tWH tWP tWH tWP
WE tALS tALH
ALE tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
I/O
CA0 to7
CA8 to11
PA0 to 7
PA8 to 15
PA16
: VIH or VIL
Data Input Cycle Timing Diagram
tCLH
CLE tCH
CE tALS tWC
ALE tWP tWH tWP tWP
WE tDS tDH tDS tDH tDS tDH
I/O
DIN0
DIN1
DIN2111
: VIH or VIL
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TH58NVG1S3AFT05
Serial Read Cycle Timing Diagram
tRC tCEA CE tRP tREH tRP tRP tCHZ
RE tREA
tOH tRHZ tREA
tOH tRHZ tREA
tOH tRHZ
I/O
tRR
RY / BY
Status Read Cycle Timing Diagram
tCLSTO
CLE
tCLS tCS
tCLH
CE tWP tCH
WE
tWHC tWHR
tCSTO
tCHZ
RE tDS tDH tIR tRSTO
tOH tRHZ
I/O
70H*
Status output
RY / BY
* 70H represents the hexadecimal number
: VIH or VIL
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TH58NVG1S3AFT05
Read Cycle Timing Diagram
tCLEA CLE tCLS tCS CE tWC tCLH tCH tCLS tCS tCLH tCH tCEA
WE tALH tALS tALH tALS
ALE tR RE tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tRR tREA DOUT DOUT N N1 Data out from Col. Add. N tWB tRC
I/O
00H
CA0 to 7
CA8 to 11
PA0 to 7
PA8 to 15
PA16
30H
Col. Add. N RY / BY
Read Cycle Timing Diagram : When Interrupted by /CE
tCLEA CLE tCLS tCS CE tWC tCLH tCH tCLS tCS tCLH tCH tCEA
WE tALH tALS tALH tALS tCHZ ALE tR RE tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tRR tREA DOUT DOUT N N1 Col. Add. N Col. Add. N RY / BY tWB tOH tRC tRHZ
I/O
00H
CA0 to 7
CA8 to 11
PA0 to 7
PA8 to 15
PA16
30H
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TH58NVG1S3AFT05
Column Address Change in Read Cycle Timing Diagram (1/2)
tCLEA CLE tCLS tCS CE tWC tCEA WE tALH tALS tALH ALE tR RE tDS tDH tDS tDH
CA0 to 7
tCLH tCH
tCLS tCS
tCLH tCH
tALS
tRC
tWB tDS tDH
CA8 to 11
tDH tDS tDH tDS tDH tDS tDH
PA0 to 7 PA8 to 15
tDS tDH tREA tRR DOUT DOUT A A1 DOUT AN
I/O
00H
PA16
30H
Column address A RY / BY
Page address P
Page address P
Column address A
1
Continues to 1 of next page
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TH58NVG1S3AFT05
Column Address Change in Read Cycle Timing Diagram (2/2)
tCLEA CLE tCLS tCS CE tWC WE tRHW tALH tALS tALH tALS tCEA tCLH tCH tCLS tCS tCLH tCH
ALE tRC RE tDS tDH tDS tDH
CA0 to 7
tDS tDH
CA8 to 11
tDS tDH
tIR I/O
DOUT AN 05H E0H
tREA DOUT DOUT B B1 DOUT B N'
Column address B RY / BY
Page address P
Column address B
1
Continued from 1 of last page
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TH58NVG1S3AFT05
Auto-Program Operation Timing Diagram
tCLS CLE
tCLS tCLH tCS tCS
CE tCH WE
tALH tALS
tALH tProg tALS tWB
ALE
RE tDS tDH tDS tDH CA0 to CA8 to PA0 to PA8 to PA16 7 11 7 15
tDS tDH DIN0 DIN1 DIN2111* 10H
tDS tDH 70H Status output
I/O
80H
RY / BY
: Do not input data while data is being output. : VIH or VIL
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TH58NVG1S3AFT05
Auto Block Erase Timing Diagram
CLE
tCLS tCS tCLH tCLS
CE
WE tALH tALS ALE tWB tBERASE
RE tDS tDH
I/O
60H
PA0 to 7
PA8 to 15
PA16
D0H
70H
Status output
RY / BY
Auto Block Erase Setup command : VIH or VIL
Erase Start command
Busy
Status Read command
: Do not input data while data is being output.
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TH58NVG1S3AFT05
ID Read Operation Timing Diagram
tCLS tCLS tCS CE tCS WE tCH tALH tALH tALS tALEA tCH tCEA
CLE
ALE
RE tDH I/O 90H ID Read command tDH 00H Address 00 tREAID tREAID 98H Maker code tREAID DAH Device code tREAID Note1 tREAID Note2 Note3
Note1 : 81H or 01H Note2 : 95H or 15H Note3 : 44H or C4H
: VIH or VIL
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TH58NVG1S3AFT05 PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is latched if ALE is Low.
NC NC NC NC NC GND RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC
Chip Enable: CE
Figure 1. Pinout
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The CE signal is ignored when device is in Busy state ( RY / BY L ), such as during a Program or Erase or Read operation, and will not enter Standby mode even if the CE input goes High.
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE . The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid.
Ready/Busy: RY / BY
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state ( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be pulled-up to Vccq with appropriate resister..
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TH58NVG1S3AFT05
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1 2048 64 I/O8
64Pages = 1block
A page consists of 2112 bytes in which 2048 bytes are used for main memory storage and 64 bytes are for redundancy or for other uses. 1 page = 2112bytes 1 block = 2112 bytes x 64 pages = (128K + 4K) bytes Capacity = 2112bytes x 64pages x 2048blocks An address is read in via the I/0 port over four consecutive clock cycles, as shown in Table 1.
8I/O 2112
Figure 2. Schematic Cell Layout Table 1. Addressing I/O8 First cycle Second cycle Third cycle Fourth cycle Fifth cycle CA7 L PA7 PA15 L I/O7 CA6 L PA6 PA14 L I/O6 CA5 L PA5 PA13 L I/O5 CA4 L PA4 PA12 L I/O4 CA3 CA11 PA3 PA11 L I/O3 CA2 CA10 PA2 PA10 L I/O2 CA1 CA9 PA1 PA9 L I/O1 CA0 CA8 PA0 PA8 PA16 PA6 to PA16 PA0 to PA5 : Block address : NAND address in block CA0 to CA11 : Column address PA0 to PA16 : Page address
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the eleven different command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2.
Table 2. Logic Table CLE Command Input Data Input Address input Serial Data Output During Programming (Busy) During Erasing (Busy) During Reading (Busy) H L L L
* * * * *
ALE L L H L
* * * * *
CE L L L L
* * * *
WE
RE H H H
WP
*
*1
H
* *
H
* * * * * * * * * *
H H
*
Program, Erase Inhibit Standby
L 0 V/Vcc
H
H: VIH, L: VIL, *: VIH or VIL *1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
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TH58NVG1S3AFT05
Table 3. Command table (HEX) First Cycle Serial Data Input Auto Program Read Address Input Column Address Change in Serial Data Output Read Start Read Column Change 80 10 00 05 30 E0 60 90 70 FF D Second Cycle Acceptable while Busy
Auto Block Erase ID Read Status Read Reset
HEX data bit assignment (Example) Serial Data Input : 80H
1
0
0 6
0 5
0 4
0 3
0
0
I/O8 7
2 I/O1
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states CLE Output select Output Deselect Standby Read Busy H: VIH, L: VIL, *: VIH or VIL L L L ALE L L L CE L L H WE H H H RE L H
*
I/O1 to I/O8
Data output High impedance High impedance High Impedance
Power
Active Active Standby Active
*
*
*
*
*
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TH58NVG1S3AFT05 DEVICE OPERATION
Read Mode
Read mode is set when "00H" and "30H" commands are issued to the Command register. Between the commands, start address for the Read mode need to be issued. Refer to Figure 3 below for sequence and the block diagram (Refer to the detailed timing chart.).
CLE CE WE ALE RE RY / BY I/O 00H Start-address input M Select page N Figure 3. Read mode (1) operation 2111 A data transfer operation from the cell array to the register starts on the rising edge of WE in the 30h command input cycle (after the address information has been latched). The device will be in Busy state during this transfer period. After the transfer period the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. Column Address M Page Address N 30H Busy M M+1 M+2
Page Address N
Cell array
Random Column Address Change in Read Cycle
CLE CE WE
ALE
RE RY / BY 00H Col. M Page N 30H Busy Col. M
I/O
M
M+1 M+2 M+3
05H Col. M'
E0H
M' M'+1 M'+2 M'+3 M'+4
Start-address input M M'
Page N Start from Col. M
Page N Start from Col. M'
Select page N
Cell array
In the serial data out from the register, the column address can be changed by inputting the column address with 05h and E0h commands. The data are read out in serial from the column address which is input to the device by 05h and E0h commands with /RE clock.
Figure 4. Random Column Address Change in Serial Read
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TH58NVG1S3AFT05
Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10H" Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)
CLE
/CE
/WE
ALE RE RY / BY 80H Din Din Din Din
10h 70h
Status Out
I/O
Col. M
Page P
Data
The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the " 10H command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached.
Data input
Program Selected page Reading & verification
Figure 7. Auto Page Program operation
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command "DOH" which follows the Erase Setup command "60H". This three-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations.
60 Block Address input : 3 cycles RY / BY
D0 Erase Start command Busy
70 Status Read command
I/O
Pass
Fail
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TH58NVG1S3AFT05
ID Read
The device contains ID code which identify the device type, the manufacturer, and some features of the device. The ID codes can be read out under the following timing conditions:
CLE tCEA CE WE tALEA ALE
RE tREAID I/O 90H ID Read command 00H Address 00 98H Maker code DAH Device code Note1 Note2 Note3
For the specifications of the access times tREAID and tALEA refer to the AC Characteristics.
Figure 13. ID Read timing
Note1 : 81H or 01H Note2 : 95H or 15H Note3 : 44H or C4H
Table 6. Code table Descripton 1 Data 2 Data 3 Data
th rd nd st
I/O8 1 1 0 or 1
I/O7 0 1 0
I/O6 0 0 0
I/O5 1 1 0
I/O4 1 1 0
I/O3 0 0 0
I/O2 0 1 0
I/O1 0 0 1
Hex Data 98H DAH 81H or 01H
Maker Code Device Code Chip Number, Cell Type, PGM Page, Write Cache
4 Data 5 Data
th
Page Size, Block Size, 0 or 1 Redundant Size, Organization Plane Number, Plane Size 0 or 1
0 1
0 0
1 0
0 0
1 1
0 0
1 0
95H or 15H 44H or C4H
3rd Data
Descripton 1 2 Internal Chip Number 4 8 2 level cell 4 level cell Cell Type 8 level cell 16 level cell 1 2 4 8 Reserved 1 Reserved 2 0 or 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 0 0 1 1 I/O1 0 1 0 1
Number of simultaneously programmed pages
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TH58NVG1S3AFT05
4th Data
Descripton 1KB Page Size (without redundant area) 2KB 4KB 8KB 64KB Block Size (without redundant area) 128KB 256KB 512KB 8 16 Reserved Reserved X8 Organization Reserved X16 0 or 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 0 0 1 1 I/O1 0 1 0 1
Redundant area size (byte/512byte)
5th Data
Descripton 1 2 Plane Number 4 8 64Mb 128Mb 256Mb 512Mb Plane Size 1Gb 2Gb 4Gb 8Gb Reserved 0 or 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 I/O8 I/O7 I/O6 I/O5 I/O4 0 0 1 1 I/O3 0 1 0 1 I/O2 I/O1
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TH58NVG1S3AFT05
Status Read
The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass /fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the I/O port on the RE clock after a "70H" command input. The resulting information is outlined in Table 5.
Table 5. Status output table STATUS I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 Chip Status 1 Chip Status 2 Not Used Not Used Not Used Ready/Busy Data Cache Busy
Write Protect
OUTPUT Pass: 0 Pass: 0 0 0 0 Ready: 1 Ready: 1 Protect: 0 Busy: 0 Busy: 0 Not Protected: 1 Fail: 1 Fail: 1 The Pass/Fail status on I/O1 and I/O2 is only valid when the device is in the Ready state.
An application example with multiple devices is shown in Figure 6.
CE1 CE2 CE3 CEN CEN 1
CLE ALE WE RE I/O1 to I/O8 RY / BY RY / BY CLE ALE WE
CE1 CEN
Device 1
Device 2
Device 3
Device N
Device N1
Busy
RE I/O 70H Status on Device 1 70H Status on Device N
Figure 6. Status Read timing application example System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device.
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TH58NVG1S3AFT05
Reset
The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an "FFH" Reset command input during the various device operations is as follows:
When a Reset (FFH) command is input during programming
80 Internal VPP 10 FF 00
RY / BY tRST (max 10 s) Figure 8.
When a Reset (FFH) command is input during erasing
D0 Internal voltage erase FF 00
RY / BY tRST (max 500 s) Figure 9.
When a Reset (FFH) command is input during Read operation
00 30 RY / BY FF 00
Figure 10. t RST (max 6 s)
When a Status Read command (70H) is input after a Reset
FF 70 I/O status : Pass/Fail Pass : Ready/Busy Ready
RY / BY
When two or more Reset commands are input in succession
(1) 10 FF (2) FF (3) FF
RY / BY The second FF command is invalid, but the third Figure 12. FF command is valid.
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TH58NVG1S3AFT05 APPLICATION NOTES AND COMMENTS
(1) Power-on/off sequence: The timing sequence shown in Figure 15 is necessary for power-on/off sequence. The device internal initialization start after the power supply reaches appropriate level in power on sequence. During the initialization the device Ready/Busy signal outputs Busy state as shown in the Figure-15. In this time period, the acceptable commands are FFh or 70h. The WP signal is useful for protecting against data corruption at power-on/off.
2.7V 2.5V 0V VCC don't care CE , WE , RE CLE, ALE VIL 1ms max 100s max invalid Ready/Busy Operation don't care VIH VIL don't care
WP
Figure 15. Power-on/off Sequence
(2) Status after power-on The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF Reset Figure 16.
(3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4) Restriction of command while Busy state During Busy state, do not input any command except 70H, and FFH.
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(5) Acceptable commands after Serial Input command "80H" Once the Serial Input command "80H" has been input, do not input any command other than the Column Address Change in Auto Program command "10H" or the Reset command "FFH".
80 WE Address input RY / BY FF
If a command other than "10H" or "FFH" is input, the Program operation is not performed and the device operation is set to the mode which the input command specifies..
80 XX Mode specified by the command. 10 Programming cannot be executed.
Command other than "10H" or "FFH"
(6) Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page DATA IN: Data (1) Data (64) Data register Page 0 Page 1 Page 2 (1) (2) (3) Page 0 Page 1 Page 2 Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) Data register (2) (32) (3)
Page 31
(32)
Page 31
(1)
Page 63
(64)
Page 63
(64)
Figure 17. page programming within a block
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(7) Status Read during a Read operation
00 comma CE WE RY/BY RE Address N Figure 18. Status Read command input Status Read Status output 00 30 70 [A]
The device status can be read out by inputting the Status Read command "70H" in Read mode. Once the device has been set to Status Read mode by a "70H" command, the device will not return to Read mode. Therefore, a Status Read during a Read operation is prohibited. However, when the Read command "00H" is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary
(8) Auto programming failure
Fail 80 Address M 80 10 M If the programming result for page address M is Fail, do not try to program the page to address N in another block without the data input sequence. Because the previous input data has been lost, the same input sequence of 80H command, address and data is necessary. Data input 10 70 I/O 80 Address N Data input 10
N Figure 19.
(9) RY / BY : termination for the Ready/Busy pin ( RY / BY ) A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain circuit.
VCC VCC Device CL VSS tr Ready 3.0 V R RY / BY tf VCC 1.0 V Busy 1.0 V tr VCC 3.3 V Ta 25C CL 100 pF 3.0 V
1.5 s tf 1.0 s tr 0.5 s 0
15 ns 10 ns 5 ns tf
This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value.
1K
2K R
3K
4K
Figure 20.
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(10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows:
Enable Programming WE
DIN
80
10
WP
RY / BY tWW (100 ns MIN)
Disable Programming WE
DIN
80
10
WP
RY / BY tWW (100 ns MIN)
Enable Erasing WE
DIN
60
D0
WP
RY / BY tWW (100 ns MIN)
Disable Erasing
WE
DIN
60
D0
WP
RY / BY tWW (100 ns MIN)
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(11) When six address cycles are input Although the device may read in sixth address, it is ignored inside the chip.
Read operation
CLE
CE
WE
ALE
I/O
00H ignored Address input
30H
RY / BY
Figure 22.
Program operation
CLE
CE
WE
ALE
I/O
80H Address input ignored Data input
Figure 23.
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(12) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 8 segments as follows :Data area (column address 0 to 2047) : 512 bytes x 4 segments 1st segment: column address 0 to 511 2nd segment: column address 512 to 1023 3rd segment: column address 1024 to 1535 4th segment: column address 1536 to 2047 Redundant area (column address 2048 to 2111) : 16 bytes x 4 segments 1st segment: column address 2048 to 2063 2nd segment: column address 2064 to 2079 3rd segment: column address 2080 to 2095 4th segment: column address 2096 to 2111
. Each segment can be programmed individually as follows:
1st programming
Data Pattern 1
All 1s
2nd programming
All 1s
Data Pattern 2
All 1s
8th programming
All 1s
Data Pattern 8
Result
Data Pattern 1
Data Pattern 2 Figure 24.
Data Pattern 8
Note: The input data for unprogrammed or previously programmed page segments must be "1" (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all "1").
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(13) Invalid blocks (bad blocks) The device occasionally contains unusable blocks. Therefore, the following issues must be recognized: At the time of shipment, all data bytes in a valid block are FFH. For bad blocks, all bytes are not in the FFH state. Please don't perform erase operation to bad blocks.
Bad Block
Check if the device has any bad blocks after installation into the system. Figure 27 shows the test flow for bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the bit line by the select gate The number of valid blocks at the time of shipment is as follows:
Bad Block
Figure 26. MIN Valid (Good) Block Number 2008 TYP. MAX 2048 UNIT Block
Bad Block Test Flow
Start Read Check : Read the 1st page or the 2nd page of each block. If the column address 0 or 2048 of the 1st page or the 2nd page is not FF (Hex), define the block as a bad block. Fail Read Check Pass Block No. Block No. 1 Bad Block *1
Block No
1
No Block No. 2048 Yes End
Figure 27.
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(14) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE Block Page Single Bit "1 to 0" (2) ECC Erase Failure Programming Failure Programming Failure
DETECTION AND COUNTERMEASURE SEQUENIE Status Read after Erase Status Read after Program (1) Block Verify after Program Block Replacement Block Replacement Retry
ECC : Error Correction Code . Block Replacement
Program Error occurs Buffer memory
Block A
When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A ( by creating a bad block table or by using another appropriate scheme).
Block B
Figure 28.
Erase
When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme).
(15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data.
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TH58NVG1S3AFT05 Package Dimensions
Weight: 0.53 g (typ.)
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