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MSX532 532 Port Digital Crosspoint Switch with LVTTL I/O's
June 2002 Revised April 2003
MSX532 532 Port Digital Crosspoint Switch with LVTTL I/O's
General Description
The MSX family of SRAM-based bit-oriented switching devices offer flow-through NRZ data rates of up to 150Mb/s and registered clock frequencies of up to 75MHz. The I/O buffers are individually configurable. The I/O buffers can be connected to each other through the switch matrix, which supports One-to-One and One-to-Many connections. The proprietary RapidConfigure parallel interface allows fast configuration of both the I/O buffers and switch matrix. It also allows readback of the device for test and verification purposes. The MSX devices also support the industry standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to download configuration data to the device. A functional block diagram of the MSX architecture is shown in Figure 1.
Features
s SRAM-based, in-system programmable s Configurable I/O Ports * Individually programmable as input, output, bi-directional, or Bus Repeater mode * Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor Clock option * Output data inversion: capable of inverting output signals in flow through mode s Non-blocking switch matrix * One-to-One and One-to-Many connections Double-buffered configuration RAM cells simultaneous global updates s Registered and flow-through data modes * Up to 75 MHz clock frequency in registered mode * Up to 150 Mb/s in flow-through mode s 20 ns propagation delay in flow-through mode s 8 mA output current s Dedicated RapidConfigure parallel interface or JTAG serial interface available for configuration and readback of MSX devices s 3.3V operation, LVTTL I/O's (5V tolerant) s MSX532 is offered in a 792 TBGA package for
Applications
* Telecom and datacom switching * Video switches and servers * Test equipment
Ordering Code:
Order Number MSX532TB792 Package Number BGA792A Package Description 792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch, 40mm Square
MSX, Bus Repeater, and RapidConfigure are trademarks of Fairchild Semiconductor Corporation.
(c) 2003 Fairchild Semiconductor Corporation
DS500746
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MSX532
FIGURE 1. MSX532 Functional Block Diagram
Introduction
Switch Matrix The MSX family are SRAM-based, bit-oriented switching devices. The main functional block of the device is a Switch Matrix as shown in Figure 1. The Switch Matrix is an x-y routing structure (or grid). Each horizontal signal trace is hardwired to a corresponding vertical signal trace as shown by the junction dots. An I/O Port pin connects to this horizontal-vertical trace pair through a programmable buffer. Signal paths through the Switch Matrix are well balanced, resulting in predictable and uniform pin-to-pin delays. The two SRAM cells (shown in Figure 2) are arranged so that a double buffered scheme can be employed. The Active SRAM cells are responsible for establishing connections in the switch matrix by turning ON a pass transistor, while the Loading SRAM cell can be used to store a second configuration that can be transferred to the Active SRAM cell at any time. If the UPDATE signal is asserted HIGH, the contents of the Loading SRAM cell are transferred to the Active SRAM cell and the switch matrix connection is either made or broken. The UPDATE signal can be used to control when the switch matrix is reconfigured. For instance, as long as the UPDATE signal is de-asserted (held LOW), the Loading SRAM cells for the entire switch matrix could be changed without affecting the current configuration of the switch. When the UPDATE signal is asserted HIGH, the entire switch matrix would be reconfigured simultaneously. If the UPDATE signal is asserted continuously, all crosspoint programming commands (generated by JTAG or RapidConfigure programming cycles) will take effect immediately, since the Loading SRAM cell's contents will be transferred directly to the Active SRAM cell.
FIGURE 2. MSX Switch Matrix Diagram 2
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MSX532
Introduction
(Continued) Input and Output Buffers (I/O buffers) Each signal in the switch matrix is connected to a programmable I/O buffer, which is independently configured through either the RapidConfigure or JTAG Interface. The I/O buffer attributes include its signal direction (input, output or bi-directional) and data flow mode (flow-through or registered). The signal can also be inverted at the output. Trickle current source (normally 15 A) on the pin side and
VDD
array side for each I/O Port and control pin is used to pull unused or non-driven circuits to a stable HIGH level. Figure 3 shows a basic block diagram of an I/O buffer with the sources for the three control signals (IE, OE and CLK). For any given port number, these three control signals can be selected from one of two sources. The control signals are explained in more detail in the following section.
IE { CLK Sources { Next Neighbor CLK_IN IN Switch Matrix
BR I/O Port
OUT
CLK Sources { Next Neighbor OE {
CLK_OUT
VSS
FIGURE 3. MSX I/O Buffer Block Diagram I/O Port Function Mode The following legend describes the various modes of the Input or Output Ports and the specification used by the Fairchild Development System Software for bitstream generation. Legend: Ax Px IE OE Next-Neighbor Clocking Included among the clocking options in MSX532 is the ability to use an adjacent port as a clock source. This is referred to as a Next-Neighbor Clock. In the MSX532, Port 0 can be clocked by Port 1, which can be clocked by Port 2, which can be clocked by Port 3, etc. In turn, Port 531 can be clocked by Port 0. Since each I/O buffer can be programmed as an input or an output (among other options) there are four ways to utilize the next neighbor clock option.
= Switch Matrix Signal = I/O Port Signal = Input Enable = Output Enable (Active LOW)
CLK = Clock
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MSX532
Introduction
(Continued) Option 1: Registered Input with Next-Neighbor Clock as Input
Option 2: Registered Output with Next-Neighbor Clock as Input
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MSX532
Introduction
(Continued) Option 3: Registered Input with Next-Neighbor Clock as Output
Option 4: Registered Output with Next-Neighbor Clock as Output
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MSX532
Introduction
Symbol
(Continued) TABLE 1. Summary for Programmable I/O Attributes for MSX Devices I/O Port Function Input The external signal is buffered from the Input Port pin to the corresponding Switch Matrix line. Mnemonic IN
Output
The internal signal is buffered from the corresponding Switch Matrix line to the Output Port pin. In this mode an optional output enable (OE) can be selected. The default level is logic 0. The output data inversion mode is available to invert the output signal. The external signal at the I/O Port is registered into an edgetriggered register within the I/O Port. A clock source is required in this mode. An input enable (IE) is available but not required.
OP
Registered Input
RI
Registered Output
The internal signal on the Switch Matrix line is registered by an edge-triggered register within the I/O Port. A clock source is required in this mode. An output enable (OE) is available but not required. The output data inversion mode is NOT available to invert the output signal.
RO
Bidirectional Transceiver
In this mode, the I/O buffer acts as a bidirectional transceiver between the I/O Port pin and the corresponding Switch Matrix line. This mode requires an input enable (IE) and output enable (OE). The output data inversion mode is available to invert the output signal.
BT
Bus Repeater
In the Bus Repeater mode, the I/O Port behaves as a wire (with a non-zero propagation delay). This unique feature patented by Fairchild incorporates as self-sensing circuit to determine signal direction and does not require a direction control signal. When multiple I/O Ports, configured as "Bus Repeater", are connected together through the Switch Matrix to form a single internal node, any (open collector or 3-STATABLE) LOW (logic "0") external signal appearing at any one of the I/O Ports gets repeated (or broadcast) to other I/O Ports. For more details, refer to the Technical Note: "The Bus Repeater Mode"
BR
Pin Side Force 0
In this output mode, the I/O Port pin is forced LOW (logic 0), regardless of the signal on the corresponding switch Matrix line. In this mode an optional output enable (OE) can be selected. In this output mode, the I/O Port pin is forced HIGH (logic 1), regardless of the signal on the corresponding Switch Matrix line. In this mode an optional output enable (OE) can be selected. In this mode, the I/O Port pin is isolated from the Switch Matrix. This is done by 3-STATING both the input and output part of the I/O buffer. In this input mode, the Switch Matrix line is forced LOW (logic 0), regardless of the signal on the corresponding I/O Port. In this mode an optional input enable (IE) can be selected.
F0
Pin Side Force 1
F1
No Connect
NC
Array Side Force 0
A0
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MSX532
Introduction
(Continued) Array Side Force 1 In this input mode, the Switch Matrix line is forced HIGH (logic 1), regardless of the signal on the corresponding I/O Port. In this mode an optional input enable (IE) can be selected. This mode combines Registered Input and buffered Output (OP). This mode requires a clock source (CLK), and input enable (IE) and output enable (OE). A1
OE Px D Q
IE Ax
Bidirectional Transceiver with Register Input
BT & RI
CLK
IE Ax D Q OE Px
Bidirectional Transceiver with Register Output
This mode combines Registered Output (RO) and buffered Input (IE). This mode requires a clock source (CLK), and input enable (IE) and output enable (OE). The output data inversion mode is NOT available to invert the output signal.
BT & RO
CLK
IE Px CLK_IN Q0 OE D0 D1 Q1
Bidirectional Transceiver with CLK_OP Register I/O
Ax
This mode combines Registered Input (RI) and Registered Output (RO). This mode requires a clock source (CLK), and input enable (IE) and output enable (OE). The output data inversion mode is NOT available to invert the output signal.
BT, RI & RO
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MSX532
Introduction
Control Signals
(Continued) four global input enables (IE_0 through IE_3), and four global output enables (OE_0 through OE_3). Each global control signal is available to half of the ports on the MSX device. Table 2 below shows the global control signals that are available to each port.
Every port on the MSX devices has two available global clock inputs, input enables, and output enables. However, not all ports have access to the same global control signals. There are four global clocks (CLK_0 through CLK_3),
TABLE 2. MSX Global Control Signals MSX340 Port Number Ports 0-84 Ports 85-169 MSX532 Port Input/Output Input Output Input Input Number Clock Source 1 Clock Source 2 Enable 1 Enable 2 Ports 0-132 Ports 133-265 CLK_0 CLK_1 CLK_2 CLK_3 CLK_1 CLK_2 CLK_3 CLK_0 IE_0 IE_1 IE_2 IE_3 IE_1 IE_2 IE_3 IE_0 Output Enable 1 OE_0 OE_1 OE_2 OE_3 Output Enable 2 OE_1 OE_2 OE_3 OE_0
Ports 170-254 Ports 266-398 Ports 255-339 Ports 399-531 RapidConfigure Interface
The MSX family of Digital Crosspoint Switches can be configured in either of two ways. Both the JTAG serial programming interface and the RapidConfigure (RC) parallel interface can assign crosspoint connections and configure I/O buffers, but JTAG is a serial input and is slower. JTAG runs reliably up to 8 MHz and requires over twenty cycles to program a single command. The RapidConfigure interface can run at up to 40 MHz and can send a new command on every clock cycle. Systems requiring frequent reconfiguration should be designed to use the RapidConfigure interface. RapidConfigure is a 29 signal parallel interface that effectively flattens the serial JTAG bitstream. Rather than consecutively shifting in twenty or so bits of data to configure an I/O buffer or make a crosspoint connection, all of these bits are driven on the RC lines simultaneously and then latched in by the MSX device in a single cycle. Additionally, the MSX RapidConfigure interface has been enhanced to enable reading back of configuration data from the device. RCA[9:0] = RapidConfigure Address A RCB[9:0] = RapidConfigure Address B RCC[3:0] = RapidConfigure Program Variable C RCI[1:0] RC_EN
RCI[1:0] are dedicated inputs. RC_RDY is a dedicated output. The RC_CLK signal is the strobe that latches write data into the MSX device. It synchronizes the signals driven on to the RC interface and determines the rate at which commands can be loaded into the MSX device. The MSX device latches command data on the falling edge of RC_CLK when RC_EN is asserted. RC Write operations can be repeated on consecutive clocks simply by keeping the RC_EN signal asserted and providing new commands on the RCA, RCB, RCC, and RCI signals. RC Read operations require four AC clock cycles and cannot be performed on back-to-back clocks. RC_EN is an Active LOW signal that enables an RC operation. Back-to-back RC Write operations may be performed by keeping the RC_EN signal asserted. During RC Read operations RC_EN must remain asserted until the cycle is complete. Back-to-back RC Read operations can be executed simply by keeping RC_EN asserted. The MSX device asserts RC_RDY when it has entered the final stage of a read and data out is ready. RC_RDY is asserted on the falling edge of RC_CLK, and de-asserted on the next falling edge. The MSX device will be driving valid read data on the RC interface when RC_RDY is asserted HIGH.
= RapidConfigure Instruction Bits = RapidConfigure Cycle Enable
RC_CLK = RapidConfigure Clock RC_RDY = Read out I/O buffer and connect/disconnect status Signal Description The RC interface supports four types of operations. Two are write operations to the MSX (I/O buffer configuration or crosspoint programming) and two are read operations (I/O buffer and crosspoint configuration read). The RC signals serve different purposes depending upon the type of operation being performed. Most of the signals on the MSX device's RC interface are bi-directional. These signals receive data during write operations. During read operations these pins receive data during the first part of the cycle, and then drive the interface in the final part of the cycle. RCA[9:0], RCB[9:0], and RCC[0] are bi-directional pins. RCC[3:1], RC_CLK, RC_EN, and
FIGURE 4. MSX Switch Configuration Signals The RC interface specifies that the RCI signals be used to determine the type of operation being performed.
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MSX532
Introduction
RCI [1:0] 00 01 10 11
(Continued) TABLE 3. RapidConfigure Input Description
Force Testing Command. Force commands can force a port to drive either a one or a zero to either the pad or crosspoint array. These commands are generally only used for diagnostic testing. I/O Buffer Programming Command. These commands are used to configure a port as an input or output, registered or not, etc. Crosspoint Array Programming Command. Crosspoint connections can be made or broken, or an individual port can be reset. Read and Reset Commands. This setting is used to read back configuration data from an I/O buffer or crosspoint connection information. It can also be used to reset all of the I/O buffers and the crosspoint array.
Read and Reset Commands When RCI[1:0] are equal to 11 a Read or Reset command is executed (see Table 4: Reset Commands). Reset Commands
RCI[1:0]
1 0
RCC[3:0]
3 2 1 0 9 8 7
RCB[9:0]
6 5 4 3 2 1 0 9 8 7
RCA[9:0]
6 5 4 3 2 1 0
110
000000000000000000000
Reset Cmd Options Reset Command Read/Reset Cmd
TABLE 4. Reset Commands (Continued) RCC [2:1] 00 01 10 11 Reserved. This is not a valid command. Reserved. This is not a valid command. Crosspoint Array Reset. This command will reset the entire crosspoint array, breaking any previously existing connections. Crosspoint Array and I/O Buffer Reset. This command resets both the I/O buffers and the crosspoint array as described above. Description
RCC[0], RCB[9:0], and RCA[9:0] have no function during a reset command and must be written as zeroes. Crosspoint Read Commands A crosspoint read is used to check whether two ports are connected through the crosspoint array. The two ports are addressed using RCA[9:0] and RCB[9:0] The MSX device uses RCC[0] to show whether the two ports are connected. It drives RCC[0] HIGH if the two ports are connected, and pulls RCC[0] LOW if the two ports are not connected.
RCI[1:0]
1 0
RCC[3:0]
3 2 1 0 9 8 7 6
RCB[9:0]
5 4 3 2 1 0 9 8 7 6
RCA[9:0]
5 4 3 2 1 0
111000
Port #1
Port #2
Cross Point Read Read Command Read/Reset Cmd
I/O Buffer Read Commands I/O Buffer reads are more complicated (see Table 5: I/O Buffer read Commands). The port to be read is addressed
RCI[1:0]
1 0
using RCA[9:0]. The MSX device uses RCA[9:0] and RCB[9:0] to return all of the configuration data for the particular I/O buffer.
RCA[9:0]
RCC[3:0]
3 2 1 0 9 8 7 6
RCB[9:0]
5 4 3 2 1 0 9 8 7 6
5
4
3
2
1
0
1111000000000000
I/O Buffer Address
I/O Buffer Config Read Read Command Read/Reset Command
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MSX532
Introduction
Signal RCA[0]
(Continued) TABLE 5. I/O Buffer Read Commands
Description RCA[0] is set to one if the I/O buffer is an input. It is zero if the I/O buffer is not configured as an input. Note that an I/O buffer can be configured as an Input, Output, Input and Output (in bi-directional mode), or No Connect. All I/O buffers default to inputs at power-on reset or following a global I/O buffer Reset command, so RCA[0] will read as a one at reset. RCA[0] 0 1 Function I/O buffer not set to input I/O buffer set to input (default)
RCA[1]
RCA[1] is set to a one if the I/O buffer is an output. It is zero if the I/O buffer is not configured as an output. If RCA[1:0] equal 00 the I/O buffer is configured as a No Connect. A No Connect means that the I/O pin of the MSX device is not connected to the crosspoint array. RCA[1] will read as a zero at reset. RCA[1] 0 1 Function I/O buffer not set to output (default) I/O buffer set to output
RCA[2]
RCA[2] is set to a one if the I/O buffer is configured in Bus Repeater Mode. It is zero if the I/O buffer is not in Bus Repeater Mode. Bus Repeater Mode will be disabled by default at reset, so RCA[2] will read as a zero. RCA[2] 0 1 Function I/O buffer not set to Bus Repeater Mode (default) I/O buffer set to Bus Repeater Mode
RCA[3]
RCA[3] is set to a one if the I/O buffer is configured as a registered input and is assigned to use its Input Clock 1. It is zero if the I/O buffer is not using Input Clock 1. Input Clock 1 for each I/O buffer will vary depending upon the quadrant of the device in which it resides. RCA[3] will read as a zero at reset. RCA[3] 0 1 Function I/O buffer not set to registered input mode (default) I/O buffer set to registered input mode
RCA[4]
RCA[4] is set to a one if the I/O buffer is configured as a registered input and is assigned to use its Input Clock 2. It is zero if the I/O buffer is not using Input Clock 2. As with Input Clock 1, the source changes depending upon the quadrant of the device in which the I/O buffer resides. RCA[4] will read as a zero at reset. RCA[4] 0 1 Function I/O buffer not using Input Clock Source 2 in RI mode (default) I/O buffer using Input Clock Source 2 in RI mode
RCA[5]
RCA[5] is set to a one if the I/O buffer is configured as a registered input and assigned to use Next Neighbor Clocking. It is zero if Next Neighbor Clocking is disabled. Next Neighbor Clocking allows the I/O buffer to be registered using the next higher numbered Port number signal as its input clock source. Port 100 on the MSX devices can use the signal from Port 101 for its input clock if this mode is enabled. Port 531's Next Neighbor is Port 0. Next Neighbor Clocking will be disabled by default at reset, so RCA[5] will read as a zero. RCA[5] 0 1 Function I/O buffer not using Next Neighbor Clock in RI mode (default) I/O buffer using Next Neighbor Clock in RI mode
RCA[6]
RCA[6] is set to a one if the I/O buffer is configured as a registered output and is assigned to use its Output Clock 1. It is zero if the I/O buffer is not using Output Clock 1. As with Input Clock 1 and 2, the Output Clocks will vary depending upon the quadrant of the device in which the I/O buffer resides. In the case of the MSX devices, the Output Clock 1 and Input Clock 1 for each I/O buffer have the same source, and the Output Clock 2 and Input Clock 2 do as well. RCA[6] will read as a zero at reset. RCA[6] 0 1 Function I/O buffer not using Output Clock Source 1 in RO mode (default) I/O buffer using Output Clock Source 1 in RO mode
RCA[7]
RCA[7] is set to a one if the I/O buffer is configured as a registered output and is assigned to use its Output Clock 2. It is zero if the I/O buffer is not using Output Clock 2. As with Output Clock 1, the source changes depending upon the quadrant of the device in which the I/O buffer resides. RCA[7] will read as a zero at reset. RCA[7] 0 1 Function I/O buffer not using Output Clock Source 2 in RO mode (default) I/O buffer using Output Clock Source 2 in RO mode
I/O Buffer Read Commands (Continued)
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MSX532
Introduction
Signal RCA[8]
(Continued)
Description RCA[8] is set to a one if the I/O buffer is configured as a registered output and is assigned to use Next Neighbor Clocking. It is zero if Next Neighbor Clocking is disabled. Next Neighbor Clocking allows the I/O buffer to be registered using the next higher numbered Port number signal as its output clock source. Port 100 on the MSX devices can use the signal from Port 101 for its output clock if this mode is enabled. Port 531's Next Neighbor is Port 0. Next Neighbor Clocking will be disabled by default at reset, so RCA[8] will read as a zero. RCA[8] 0 1 Function I/O buffer not using Next Neighbor Clock in RO mode (default) I/O buffer using Next Neighbor Clock in RO mode
RCA[9]
RCA[9] is set to a one if the I/O buffer is assigned to use Input Enable 1. It is zero if the I/O buffer is not using Input Enable 1. All bi-directional I/O buffers must use one of the dedicated input enable pins (IE_0, IE_1, IE_2, or IE_3) to enable the I/O buffer to drive data into the crosspoint array. As with the dedicated clock pins, each I/O buffer can access two input enable signals, which will vary depending upon the quadrant of this chip in which the I/O buffer resides. RCA[9] will read as a zero at reset. RCA[9] 0 1 Function I/O buffer not using Input Enable Source 1 (default) I/O buffer using Input Enable Source 1
RCB[0]
RCB[0] is set to a one if the I/O buffer is assigned to use Input Enable 2. It is zero if the I/O buffer is not using Input Enable 2. RCB[0] will read as a zero at reset. RCB[0] 0 1 Function I/O buffer not using Input Enable Source 2 (default) I/O buffer using Input Enable Source 2
RCB[1]
RCB[1] is set to a one if the I/O buffer is assigned to use Output Enable 1. It is zero if the I/O buffer is not using Output Enable 1. All bi-directional I/O buffers must use one of the dedicated output enable pins (OE_0, OE_1, OE_2, or OE_3) to enable the I/O buffer to drive the pin of the device. As with the dedicated clock pins, each I/O buffer can access two output enable signals, which will vary depending upon the quadrant of the chip in which the I/O buffer resides. RCB[1] will read as a zero at reset. RCB[1] 0 1 Function I/O buffer not using Output Enable Source 1 (default) I/O buffer using Output Enable Source 1
RCB[2]
RCB[2] is set to a one if the I/O buffer is assigned to use Output Enable 2. It is zero if the I/O buffer is not using Output Enable 2. RCB[2] will read as a zero at reset. RCB[2] 0 1 Function I/O buffer not using Output Enable Source 2 (default) I/O buffer using Output Enable Source 2
RCB[6:3] RCB[6:3] are reserved. RCB[7] RCB[7] is set to a one if the I/O buffer is configured as an inverted output. It is zero if the I/O buffer is not configured as an inverted output. The output of any I/O buffer may be inverted so long as it is not a registered output or running in Bus Repeater Mode. RCB[7] will read as a zero at reset. RCB[7] 0 1 RCB[8] Function I/O buffer not configured as inverted output (default) I/O buffer configured as inverted output
RCB[8] is set to a one if the I/O buffer is configured as a registered input and is using an inverted input clock source. It is zero if it is not using an inverted input clock. Inputs can use any of the three clock sources described above and may invert that clock if desired. RCB[8] will read as a zero at reset. RCB[8] 0 1 Function I/O buffer not using inverted clock source in RI mode (default) I/O buffer using inverted clock source in RI mode
RCB[9]
RCB[9] is set to a one if the I/O buffer is configured as a registered output and is using an inverted output clock source. It is zero if it is not using an inverted output clock. Outputs can use any of the three clock sources described above and may invert that clock if desired. RCB[9] will read as a zero at reset. RCB[9] 0 1 Function I/O buffer not using inverted clock source in RO mode (default) I/O buffer using inverted clock source in RO mode
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MSX532
Introduction
(Continued) Crosspoint Programming Connections between ports through the crosspoint array can be quickly made or broken using the RC interface. The two ports to be connected or disconnected are addressed
RCI[1:0]
1 0
using RCA[9:0] and RCB[9:0]. RCC[1] controls whether a connection is made or broken. The two ports are connected when RCC[1] is set to zero, and disconnected when RCC[1] is set to one
RCA[9:0]
RCC[3:0]
3 2 1 0 9 8 7 6
RCB[9:0]
5 4 3 2 1 0 9 8 7 6
5
4
3
2
1
0
1001
0
Port #1
Port #2
Connect/Disconnect (0-Connect, 1-Disconnect) Crosspoint Program
Unlike I/O buffer programming commands, which take effect immediately upon execution of the command, crosspoint connections will only be made if the UPDATE signal is asserted HIGH. The crosspoint programming command loads the Loading SRAM cell in the selected crosspoint array location with a one (in the case of a new connection) or a zero (to break an existing connection). If the UPDATE signal is asserted, the Loading SRAM cells contents are immediately transferred to the Active SRAM cell and the connection is made or broken. However, if the UPDATE signal is held LOW, the new connection will not be made.
The UPDATE signal can be used to control when the switch matrix connections are reconfigured. I/O Buffer Configuration Programming Each port can be fully configured in a single RapidConfigure cycle. The figure below shows how an I/O buffer is programmed using all of the signals on the RC interface. The following table shows how each control bits (RCC[3:0] and RCB[9:0]) are used. During an I/O buffer programming command the RCA[9:0] signals address the port to be programmed (see Table 6: I/O buffer Programming Commands)
RCA[9:0]
RCI[1:0]
1 0
RCC[3:0]
3 2 1 0 9 8 7 6
RCB[9:0]
5 4 3 2 1 0 9 8 7 6
5
4
3
2
1
0
01
I/O Buffer Address
Inverted Output Clock Inverted Input Clock Invert Output Input Clock Source Output Clock Source Input Enable Select Output Enable Select Input/Output Select Bus Repeater Enable I/O Buffer Configuration
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Introduction
Signal RCC[3]
(Continued) TABLE 6. I/O Buffer Programming Commands Description
Bus Repeater Enable. Setting this bit to a one enables the I/O buffer to operate in Bus Repeater Mode, a special bi-directional mode. When zero the I/O buffer will not operate in Bus Repeater Mode. When programming an I/O buffer to use Bus Repeater Mode, all of the other control bits must be set to zeroes. Attempting to combine other I/O buffer options with Bus Repeater Mode may lead to unpredictable results.
RCC[2:1] Input/Output Select. These two bits are used to configure the I/O buffer as an input, output, input/output (bidirectional mode), or no connect. When operating in bi-directional mode it is critical that the port be assigned input and output enables so that it can be 3-STATED appropriately to avoid contention. RCC[2:1] 00 01 10 11 RCC[0] and RCB[9] Function No Connect Input Output Input / Output for Bi-Directional Mode
Output Enable Select. These two bits are used to select from the two available active LOW global output enables. The output will be allowed to drive when its assigned output enable is asserted. An output port will be 3STATED when its assigned output enable is de-asserted. When both output enables are selected, the two available active LOW output enable signals are AND'ed together to form the port's combined output enable signal. RCC[0], RCB[9] 00 01 10 11 Function No Output Enable Selected Output Enable 1 Output Enable 2 Both Output Enables
RCB[8:7] Input Enable Select. These bits are used to assign a port one of the two available global input enable signals. An input port will drive into the crosspoint array when its assigned input enable is asserted. When both input enables are selected, the two available input enable signals are OR'ed together to form the port's combined input enable signal. RCB[8:7] 00 01 10 11 Function No Input Enable Selected Input Enable 1 Input Enable 2 Both Input Enables
RCB[6:5] Output Clock Source. These bits are used to select a clock source for a registered output port. Each I/O buffer can select from one of two global clock inputs, or can use Next Neighbor Clocking. Next Neighbor Clocking uses the signal on the next higher numbered port as a clock source. If no clock source is assigned to an output port, it will operate in flow-through mode. RCB[6:5] 00 01 10 11 Function No Output Clock Source Selected Output Clock Source 1 Output Clock Source 2 Next Neighbor Output Clock Source
RCB[4:3] Input Clock Source. These bits are used to select a clock source for a registered input port. Each I/O buffer can select from one of two global clock inputs, or can use Next Neighbor Clocking. Next Neighbor Clocking uses the signal on the next higher numbered port as a clock source. If no clock source is assigned to an input port, it will operate in flow-through mode. RCB[6:5] 00 01 10 11 RCB[2] Function No Input Clock Source Selected Input Clock Source 1 Input Clock Source 2 Next Neighbor Input Clock Source
Invert Output. If an output port is programmed with this bit set to a one, the output of the port will be inverted. If this bit is zero, the output will not be inverted. Outputs may not be inverted when operating in Bus Repeater Mode or in registered output mode. Inverted Input Clock. When this bit is set to a one, the registered input port's selected clock source will be inverted. When zero the input clock source will not be inverted.
RCB[1]
13
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MSX532
Introduction
Signal RCB[0]
(Continued) Description
Inverted Output Clock. When this bit is set to a one, the registered output port's selected clock source will be inverted. When zero the output clock source will not be inverted. I/O Buffer Programming The JTAG I/O Buffer Data Register where data is held, is used to program the I/O buffer. This register is used with the JTAG interface only. The JTAG I/O buffer data register is 20 bits wide. Power on reset, RapidConfigure reset, Hardware reset, and JTAG reset programs all Ports as inputs. JTAG can be reset via the TRST pin or by clocking five consecutive ones to the TMS pin. The HW_RST (hardware reset) pin resets and breaks all connections in the Crosspoint Array to all no-connects, and the I/O buffers to inputs. Table 7 lists the bits and their function in JTAG mode. These are internal bits as shifted into the I/O buffer data register for I/O buffer programming.
JTAG Interface The dedicated JTAG TAP interface is designed in compliance with the IEEE-1149.1. The standard interface has five pins: Test Data Out (TDO), Test Mode Select (TMS), Test Data In (TDI), Test Reset (TRST), and Test Clock (TCK) which allow Boundary Scan Testing as well as device configuration and verification. Data on the TDI and TMS pins are clocked into the device on the rising edge of the TCK signal, while the valid data appears on the TDO pin after the falling edge of TCK. For more detailed information on JTAG programming, refer to the MSX Family Register Programming Manual.
TABLE 7. I/O Buffer Programming Bit Functions Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 I/O Buffer Function Input (IN) Output (OP) Bus Repeater (BR) Reg In Clock 1 Reg In Clock 2 Reg In Clock Neighbor Reg Out Clock 1 Reg Out Clock 1 Input Enable 1 (IE_1) Input Enable 2 (IE_2) Input Pin Data to Drive Array Output Array Data to Pin Low Array Signal, Drive Pin LOW Low Pin Signal, Drive Array LOW Selects Reg. In I/O Buffer, Clock 1 Selects Reg. In I/O Buffer, Clock 2 Selects Reg. In I/O Buffer, Neighbor Selects Reg. Out I/O Buffer, Clock 1 Selects Reg. Out I/O Buffer, Clock 2 Select Input Enable 1 (Note 1) Select Input Enable 2 (Note 1) Description
Reg Out Clock Neighbor Selects Reg. Out I/O Buffer, Neighbor
Output Enable 1 (OE_1) Select Output Enable 1 (Note 2) Output Enable 2 (OE_2) Select Output Enable 2 (Note 2) Force 1 Force 0 Array 1 Array 0 Invert Output Invert Input Clock Invert Output Clock Force I/O Buffer Output Pin to a 1 Force I/O Buffer Output Pin to a 0 Force I/O Buffer Array to a 1 Force I/O Buffer Array to a 0 Output data is inverted. This operation is invalid in Bus Repeater mode and Register Output mode Invert the Clock to the Input Register Invert the Clock to the Output Register
Note 1: If both IE_1 and IE_2 are selected, the two are assigned an OR function to form the IE. Either can be "1" to enable the input. Note 2: If both OE_1 and OE_2 are selected, active LOW signals are assigned an AND function to form the resulting OE. Either can be "0" to enable the output.
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MSX532
Introduction
(Continued) JTAG Architecture and Shift Registers
FIGURE 5. MSX JTAG Architecture
FIGURE 6. JTAG State Machine 15 www.fairchildsemi.com
MSX532
Introduction
Bit Number Bit Name 15 13
(Continued) TABLE 8. JTAG Input Format Instruction 14 12 13 11 12 10 Control 11 C1 10 C0 9 A9 8 A8 7 A7 6 A6 Address 5 A5 4 A4 3 A3 2 A2 1 A1 0 A0
TABLE 9. JTAG Instructions 15 14 13 12 1 1 1 1 Bypass Instruction Description Places device in a mode to pass TDI data to TDO with one clock delay. Used for programming and testing devices through serial connected JTAG controls. Sets and clears the control bit A0 (LSB) Resets I/O buffers for the Ports to Input and clear all Ports to Disconnect. The device ID is serialized out to TDO. The Instruction serialized out is the RESET Instruction during the Instruction phase. Update is forced to the crosspoint array Serialize the device ID and revision history out to TDO. ID for the MSX is 0x0000A89F. Set the 10-bit JTAG Address Register with the lower ten bits of the JTAG Instruction Register. The lower ten bits of the JTAG Address Register become the 'B' Address for Crosspoint Access. Read or Write the crosspoint addressed by the lower ten bits of the JTAG Instruction (A Address) and the JTAG Address Register or Address Counter (B Address). Read data is shifted out on TDO. C1 C0 = 0 0 Read Switch with A and B Address. Increment 'B' address with each ShiftDR. C1 C0 = 0 1 Connect switch at location Addressed with A and B. Increment 'B' address with each ShiftDR. Activate with UpdateDR. C1 C0 = 1 0 Disconnect switch at location Addressed with A and B. Increment 'B' address with each ShiftDR. Activate with UpdateDR. C1 C0 = 1 1 Force update of Switch Array Shadow register. Activate with UpdateDR. 1 0 0 1 Disconnect a Port in the Crosspoint Array 0 Clear the Crosspoint Array 1 Shift the IO Buffer Data Register 0 Shift out the I/O buffer Copy Register 1 Access an I/O buffer Disconnect all Ports from the Port Addressed by the lower ten bits of the JTAG Instruction. The addressed port is reset to disconnect. The programmed state of the I/O buffer is not changed. Clear the crosspoint array at no-connect. Leave the I/O buffers unchanged. Shift twenty bits of data into and out of the I/O buffer Data register. The data is used to program the I/O buffers. Parallel shift twenty bits into I/O buffer Copy Register. Shifts twenty bits of data out of the I/O buffer Copy Register. Data is either the I/O buffer Data register shifted in by instruction 0111 or the last JTAG I/O buffer Read Data. Read or write the I/O buffer addressed with the lower ten bits of the JTAG Instruction. Read data is placed in the twenty-bit I/O buffer Copy Register. Write Data for the I/O buffer is from the I/O buffer Data Register. C1 C0 = 0 0 Read an I/O buffer date into the Copy Register. C1 C0 = 0 1 Write an I/O buffer with data in I/O buffer Data Register. 0 0 1 0 0 1 0 Not used. 1 Test mode only Fairchild only - internal test mode to test RapidConfigure through JTAG. for programming device with RapidConfigure through JTAG 0 Crosspoint Array Write Testing, Instruction Address = Lower Limit = A, Address Register = Upper Limit = B. Write one location per ShiftDR C1 = 1, C0 = 1 Connect all ports in address range C1 = 1, C0 = 0 Connect Pattern=A[1] XOR B[1] C1 = 0, C0 = 0 Connect Pattern=A[4] C1 = 0, C0 = 1 Connect Pattern = NOT (A[1] XOR B[1]). Compliment address limits, Address is complimented to test A-High Port to B-Low Port connections. Other three patterns test opposite. The number of cycles = (Sum of (X = 1), where X = Low Limit to X = High Limit) - 1 0 Sample/Preload EXTEST 1 Sample/Preload EXTEST External scan tests for interconnect testing. External scan tests for interconnect testing. 16
1 1
1 1
1 0
0 Control Bit 1 IO Buffer and Crosspoint Array Reset, Device ID out 0 Device ID out 1 Set the JTAG Address Register 0 Access the Crosspoint Array and Update Array
1 1
1 0
0 1
1
0
1
1 0
0 1
0 1
0
1
1
0
1
0
0
0
1
0 0
0 0
0 0
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MSX532
Introduction
(Continued) Device Reset Options At power-on, all MSX532 I/O buffers are set as flowthrough inputs (IN) with input enable ON, and the switch matrix set to all No Connects (NC). The RapidConfigure reset, hardware reset, and JTAG reset functions will program the I/O buffers to flow-through input (IN) mode with input enable ON, and each Loading SRAM cell in the Switch Matrix is set to No Connect. An UPDATE Device Reset Options Programming Interface Reset Method Power-on Reset HW_RST (Low Pulse)
signal is required to complete the operation and set the Active SRAM cells to No Connect. The JTAG interface can be reset via the TRST pin or by clocking five consecutive one to the TMS pin. The hardware reset pin can be done accomplished through the HW_RST pin (Active LOW). RC reset can be accomplished by applying the RC Instruction 1101 to the RCI[3:0] pins.
I/O Port IN IN
Switch Matrix NC
RCE Mode Control
JTAG TAP
Hardware Reset
1 (RC Enabled) TLR (Note 3) TLR TLR TLR TLR Unchanged Unchanged Unchanged
NC (Note 4) 1 (RC Enabled) Unchanged Unchanged Unchanged Unchanged
JTAG Reset
1. Low Pulse on TRST 2. TMS High for 5 SCLK Cycles 3. Device Reset (Instruction 1101)
Unchanged Unchanged Unchanged Unchanged IN IN
NC (Note 3) 1 (RC Enabled) NC (Note 3) 1 (RC Enabled)
4. Reset Crosspoint Array (Instruction 1101) Unchanged NC (Note 3) RapidConfigure Reset 1. Device Reset (Instruction 1101) 2. Reset Crosspoint Array (Instruction 0010) Unchanged NC (Note 3)
Note 3: NC = No Connect. Each Loading SRAM cell in the Switch Matrix is updated to No Connect. An UPDATE signal is required to complete the operation and set the Active SRAM cells to No Connect. Note 4: TLR = Test Logic Reset State.
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MSX532
Pin Description
Pin Name Type Description P[531:000] Bi-directional Input/Output Signals. OE[3:0] Input Global Output Enables. Each output enable can control two of the four I/O banks. Signal OE_0 OE_1 OE_2 OE_3 IE[3:0] Input Signal IE_0 IE_1 IE_2 IE_3 UPDATE CLK[3:0] Input Input Global Update Global Clocks. Each clock can control two of the four I/O banks. Signal CLK_0 CLK_1 CLK_2 CLK_3 HW_RST RCE Input Input MSX532 Connected I/O's P399-P531, P000-P132 P000-P132, P133-P265 P133-P265, P266-P398 P266-P398, P399-P531 MSX532 Connected I/O's P399-P531, P000-P132 P000-P132, P133-P265 P133-P265, P266-P398 P266-P398, P399-P531 MSX532 Connected I/O's P399-P531, P000-P132 P000-P132, P133-P265 P133-P265, P266-P398 P266-P398, P399-P531
Global Input Enables. Each input enable can control two of the four I/O banks.
Hardware Reset. RapidConfigure Mode Select Programing mode is determined at power up or HW_RST 0 = JTAG Mode (RapidConfigure Disabled) 1 = RapidConfigure Mode (JTAG, I/O buffer, Crosspoint Programming Disabled)
Note: Device can be reconfigured from JTAG to RC or from RC to JTAG in the JTAG mode without HW_RST or power up. In RapidConfigure mode the programming of the I/O buffers and crosspoint array through JTAG is disabled, but the JTAG port can still be used for boundary scan testing.
RC Pins RC_CLK RC_EN RCA[9:0] RCB[9:0] RCC[0] RCC[3:1] RCI[1:0] RC_RDY TCK TDI TDI TMS TRST VDD VSS Input Input RapidConfigure Clock. RapidConfigure Cycle Enable.
Bi-directional RapidConfigure Address A. Bi-directional RapidConfigure Address B. Bi-directional RapidConfigure Program Variable C. Input Input Output Input Input Output Input Input Power Ground RapidConfigure Program Variable C. RapidConfigure Instruction Bits. Read Out I/O Buffer and Connect/Disconnect Status. JTAG Pins JTAG Test Clock. JTAG Test Data In. JTAG Test Data Out. JTAG Test Mode Select. JTAG Test and JTAG Scan Reset. Power and Ground Pins +3.3V power for the chip. Ground for the chip. Tie these pins to system ground.
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MSX532
Absolute Maximum Ratings(Note 5)
Supply Voltage VDD Supply Voltage (Inputs) VIN (Note 6)(Note 7) Junction Temperature TJ Storage Temperature TSTG Maximum Power Dissipation PMAX Electrostatic Discharge ESD (Note 8) -0.3V to +5.5V +150C -65C to +150C 10.5W 1500V -0.3V to +3.6 V
Recommended Operating Conditions
Supply Voltage VDD Operating Temperature TA +3.0V to +3.6V 0C to +70C
Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 6: A maximum undershoot of 2V for a maximum duration of 20 ns is acceptable. Overshoot to 5.5V is acceptable. Note 7: All inputs are 5V tolerant with the VDD pin at 3.3V. Note 8: Measured using Human Body Model.
Pin Capacitance
Symbol CCLK CPORT Input Capacitance
(Note 9)
Parameter Limits 10.0 8.0 Units pF pF
I/O Signal Port Capacitance
Note 9: Capacitance measured at 25C. Sample tested only.
DC Electrical Characteristics (TA = 0C to 70C, VDD = 3.3V 10%)
Symbol VIH VIL VOH Parameter HIGH Level Input LOW Level Input HIGH Level Output Conditions Ports are 5V Tolerant Ports are 5V Tolerant VDD = Min VDD = 3.00 IOH = -4 mA VOL LOW Level Output VDD = Min VDD = 3.00 IOL = 8 mA ILIH, ILIL ILOZ IOSH IOSL Input Leakage for Non-programmable I/O pins 3-STATE Leakage Output OFF State Short Circuit Current, Out = HIGH Short Circuit Current, Out = LOW IDDQ QDDD (Note 10) Quiescent Supply Current Dynamic Supply Current VDD = Max 0.0 < In < VDD VDD = Max 0.0 < In < VDD VDD = Max V0 = GND VDD = Max V0 = VDD Supply Current VDD = Max VDD = Max. No Load, One Input Cycling @ 50% Duty Cycle 96.0 0.375 mA mA/MHz +5.0 -600 +5.0 -100 -80.0 80.0 A A mA mA 0.4 V 2.4 VDD + 0.3 V Min 2.1 -0.3 Max 5.25 0.8 Units V V
Note 10: See Power Consumption section for dynamic power consumption calculation.
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MSX532
AC Electrical Characteristics (TA = 0C to 70C, VDD = 3.3V 10%)
Symbol RDATA fRIO tW_RIO tS_RI tS_RO tH_RI tH_RO tCO_RO tCO_RI tPHL, tPLH tMC Delta tW+ tWtSK tPZH_IT, tPZL_IT tPZH_OT, tPZL_OT tPZH_OT, tPZL_OT tRC tW+_RC tW-_RC tS_RC tH_RC tP_RC tP_RD tP_UD fJTAG tW_JTAG tS_JTAG tH_JTAG tP_JTAG RapidConfigure Address Setup to RC Clock RapidConfigure Address Hold Time to RC Clock Read Back Access Time RC_RDY to Readback Data Update of Crosspoint to Data Out JTAG Clock Frequency (TCK) JTAG Clock Pulse Width (TCK) at 8 MHz Cycle JTAG Setup Time JTAG Hold Time JTAG Clock to Output Data Valid (TDO) 48.0 4.0 0.0 10.0 1.0 4.0 9.0 4.0 10.0 8.0 72.0 ns ns ns ns ns MHz ns ns ns ns RapidConfigure Clock Period RapidConfigure Clock Pulse Width 20.0 8.0 ns ns Output Enable to High Z State 7.5 ns Output Enable to Valid Data 7.5 ns NRZ Data Rate Registered Input/Output Clock Frequency Registered Clock Pulse Width, HIGH or LOW Registered Input Setup Time to Clock Registered Output Setup Time to Clock Registered Input Clock to Hold Data Registered Output Clock to Hold Data Registered Output Clock to Data Out Valid Registered Input Clock to Data Out Valid One Way Signal Propagation Delay, Fanout = 1 Additional Delay Per Output Multicast (MC) Mode Input Flow-through Positive Pulse Width Input Flow-through Negative Pulse Width Skew Input Enable to Valid Data 6.0 6.0 4.0 20.0 ns ns 3.0 5.0 9.5 0.0 0.0 11.0 24.0 20.0 2.0 Parameter Min Max 150 75.0 Units Mb/s MHz ns ns ns ns ns ns ns ns ns
Refer to Figure 7 for AC test conditions.
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MSX532
Test Circuit and Timing Diagrams
FIGURE 7. Test Circuit and Waveform Definition
FIGURE 8. Registered Input and Registered Output Mode Timing (ICLK and OCLK Synchronized)
FIGURE 9. Registered Input Timing Mode
FIGURE 10. Registered Output Timing Mode
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MSX532
Test Circuit and Timing Diagrams
(Continued)
FIGURE 11. I/O Port Timing (Flow-through Mode)
FIGURE 12. Input Enable Timing (Flow-through Mode)
FIGURE 13. Output Enable Timing
FIGURE 14. JTAG Timing
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MSX532
Test Circuit and Timing Diagrams
(Continued)
FIGURE 15. RapidConfigure I/O Buffer or Crosspoint Read and Write Cycles
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MSX532
Test Circuit and Timing Diagrams
(Continued)
tH_RC
RC_CLK RC_EN RC_RDY RCI[1:0] RCC[3:0] RCB[9:0] RCA[9:0]
RC Read Cmd latched on falling edge of RC_CLK
Reset Cmd Data Reset Cmd Data Cmd Data Cmd Data
FIGURE 16. RapidConfigure Reset Command Cycle
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MSX532
Package and Pinout
MSX532 [792 TBGA Package] Pinout
1 Vss A Vss Vss B Vss Vss C Vss Vss D E F RCA8 Vss G RCB3 RCB7 H RCB6 Vss J K L M P523 Vss N P517 P512 P P513 Vss R P506 P502 T P504 Vss U P499 P495 V P494 P488 W P489 P485 Y P484 Vss AA P482 P479 AB P476 P475 AC P473 P468 AD P466 Vss AE P464 P458 AF P459 P450 AG P454 P451 AH P449 P443 AJ P447 P441 AK P440 P433 AL P436 P432 AM P430 Vss AN P424 AP P422 Vss AR P421 Vss AT AU Vss Vss AV Vss Vss AW Vss 1 2 3 Vss 4 5 P407 6 7 P400 8 9 P390 10 11 P383 12 13 P372 14 15 P362 16 17 P355 18 19 P345 20 21 P338 22 23 P329 24 25 P320 26 27 P311 28 29 P300 30 31 P291 32 33 P284 34 35 Vss 36 37 Vss 38 39 Vss Vss P415 P414 P406 P403 P394 P393 Vss P384 P377 P374 P368 P364 P359 P356 P348 P349 Vss Vss P347 P344 P339 P334 P337 P335 P328 Vss P326 P324 P318 P317 P319 P314 P308 Vss P309 P307 P301 Vss P298 P294 P288 P289 P287 P280 P278 Vss Vss Vss Vss Vss AW Vss Vss AV Vss OE_2# Vss CLK_2 CLK_ P412 P401 P392 P382 P375 P365 P354 3 Vss P410 Vss Vss P387 Vss P366 Vss Vss OE_3 # Vss Vss Vss Vss Vss P417 P416 P408 IE_3 P409 P402 P397 P405 P396 P395 P386 Vdd P388 P385 P379 Vdd P378 P376 P369 Vdd P371 P367 P358 Vdd P360 P357 P351 Vdd P350 P346 P342 Vdd P343 P336 P333 Vdd P332 P327 P325 Vdd P322 P316 P315 Vdd P313 P306 P305 Vdd P304 P299 P295 P297 P292 P286 P285 Vdd P282 P281 P276 P279 Vss Vss Vss Vss Vss P275 Vss AU P273 Vss AT P418 P419 Vss Vdd P411 P404 P399 Vdd P389 Vdd P381 Vdd P370 Vdd P361 Vdd P352 Vdd P340 Vdd P330 Vdd P323 Vdd P312 Vdd P302 P296 P293 Vdd P283 Vdd Vss P274 P277 P270 P266 AR P429 P420 P427 Vdd P423 P413 P398 P391 P380 P373 P363 P353 P341 P331 P321 P310 P303 P290 IE_2 P271 Vdd P269 P272 P264 P265 AP P426 P428 P425 Vdd Vdd P268 P262 P267 P260 Vss AN P431 P434 Vdd Vss P258 Vdd P257 P263 P254 P261 AM P437 P439 P435 Vdd Vdd P259 P253 P256 P250 P255 AL P438 P445 Vdd Vss P249 Vdd P246 P252 P244 P251 AK P444 P446 P442 Vdd Vdd P248 P245 P247 P243 Vss AJ P448 P452 Vdd Vss P240 Vdd P239 P242 P237 P241 AH P455 P456 P453 Vdd Vdd P238 P234 P236 P233 Vss AG P457 P463 Vdd P461 P230 Vdd P228 P235 P226 P232 AF P462 P465 P460 Vdd P467 P470 Vdd Top View Vdd P231 P469 P223 Vdd P227 P229 P221 P225 P224 Vss AE P219 P222 AD P472 P474 P471 Vdd Vdd P220 P217 P218 P214 Vss AC P477 P483 Vdd P480 P213 Vdd P210 P216 P209 P215 AB P478 P487 P481 Vdd Vdd P212 P206 P211 P204 Vss AA P486 P490 Vdd P493 P200 Vdd P203 P207 P205 P208 Y P491 P497 P492 Vdd Vdd P201 P197 P202 P199 Vss W P496 P501 Vdd P503 P190 Vdd P193 P196 P194 P198 V P498 P507 P500 Vdd Vdd P192 P186 P195 P188 Vss U P505 P508 Vdd P510 P180 Vdd P182 P189 P185 P191 T P509 P514 P511 Vdd P515 P519 Vdd P520 P516 P524 P518 P527 RCC0 RCC2 RCB8 RCE RCI0 RC_CLK RC_E RCI1 RCC3 P526 N# P529 P530 UPDAT P531 P528 E P521 P525 P522 P150 P156 P157 P162 P163 P165 Vdd Vdd P173 P172 Vdd Vdd P183 P177 P184 P175 P179 P178 P187 R P168 P174 P176 P181 P P169 P171 Vss N P159 P164 P167 P170 M P153 P158 P160 P166 L P154 P161 K RCC1 RCB4 RCB9 Vdd Vdd P152 P147 P155 P148 Vss J RCB5 RCB0 Vdd RCA7 P138 Vdd P140 P149 P144 P151 H RCB2 RCA4 RCA9 Vdd Vdd RCA1 Vss Vss Vss Vss TMS 2 3 Vss 4 5 6 7 Vss P00 P00 7 2 P00 P00 6 3 P00 4 TCK 8 9 P01 2 P01 3 P01 0 P011 P01 4 P008 P00 9 Vdd P019 Vdd Vdd 10 11 Vss P016 P02 2 P017 P02 0 P015 P02 1 P01 8 P02 6 P02 4 P02 5 P02 3 Vdd P027 Vdd 12 13 P03 3 P03 1 P03 0 P02 8 P02 9 14 15 Vss P03 7 P03 4 P044 P040 P045 P041 P048 P051 P054 P058 16 17 P050 P055 P061 P060 P066 18 19 Vss P065 P064 P070 P077 20 21 Vss P071 P074 P081 P084 22 23 P075 P080 P085 P091 P094 24 25 Vss P089 P095 P100 P104 26 27 P092 P098 P102 P108 P115 28 29 Vss P109 P113 P118 P122 30 31 P112 P119 P123 P126 P133 Vss Vss Vss P134 Vss P137 Vdd P141 P136 P143 IE_1 P142 E Vdd P036 Vdd Vdd P046 Vdd Vdd P057 Vdd Vdd P068 Vdd Vdd P078 Vdd Vdd P088 Vdd Vdd P099 Vdd Vdd P106 Vdd Vdd P116 Vdd Vdd P129 P135 OE_1# CLK_1 P145 F P139 P146 G 32 33 Vss P125 P128 P131 Vss Vss Vss D 34 35 Vss Vss Vss Vss Vss C 36 37 Vss Vss Vss B 38 39 Vss A TRST # P00 Vss HW_RS 0 Vss T# P00 CLK_ 1 0 IE_0 Vss
RC_R P00 DY TDO 5 RCA6 Vss RCA0 OE_0 Vss Vdd RCA3 RCB1 RCA2 # TDI RCA5
P03 P063 P072 P083 P130 P052 P042 P090 P101 P111 P120 5 P067 P076 P059 P049 P096 P105 P039 Vss P114 P124 P087 P03 P062 P073 P082 P132 P053 P093 P103 P110 P043 P121 2 P038 P069 P079 P056 P047 P097 P107 P117 P127 P086 Vss
MSX532 in 792 TBGA
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MSX532
Package and Pinout
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 Ball Name VSS VSS VSS VSS TRST P000 VSS P007 P012 P016 VSS P026 P033 P037 VSS P044 P050 P055 VSS P065 VSS P071 P075 P080 VSS P089 P092 P098 VSS P109 P112 P119 VSS P125 VSS VSS VSS VSS VSS Ball B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39
(Continued) TABLE 10. MSX532 Pinout By Ball Sequence Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 Ball Name VSS VSS VSS VSS IE_0 TMS P003 P004 P010 P015 P020 P025 P030 P035 P041 P042 P048 P052 P058 P063 P066 P072 P077 P083 P084 P090 P094 P101 P104 P111 P115 P120 P122 P130 P133 VSS VSS VSS VSS Ball D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 Ball Name VSS RCA1 VSS VSS VSS RC_RDY TCK P005 P011 P014 P021 P023 P028 P032 P039 P043 P049 P053 P059 P062 P067 P073 P076 P082 P087 P093 P096 P103 P105 P110 P114 P121 P124 P132 VSS VSS VSS IE_1 VSS Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 Ball Name RCA6 RCA3 RCA0 VSS VSS OE_0 TDO VDD P008 VDD P018 VDD P029 VDD P038 VDD P047 VDD P056 VDD P069 VDD P079 VDD P086 VDD P097 VDD P107 VDD P117 VDD P127 P135 VSS VSS P134 OE_1 P142 Ball F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 Ball Name RCB1 RCA8 RCA5 RCA4 RCA2 VDD TDI VDD P009 VDD P019 VDD P027 VDD P036 VDD P046 VDD P057 VDD P068 VDD P078 VDD P088 VDD P099 VDD P106 VDD P116 VDD P129 VDD P137 P136 CLK_1 P139 P145
Ball Name VSS VSS VSS CLK_0 HW_RST P001 P002 P006 P013 P017 P022 P024 P031 P034 P040 P045 P051 P054 P061 P060 P064 P070 P074 P081 P085 P091 P095 P100 P102 P108 P113 P118 P123 P126 P128 P131 VSS VSS VSS
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MSX532
Package and Pinout
Ball G1 G2 G3 G4 G5 G6 G34 G35 G36 G37 G38 G39 N1 N2 N3 N4 N5 N6 N34 N35 N36 N37 N38 N39 W1 W2 W3 W4 W5 W6 W34 W35 W36 W37 W38 W39 Ball Name VSS RCB3 RCB2 RCB0 RCA9 RCA7 P138 P141 P140 P143 P144 P146 VSS P517 P516 P519 P518 P520 P172 P173 P175 P174 P176 VSS P488 P489 P491 P490 P492 P493 P200 P201 P203 P202 P205 VSS Ball H1 H2 H3 H4 H5 H6 H34 H35 H36 H37 H38 H39 P1 P2 P3 P4 P5 P6 P34 P35 P36 P37 P38 P39 Y1 Y2 Y3 Y4 Y5 Y6 Y34 Y35 Y36 Y37 Y38 Y39
(Continued) Ball J1 J2 J3 J4 J5 J6 J34 J35 J36 J37 J38 J39 R1 R2 R3 R4 R5 R6 R34 R35 R36 R37 R38 R39 AA1 AA2 AA3 AA4 AA5 AA6 AA34 AA35 AA36 AA37 AA38 AA39 Ball Name VSS RCC2 RCC1 RCC0 RCB9 RCB8 P150 P152 P153 P155 P154 VSS VSS P506 P509 P508 P511 P510 P180 P183 P182 P184 P185 P187 VSS P482 P478 P483 P481 P480 P213 P212 P210 P211 P209 VSS Ball K1 K2 K3 K4 K5 K6 K34 K35 K36 K37 K38 K39 T1 T2 T3 T4 T5 T6 T34 T35 T36 T37 T38 T39 AB1 AB2 AB3 AB4 AB5 AB6 AB34 AB35 AB36 AB37 AB38 AB39 Ball Name RCE RC_EN RC_CLK RCI1 RCI0 RCC3 P157 P156 P159 P158 P160 P161 P502 P504 P505 P507 VDD VDD VDD VDD P186 P189 P188 P191 P479 P476 P477 P474 VDD VDD VDD VDD P217 P216 P214 P215 Ball L1 L2 L3 L4 L5 L6 L34 L35 L36 L37 L38 L39 U1 U2 U3 U4 U5 U6 U34 U35 U36 U37 U38 U39 AC1 AC2 AC3 AC4 AC5 AC6 AC34 AC35 AC36 AC37 AC38 AC39 Ball Name P526 P528 P529 P531 P530 UPDATE P163 P162 P165 P164 P167 P166 VSS P499 P498 P501 P500 P503 P190 P192 P193 P195 P194 VSS P475 P473 P472 P470 P471 P469 P223 P220 P221 P218 P219 VSS Ball M1 M2 M3 M4 M5 M6 M34 M35 M36 M37 M38 M39 V1 V2 V3 V4 V5 V6 V34 V35 V36 V37 V38 V39 AD1 AD2 AD3 AD4 AD5 AD6 AD34 AD35 AD36 AD37 AD38 AD39 Ball Name P521 P523 P522 P524 P525 P527 VDD VDD P168 P169 P171 P170 P495 P494 P496 P497 VDD VDD VDD VDD P197 P196 P199 P198 P468 P466 P467 P465 VDD VDD VDD VDD P227 P225 P224 P222
Ball Name RCB7 RCB6 RCB5 RCB4 VDD VDD VDD VDD P147 P149 P148 P151 P512 P513 P515 P514 VDD VDD VDD VDD P177 P179 P178 P181 P485 P484 P486 P487 VDD VDD VDD VDD P206 P207 P204 P208
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MSX532
Package and Pinout
Ball AE1 AE2 AE3 AE4 AE5 AE6 AE34 AE35 AE36 AE37 AE38 AE39 AL1 AL2 AL3 AL4 AL5 AL6 AL34 AL35 AL36 AL37 AL38 AL39 Ball Name VSS P464 P462 P463 P460 P461 P230 P231 P228 P229 P226 VSS P433 P436 P437 P434 P435 VSS P258 P259 P257 P256 P254 P255 Ball AF1 AF2 AF3 AF4 AF5 AF6 AF34 AF35 AF36 AF37 AF38 AF39 AM1 AM2 AM3 AM4 AM5 AM6 AM34 AM35 AM36 AM37 AM38 AM39
(Continued) Ball AG1 AG2 AG3 AG4 AG5 AG6 AG34 AG35 AG36 AG37 AG38 AG39 AN1 AN2 AN3 AN4 AN5 AN6 AN34 AN35 AN36 AN37 AN38 AN39 Ball Name P450 P454 P455 P452 P453 VSS P240 P238 P239 P236 P237 VSS VSS P429 P426 P427 P425 P423 P271 P268 P269 P267 P264 VSS Ball AH1 AH2 AH3 AH4 AH5 AH6 AH34 AH35 AH36 AH37 AH38 AH39 Ball Name P451 P449 P448 P446 VDD VDD VDD VDD P245 P242 P243 P241 Ball AJ AJ2 AJ3 AJ4 AJ5 AJ6 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 Ball Name P443 P447 P444 P445 P442 VSS P249 P248 P246 P247 P244 VSS Ball AK1 AK2 AK3 AK4 AK5 AK6 AK34 AK35 AK36 AK37 AK38 AK39 Ball Name P441 P440 P438 P439 VDD VDD VDD VDD P253 P252 P250 P251
Ball Name P458 P459 P457 P456 VDD VDD VDD VDD P234 P235 P233 P232 P432 P430 P431 P428 VDD VDD VDD VDD P262 P263 P260 P261
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MSX532
Package and Pinout
Ball AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 AP35 AP36 AP37 AP38 AP39 Ball Name P424 P422 P420 P419 VDD VDD P413 P404 P398 VDD P391 VDD P380 VDD P373 VDD P363 VDD P353 VDD P341 VDD P331 VDD P321 VDD P310 VDD P303 P296 P290 VDD IE_2 VDD VDD P274 P272 P270 P265 Ball AR1 AR2 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR39
(Continued) Ball AT1 AT2 AT3 AT4 AT5 AT6 AT7 AT8 AT9 AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 Ball Name VSS OE_3 VSS VSS VSS P416 P409 P402 P396 P395 P388 P385 P378 P376 P371 P367 P360 P357 P350 P346 P343 P336 P332 P327 P322 P316 P313 P306 P304 P299 P292 P286 P282 P281 VSS VSS VSS P275 VSS Ball AU1 AU2 AU3 AU4 AU5 AU6 AU7 AU8 AU9 AU10 AU11 AU12 AU13 AU14 AU15 AU16 AU17 AU18 AU19 AU20 AU21 AU22 AU23 AU24 AU25 AU26 AU27 AU28 AU29 AU30 AU31 AU32 AU33 AU34 AU35 AU36 AU37 AU38 AU39 Ball Name VSS VSS VSS VSS P417 P414 P408 P403 P397 P393 P386 P384 P379 P374 P369 P364 P358 P356 P351 P347 P342 P337 P333 P326 P325 P319 P315 P309 P305 P298 P295 P289 P285 P280 P276 VSS VSS VSS VSS Ball AV1 AV2 AV3 AV4 AV5 AV6 AV7 AV8 AV9 AV10 AV11 AV12 AV13 AV14 AV15 AV16 AV17 AV18 AV19 AV20 AV21 AV22 AV23 AV24 AV25 AV26 AV27 AV28 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AV37 AV38 AV39 Ball Name VSS VSS VSS CLK_3 P415 P412 P406 P401 P394 P392 VSS P382 P377 P375 P368 P365 P359 P354 P348 P349 P344 P339 P335 P328 P324 P318 P314 P308 P307 P301 P294 P288 P287 OE_2 P278 VSS VSS VSS VSS Ball AW1 AW2 AW3 AW4 AW5 AW6 AW7 AW8 AW9 AW10 AW11 AW12 AW13 AW14 AW15 AW16 AW17 AW18 AW19 AW20 AW21 AW22 AW23 AW24 AW25 AW26 AW27 AW28 AW29 AW30 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AW39 Ball Name VSS VSS VSS VSS P410 P407 VSS P400 VSS P390 P387 P383 VSS P372 P366 P362 VSS P355 VSS P345 VSS P338 P334 P329 VSS P320 P317 P311 VSS P300 VSS P291 VSS P284 CLK_2 VSS VSS VSS VSS
Ball Name VSS P421 P418 VSS VSS IE_3 P411 P405 P399 VDD P389 VDD P381 VDD P370 VDD P361 VDD P352 VDD P340 VDD P330 VDD P323 VDD P312 VDD P302 P297 P293 VDD P283 P279 VSS VSS P277 P273 P266
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MSX532
Package and Pinout
Ball Name CLK_0 CLK_1 CLK_2 CLK_3 HW_RST IE_0 IE_1 IE_2 IE_3 OE_0 OE_1 OE_2 OE_3 P000 P001 P002 P003 P004 P005 P006 P007 P008 P009 P010 P011 P012 P013 P014 P015 P016 P017 P018 P019 P020 P021 P022 P023 P024 P025 P026 Ball B4 F37 AW35 AV4 B5 C5 D38 AP33 AR6 E6 E38 AV34 AT2 A6 B6 B7 C7 C8 D8 B8 A8 E9 F9 C9 D9 A9 B9 D10 C10 A10 B10 E11 F11 C11 D11 B11 D12 B12 C12 A12
(Continued) TABLE 11. MSX532 Pinout By Ball Name (alphabetically) Ball Name P027 P028 P029 P030 P031 P032 P033 P034 P035 P036 P037 P038 P039 P040 P041 P042 P043 P044 P045 P046 P047 P048 P049 P050 P051 P052 P053 P054 P055 P056 P057 P058 P059 P060 P061 P062 P063 P064 P065 P066 Ball F13 D13 E13 C13 B13 D14 A13 B14 C14 F15 A14 E15 D15 B15 C15 C16 D16 A16 B16 F17 E17 C17 D17 A17 B17 C18 D18 B18 A18 E19 F19 C19 D19 B20 B19 D20 C20 B21 A20 C21 Ball Name P067 P068 P069 P070 P071 P072 P073 P074 P075 P076 P077 P078 P079 P080 P081 P082 P083 P084 P085 P086 P087 P088 P089 P090 P091 P092 P093 P094 P095 P096 P097 P098 P099 P100 P101 P102 P103 P104 P105 P106 Ball D21 F21 E21 B22 A22 C22 D22 B23 A23 D23 C23 F23 E23 A24 B24 D24 C24 C25 B25 E25 D25 F25 A26 C26 B26 A27 D26 C27 B27 D27 E27 A28 F27 B28 C28 B29 D28 C29 D29 F29 Ball Name P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 Ball E29 B30 A30 D30 C30 A31 B31 D31 C31 F31 E31 B32 A32 C32 D32 C33 B33 D33 A34 B34 E33 B35 F33 C34 B36 D34 C35 E37 E34 F36 F35 G34 F38 G36 G35 E39 G37 G38 F39 G39 Ball Name P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 Ball H36 H38 H37 J34 H39 J35 J36 J38 J37 K35 K34 K37 K36 K38 K39 L35 L34 L37 L36 L39 L38 M36 M37 M39 M38 N34 N35 N37 N36 N38 P36 P38 P37 R34 P39 R36 R35 R37 R38 T36
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MSX532
Ball Name P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 P223 P224 P225 P226
Ball R39 T38 T37 U34 T39 U35 U36 U38 U37 V37 V36 V39 V38 W34 W35 W37 W36 Y38 W38 Y36 Y37 Y39 AA38 AA36 AA37 AA35 AA34 AB38 AB39 AB37 AB36 AC37 AC38 AC35 AC36 AD39 AC34 AD38 AD37 AE38
Ball Name P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P241 P242 P243 P244 P245 P246 P247 P248 P249 P250 P251 P252 P253 P254 P255 P256 P257 P258 P259 P260 P261 P262 P263 P264 P265 P266
Ball AD36 AE36 AE37 AE34 AE35 AF39 AF38 AF36 AF37 AG37 AG38 AG35 AG36 AG34 AH39 AH37 AH38 AJ38 AH36 AJ36 AJ37 AJ35 AJ34 AK38 AK39 AK37 AK36 AL38 AL39 AL37 AL36 AL34 AL35 AM38 AM39 AM36 AM37 AN38 AP39 AR39
Ball Name P267 P268 P269 P270 P271 P272 P273 P274 P275 P276 P277 P278 P279 P280 P281 P282 P283 P284 P285 P286 P287 P288 P289 P290 P291 P292 P293 P294 P295 P296 P297 P298 P299 P300 P301 P302 P303 P304 P305 P306
Ball AN37 AN35 AN36 AP38 AN34 AP37 AR38 AP36 AT38 AU35 AR37 AV35 AR34 AU34 AT34 AT33 AR33 AW34 AU33 AT32 AV33 AV32 AU32 AP31 AW32 AT31 AR31 AV31 AU31 AP30 AR30 AU30 AT30 AW30 AV30 AR29 AP29 AT29 AU29 AT28
Ball Name P307 P308 P309 P310 P311 P312 P313 P314 P315 P316 P317 P318 P319 P320 P321 P322 P323 P324 P325 P326 P327 P328 P329 P330 P331 P332 P333 P334 P335 P336 P337 P338 P339 P340 P341 P342 P343 P344 P345 P346
Ball AV29 AV28 AU28 AP27 AW28 AR27 AT27 AV27 AU27 AT26 AW27 AV26 AU26 AW26 AP25 AT25 AR25 AV25 AU25 AU24 AT24 AV24 AW24 AR23 AP23 AT23 AU23 AW23 AV23 AT22 AU22 AW22 AV22 AR21 AP21 AU21 AT21 AV21 AW20 AT20
Ball Name P347 P348 P349 P350 P351 P352 P353 P354 P355 P356 P357 P358 P359 P360 P361 P362 P363 P364 P365 P366 P367 P368 P369 P370 P371 P372 P373 P374 P375 P376 P377 P378 P379 P380 P381 P382 P383 P384 P385 P386
Ball AU20 AV19 AV20 AT19 AU19 AR19 AP19 AV18 AW18 AU18 AT18 AU17 AV17 AT17 AR17 AW16 AP17 AU16 AV16 AW15 AT16 AV15 AU15 AR15 AT15 AW14 AP15 AU14 AV14 AT14 AV13 AT13 AU13 AP13 AR13 AV12 AW12 AU12 AT12 AU11
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MSX532
Ball Name P387 P388 P389 P390 P391 P392 P393 P394 P395 P396 P397 P398 P399 P400 P401 P402 P403 P404 P405 P406 P407 P408 P409 P410 P411 P412 P413 P414 P415 P416 P417 P418 P419 P420 P421 P422 P423 P424 P425 P426
Ball AW11 AT11 AR11 AW10 AP11 AV10 AU10 AV9 AT10 AT9 AU9 AP9 AR9 AW8 AV8 AT8 AU8 AP8 AR8 AV7 AW6 AU7 AT7 AW5 AR7 AV6 AP7 AU6 AV5 AT6 AU5 AR3 AP4 AP3 AR2 AP2 AN6 AP1 AN5 AN3
Ball Name P427 P428 P429 P430 P431 P432 P433 P434 P435 P436 P437 P438 P439 P440 P441 P442 P443 P444 P445 P446 P447 P448 P449 P450 P451 P452 P453 P454 P455 P456 P457 P458 P459 P460 P461 P462 P463 P464 P465 P466
Ball AN4 AM4 AN2 AM2 AM3 AM1 AL1 AL4 AL5 AL2 AL3 AK3 AK4 AK2 AK1 AJ5 AJ1 AJ3 AJ4 AH4 AJ2 AH3 AH2 AG1 AH1 AG4 AG5 AG2 AG3 AF4 AF3 AF1 AF2 AE5 AE6 AE3 AE4 AE2 AD4 AD2
Ball Name P467 P468 P469 P470 P471 P472 P473 P474 P475 P476 P477 P478 P479 P480 P481 P482 P483 P484 P485 P486 P487 P488 P489 P490 P491 P492 P493 P494 P495 P496 P497 P498 P499 P500 P501 P502 P503 P504 P505 P506
Ball AD3 AD1 AC6 AC4 AC5 AC3 AC2 AB4 AC1 AB2 AB3 AA3 AB1 AA6 AA5 AA2 AA4 Y2 Y1 Y3 Y4 W1 W2 W4 W3 W5 W6 V2 V1 V3 V4 U3 U2 U5 U4 T1 U6 T2 T3 R2
Ball Name P507 P508 P509 P510 P511 P512 P513 P514 P515 P516 P517 P518 P519 P520 P521 P522 P523 P524 P525 P526 P527 P528 P529 P530 P531 RC_CLK RC_EN RCA0 RCA1 RCA2 RCA3 RCA4 RCA5 RCA6 RCA7 RCA8 RCA9 RCB0 RCB1 RCB2
Ball T4 R4 R3 R6 R5 P1 P2 P4 P3 N3 N2 N5 N4 N6 M1 M3 M2 M4 M5 L1 M6 L2 L3 L5 L4 K3 K2 E3 D2 F5 E2 F4 F3 E1 G6 F2 G5 G4 F1 G3
Ball Name RCB3 RCB4 RCB5 RCB6 RCB7 RCB8 RCB9 RCC0 RCC1 RCC2 RCC3 RCE RCI0 RCI1 RC_RDY TCK TDI TDO TMS TRST UPDATE VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
Ball G2 H4 H3 H2 H1 J6 J5 J4 J3 J2 K6 K1 K5 K4 D6 D7 F7 E7 C6 A5 L6 E8 E10 E12 E14 E16 E18 E20 E22 E24 E26 E28 E30 E32 F6 F8 F10 F12 F14 F16
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MSX532
Ball Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
Ball F18 F20 F22 F24 F26 F28 F30 F32 F34 H5 H6 H34 H35 M34 M35 P5 P6 P34 P35 T5 T6 T34 T35 V5 V6 V34 V35 Y5 Y6 Y34 Y35 AB5 AB6 AB34 AB35 AD5 AD6 AD34 AD35 AF5
Ball Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
Ball AF6 AF34 AF35 AH5 AH6 AH34 AH35 AK5 AK6 AK34 AK35 AM5 AM6 AM34 AM35 AP5 AP6 AP10 AP12 AP14 AP16 AP18 AP20 AP22 AP24 AP26 AP28 AP32 AP34 AP35 AR10 AR12 AR14 AR16 AR18 AR20 AR22 AR24 AR26 AR28
Ball Name VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball AR32 A1 A2 A3 A4 A7 A11 A15 A19 A21 A25 A29 A33 A35 A36 A37 A38 A39 B1 B2 B3 B37 B38 B39 C1 C2 C3 C4 C36 C37 C38 C39 D1 D3 D4 D5 D35 D36 D37 D39
Ball Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball E4 E5 E35 E36 G1 J1 J39 N1 N39 R1 U1 U39 W39 AA1 AA39 AC39 AE1 AE39 AG6 AG39 AJ6 AJ39 AL6 AN1 AN39 AR1 AR4 AR5 AR35 AR36 AT1 AT3 AT4 AT5 AT35 AT36 AT37 AT39 AU1 AU2
Ball Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball AU3 AU4 AU36 AU37 AU38 AU39 AV1 AV2 AV3 AV11 AV36 AV37 AV38 AV39 AW1 AW2 AW3 AW4 AW7 AW9 AW13 AW17 AW19 AW21 AW25 AW29 AW31 AW33 AW36 AW37 AW38 AW39
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MSX532
Package Thermal Characteristics
TABLE 12. Package Thermal Characteristics Package TBGA Pin Count 792
JC (C/W)
0.4
JA (C/W)
Still Air 7.58
JA (C/W)
200 Ifpm 6.00
JA (C/W)
300 Ifpm 5.66
JA (C/W)
500 Ifpm 5.26
Thermal performance values are based on simulation data
Power Consumption
There are three components to consider when calculating power for the MSX Family of devices: 1. Steady State Component: This element equals 252 mW. 2. Connection Component: This element equals 0.006 mW x Mb/s x connections. 3. Output Drive Component: This element equals 0.013 mW x number of outputs x Mb/s x capacitive load (pF). Power Consumption = Steady State Component + Connection Component + Output Drive Component.
= 252 mW + (0.006 x Mb/s x #connections) + (0.013 x Mb/s x #outputs x Cload)
The following examples shows the total power consumption as determined by the above formula: Example 1 Using the MSX532 with 10 Mb/s into a 10pF load with 266 inputs connected to 266 outputs: Power Consumption Example 2 Using the MSX532 with 150 Mb/s into a 10pF load with 266 inputs connected to 266 outputs: Power Consumption
= 252 mW + (0.006 x 10 x 266) + (0.013 x 266 x 10 x 10) = 252 mW
+ 16 mW + 346 mW = 0.614 Watts
= 252 mW + (0.006 x 150 x 266) + (0.013 x 266 x 150 x 10) = 252 mW
+ 239.4 mW + 5187 mW = 5.68 Watts
Glossary
Array Side: The signal and connections between the Crosspoint Array and the I/O Buffer. Bus Repeater: A circuit operation of the I/O Buffer that enables the MSX device to pass data in both directions on an I/O device pin. The I/O Buffer is placed in a disabled output state to the pin and to the Crosspoint array. A forced LOW on either side of the I/O Buffer will be transmitted to the other side of the I/O Buffer and held until the forced LOW is changed to a force HIGH. At the change of the forcing input, the I/O Buffer will force the other side to a following high state and drive a high level out for a period of time. After the period of time, the I/O Buffer will return to the disabled state. Bypass: A JTAG instruction that connects the previous chip to the next chip through a one bit data register to speed up programming of other chips in a JTAG chain of devices. Clock: Four device corner inputs used to gate data into registers in the I/O Buffer. The Corner inputs serve two sides of the MSX. This provides two choices for each I/O Buffer register in and register out. The neighbor input can also be used as register clock and the clocks can be inverted. Control Register: A programmable register used to control various functions in programming and other circuit settings. All Bits programmed in the JTAG Mode. RapidConfigure Enable bit can be set with a high level on the RCE pin during a reset of the circuits. Crosspoint: A single cell containing two N Channel transistors and two RAM bits. The RAM bits are connected in a master-slave configuration to provide an update for programming and changing program information all at once. Each cell contains both an X and Y reset to remove all ports connected to an addressed port in a single program cycle. Crosspoint Array: An array of Crosspoint used to connect any port to any other port or any combination of other ports. The array has all redundant cell removed; there is a single Crosspoint cell for each port to port connection. The reduced cell count is folded to provide a square array. The array has a diagonal line where the cells are rotated. Data Bit Lines: A pair of signal lines used to write into and read out of Crosspoint Cells. The lines are pre-charged before a read and one is pulled LOW for a write. Device ID: A 32-bit register in the MSX device with a wired identification. The ID consists of a given number for the device and a revision history field. The identification is shifted out during JTAG reset and the DEVICE ID instruction in JTAG mode. The ID for the MSX devices is 0x0000A89F.
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MSX532
Glossary
(Continued) Extest: A JTAG instruction that samples I/O pin states and loads new I/O buffer states for testing device pin connections. The MSX devices use a special test mode in Extext to observe the buffer data on the pin side and the array side. A bit in the Control Register controls this mode. I/O Buffer: The circuit that controls the driving of its associated pin and its port into and out of the Crosspoint Array. The buffer contains all the circuits to make it independent of the other I/O Buffers. Each Buffer contains registers for input and output, driving circuits for input and output, sense for Crosspoint Array input, and RAM bits to hold programmed data controlling the function of the buffer. Input or Output Path: The signal flow from pin to array and array to pin. Each path has a register with selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on either side of the I/O Buffer. JTAG: The Joint Test Action group is a committee to standardize scan testing of devices. The JTAG interface is referred to as IEEE 1149.1. This is a five bit serial programming and testing method. JTAG Sequence: The ordering of all the pins in a serial chain for driving and sensing signals on pins during Extest and Sample/Preload. All pins except power and ground and the five JTAG pins are in the serial string. Next Neighbor: Input can be selected as the clock for the I/O buffer registers for data and clock pairing. The next
higher port is the selected neighbor except for Port 531, which uses Port 0. Pin Side Driver: The I/O Buffer circuit that drives the device pin associated with that buffer. Port: A name followed by a number to identify a pin on the device. Ports are numbered from 531 to 0 on the MSX device. In shifting sequence, Port P000 is shifted in first and shifted out first. RapidConfigure: A parallel programming method for the MSX devices. The RC mode uses 29 dedicated pins to program the Crosspoint Array and the I/O Buffers. The 29 pins consist of an enable, a strobe, two instruction bits, four variable bits, and two ten-bit address fields. RCE: A control pin of the MSX device that is sampled during reset to determine if the device becomes active in the JTAG or the RapidConfigure mode. This pin places the Control Register bit in the state to allow RC operations or not based on the voltage level of the RCE pin. The JTAG mode is always enabled and can set or clear the RC bit in the Control Register. Trickle Current: A very low current (~15 microamperes) used to pull unused or non-driven circuits to a stable HIGH level. Prevents signals from drifting between CMOS thresholds and drawing currents from the power supply. In the case of Bus Repeater, the small trickle current provides a known high level on the pin and array side inputs.
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MSX532 532 Port Digital Crosspoint Switch with LVTTL I/O's
Physical Dimensions inches (millimeters) unless otherwise noted
792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch, 40mm Square Package Number BGA792A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 36 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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