View MAX5105_47679.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1925; Rev 1; 6/01
Nonvolatile, Quad, 8-Bit DACs
General Description
The MAX5105/MAX5106 nonvolatile, quad, 8-bit digitalto-analog converters (DACs) operate from a single +2.7V to +5.5V supply. An internal EEPROM stores the DAC states even after power is removed. Data from these nonvolatile registers automatically initialize the DAC outputs and operating states during power-up. Precision internal buffers swing Rail-to-Rail(R), and the reference input range includes both ground and the positive rail. The MAX5105/MAX5106 feature a software-controlled 10A shutdown mode and a mute state that drives the DAC outputs to their respective REFL_ voltages. The MAX5105 includes an asynchronous MUTE input, as well as a RDY/BSY output that indicates the status of the nonvolatile memory. The MAX5105 is available in a 20-pin QSOP and 20-pin wide SO packages, and the MAX5106 is available in a 16-pin QSOP package.
Features
o On-Chip EEPROM Stores DAC States o Power-On Reset Initialization of All Registers to Prestored States o +2.7V to +5.5V Single-Supply Operation o Four 8-Bit DACs with Independent High and Low Reference Inputs (MAX5105) o Ground to VDD Reference Input Range o Rail-to-Rail Output Buffers o Low 1mA Supply Current o Low Power 10A (max) Shutdown Mode o Small 20- or 16-Pin QSOP Package o SPITM/QSPITM/MICROWIRETM-Compatible Serial Interface o Asynchronous MUTE Input (MAX5105) o RDY/BSY Pin to Indicate Memory Status (MAX5105) o Wide Operating Temperature Range (-40C to +85C)
MAX5105/MAX5106
________________________Applications
Digital Gain and Offset Adjustments Programmable Attenuators Portable Instruments Power-Amp Bias Control
Functional Diagram appears at end of data sheet. Rail-to-Rail is a trademark of Nippon Motorola, Ltd. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information
PART MAX5105EEP MAX5105EWP MAX5106EEE TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 QSOP 20 SO 16 QSOP
Pin Configurations
TOP VIEW
REFH1 1 REFH0 2 VDD 3 RDY/BSY 4 CLK 5 CS 6 DIN 7 DOUT 8 MUTE 9 GND 10 20 REFH2 19 REFH3 18 OUT0 17 OUT1 REFH1 1 REFH0 2 VDD 3 CLK 4 CS 5 DIN 6 DOUT 7 GND 8 16 REFH2 15 REFH3 14 OUT0
MAX5106
13 OUT1 12 OUT2 11 OUT3 10 REFL1 9 REFL0
MAX5105
16 OUT2 15 OUT3 14 REFL3 13 REFL2 12 REFL1 11 REFL0
16 QSOP
20 QSOP/SOIC ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
ABSOLUTE MAXIMUM RATINGS
VDD, DIN, CS, CLK, MUTE to GND .............................-0.3V, +6V DOUT, REFH_, REFL_, RDY/BSY, OUT_ to GND .........................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.3mW/C above +70C)........666.7mW 20-Pin QSOP (derate 9.1mW/C above +70C)........727.3mW 20-Pin SO (derate 10mW/C above +70C).................800mW Operating Temperature Range MAX510_ .........................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VREFH_ = +2.7V to +5.5V, GND = VREFL_ = 0, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25C.)
PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity INL Code range 10hex to F0hex, ILOAD = 50A Full code range, ILOAD = 50A Differential Nonlinearity (Note 1) Zero-Code Error Zero-Code Temperature Coefficient Gain Error (Note 2) Gain-Error Temperature Coefficient Power-Supply Rejection Ratio REFERENCE INPUT Reference Input Voltage Range Input Resistance Input Resistance Matching Input Capacitance DAC OUTPUTS (VREFH VREFL) VREFL_ x (N/256) + VREFL_ VREFH_, VREFL_ 0 92 256 0.2 10 VDD 413 1 V k % pF PSRR DNL ZCE Code range 10hex to F0hex, ILOAD = 50A Full code range, ILOAD = 50A Code = 0Ahex Code = 0Ahex Code = F0hex Code = F0hex Code = 0Ahex and FFhex, VDD = 2.7V to 5.5V, VREFH_ = 2.5V, VREFL_ = 0, ILOAD = 50A 0.002 20 1 8 1 2 0.5 1 20 mV V/C LSB LSB/C LSB Bits LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
1
LSB/V
Output Voltage Range
N = input code, ILOAD = 0
V
2
_______________________________________________________________________________________
Nonvolatile, Quad, 8-Bit DACs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VREFH_ = +2.7V to +5.5V, GND = VREFL_ = 0, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25C.)
PARAMETER Output Current (Note 3) Amplifier Output Resistance (Note 3) DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance DYNAMIC PERFORMANCE CLK to OUT_ Settling Time (Note 4) Channel-to-Channel Crosstalk (Note 5) tCOS VDD = +5V, code = Ffhex, VREFH_ = 2.5Vp-p at 10kHz VDD = +5V, code = FFhex VREFH_ = 2.5Vp-p at 1kHz VREFH_ = 2.5Vp-p at 10kHz 6 85 58 dB 56 250 86 4 75 tSDR tSHDN VDD IDD ILOAD = 0, digital inputs at GND or VDD During nonvolatile write operation 2.7 0.8 20 0.5 10 7 2 5.5 1.0 kHz dB nV - s nV/Hz s s V mA A s dB VOH VOL ILEAK COUT 15 ISOURCE = 0.4mA ISINK = 1mA VDD - 0.3 0.4 10 V V A pF VIH VIL IIN CIN VIN = 0 or VDD 10 0.7 x VDD 0.8 10 V V A pF SYMBOL VOUT_< 1LSB CONDITIONS MIN TYP 1.0 3 MAX UNITS mA
MAX5105/MAX5106
Signal to Noise Plus Distortion
SINAD
Multiplying Bandwidth Reference Feedthrough Clock Feedthrough DAC Output White Noise Shutdown Recovery Time Time to Shutdown POWER SUPPLIES Supply Voltage Supply Current Shutdown Current
VREFH_ = 0.5Vp-p, 3dB bandwidth VDD = +5V, code = 00hex, VREFH_ = 2.5Vp-p at 1kHz
________________________________________________________________________________________
3
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VREFH_ = +2.7V to +5.5V, GND = VREFL_ = 0, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25C.)
PARAMETER DIGITAL TIMING CLK Period CLK High Time CLK Low Time CS High Time CS Setup Time CS Hold Time DIN Setup Time DIN Hold Time CLK to DOUT Valid Time CLK to DOUT Propagation Delay DOUT Disable Time Nonvolatile Store Time Data Retention Endurance tCP tCH tCL tCSHT tCSS tCSH tDS tDH tCDV tCD tCSD tBUSY MIL STD-883 Test Method 1008 MIL STD-883 Test Method 1033 100 100,000 CLOAD = 100pF CLOAD = 100pF CLOAD = 100pF 1 300 300 150 100 0 100 0 1 1 250 13 s ns ns ns ns ns ns ns s s ns ms Years Stores SYMBOL CONDITIONS MIN TYP MAX UNITS
NONVOLATILE MEMORY RELIABILITY
Note 1: Guaranteed monotonic. Note 2: Gain error is: [100 x (VF0(MEAS) - ZCE - VF0(IDEAL))/VREFH]; where VF0(MEAS) is the DAC output voltage with input code F0hex. VF0(IDEAL) is the ideal DAC output voltage with input code F0hex (i.e., (VREFH - VREFL) x 240/256 + VREFL). Note 3: In the voltage range, 0.5V < VOUT_ < VDD - 0.5V. Note 4: Output settling time is measured from the 50% point of the rising edge of last CLK to 1/2LSB of VOUT's final value for a code transition from 10hex to F0hex. See Figure 4. Note 5: Channel-to-channel crosstalk is defined as the coupling from one driven reference with input code = FFhex to any other DAC output with the reference of that DAC at a constant value and input code = 00hex.
4
_______________________________________________________________________________________
Nonvolatile, Quad, 8-Bit DACs
Typical Operating Characteristics
(RL = , code = FFhex, VREFL_ = GND, TA = +25C, unless otherwise noted.)
DAC ZERO-CODE OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
MAX5105/06 toc01
MAX5105/MAX5106
DAC FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT
VDD = VREFH_ = +5V 5 OUTPUT VOLTAGE (V) 4 3 2 1 VDD = VREFH_ = +3V
MAX5105/06 toc02
SUPPLY CURRENT vs. TEMPERATURE
650 SUPPLY CURRENT (A) 600 550 500 450 400 VDD = +3V VREFH_ = +2.5V VDD = +5V VREFH_ = +4.096V
MAX5105/06 toc03
0.5
6
700
0.4 OUTPUT VOLTAGE (V) VDD = +3V VREFL_ = +0.2V
0.3
VDD = +5V VREFL_ = +0.2V
0.2
0.1 CODE = 00hex 0 0 2 4 6 8 10 OUTPUT CURRENT (mA)
350 300 0 2 4 6 8 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) OUTPUT CURRENT (mA)
0
SUPPLY CURRENT vs. REFERENCE VOLTAGE
MAX5105/06 toc04
SUPPLY CURRENT vs. REFERENCE VOLTAGE
MAX5105/06 toc05
THD + NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE
VREF = SINE-WAVE VDD = +3.0V CENTERED AT 1.5V DAC CODE = FFhex 80kHz LOWPASS FILTER
MAX5105/06 toc06
1000 900 800 SUPPLY CURRENT (A) 700 600 500 400 300 200 100 0 0.0 0.5 1.0 1.5 2.0 VDD = +3V 2.5 CODE = 00hex CODE = FFhex
1000 900 800 SUPPLY CURRENT (A) 700 600 500 400 300 200 100 0 CODE = 00hex CODE = FFhex
0 -10 THD + NOISE (dB) -20 -30 -40 -50 -60
fVREF = 10kHz fVREF = 1kHz
VDD = +5V 0 1 2 3 4 5
-70 0.0 0.5 1.0 1.5 2.0 2.5 3.0 REFERENCE AMPLITUDE (Vp-p)
3.0
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
THD + NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE
MAX5105/06 toc07
THD + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY
MAX5105/06 toc08
THD + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY
-10 -20 -30 -40 -50 -60 -70 VREF = 1Vp-p VREF = SINE-WAVE VDD = +5.0V CENTERED AT 2.5V DAC CODE = FFhex 500kHz LOWPASS FILTER VREF = 2Vp-p VREF = 2.5Vp-p
MAX5105/06 toc09
0 -10 -20 THD + NOISE (dB) -30 -40 -50 -60 -70 -80 0 1 2
0 -10 -20 -30 -40 -50 -60 -70 VREF = 0.5Vp-p
THD + NOISE (dB)
VREF = 2Vp-p VREF = 1Vp-p
fVREF = 10kHz
fVREF = 1kHz
3
4
5
10
100
1k FREQUENCY (Hz)
10k
100k
THD + NOISE (dB)
VREF = SINE-WAVE VDD = +5.0V CENTERED AT 2.5V DAC CODE = FFhex 80kHz LOWPASS FILTER
VREF = SINE-WAVE VDD = +3.0V CENTERED AT 1.5V DAC CODE = FFhex 500kHz LOWPASS FILTER
0
10
100
1k FREQUENCY (Hz)
10k
100k
REFERENCE AMPLITUDE (Vp-p)
________________________________________________________________________________________
5
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
Typical Operating Characteristics (continued)
(RL = , code = FFhex, VREFL_ = GND, TA = +25C, unless otherwise noted.)
REFERENCE INPUT FREQUENCY RESPONSE
MAX5105/06 toc10
REFERENCE FEEDTHROUGH vs. FREQUENCY
MAX5105/06 toc11
CROSSTALK vs. FREQUENCY
-30 RELATIVE OUTPUT (dB) -40 -50 -60 -70 -80 -90 -100 VREH0 = 3Vp-p SINE-WAVE CENTERED AT +2.5V DAC0 CODE = FFhex VREFH1 = GND DAC1 CODE = 00hex VDD = +5V
MAX5105/06 toc12
MAX5105/06 toc15
5 0 -5 RELATIVE OUTPUT (dB) -10 -15 -20 -25 -30 -35 -40 -45 1 VREF = 0.5Vp-p SINE-WAVE CENTERED AT +2.5V DAC CODE = FFhex VDD = +5.0V 10 100 1k
-20 -30 RELATIVE OUTPUT (dB) -40 -50 -60 -70 -80 -90 -100 1 10 100 1k VREF = 2.5Vp-p SINE-WAVE CENTERED AT +2.5V DAC CODE = FFhex VDD = +5V
-20
10k 100k 1M 10M 100M
10k 100k 1M 10M 100M
1
10
100
FREQUENCY (Hz)
FREQUENCY (Hz)
1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
1LSB DIGITAL STEP-CHANGE (NEGATIVE)
MAX5105/06 toc13
1LSB DIGITAL STEP-CHANGE (NEGATIVE)
MAX5105/06 toc14
1LSB DIGITAL STEP-CHANGE (POSITIVE)
5V 3V CS 0 0
3V CS 0 CS
50mV/div
50mV/div
OUT1
OUT1
OUT1
VDD = +3.0V VREFH1 = +2.5V CLOAD = 100pF
1.0 s/div fCLK = 500kHz CODE = 80 HEX TO 7F HEX RL = 10k
VDD = +5.0V VREFH1 = +4.096V CLOAD = 100pF
1.0 s/div fCLK = 500kHz CODE = 80 HEX TO 7F HEX RL = 10k
VDD = +3.0V VREFH1 = +2.5V CLOAD = 100pF
1.0 s/div fCLK = 500kHz CODE = 7F HEX TO 80 HEX RL = 10k
1LSB DIGITAL STEP-CHANGE (POSITIVE)
MAX5105/06 toc16
CLOCK FEEDTHROUGH
MAX5105/06 toc17
CLOCK FEEDTHROUGH
MAX5105/06 toc18
5V CS 0 CLK
3V CLK 0
5V
0
10mV/div
50mV/div
OUT1
OUT1
OUT1
VDD = +5.0V VREFH1 = +4.096V CLOAD = 100pF
1.0 s/div fCLK = 500kHz CODE = 7F HEX TO 80 HEX RL = 10k
VDD = +3.0V VREFH1 = +2.5V CLOAD = 100pF
1.0 s/div fCLK = 500kHz CODE = 00 HEX RL = 10k
VDD = +5.0V VREFH1 = +4.096V CLOAD = 100pF
1.0 s/div fCLK = 500kHz CODE = 00 HEX RL = 10k
6
_______________________________________________________________________________________
10mV/div
50mV/div
Nonvolatile, Quad, 8-Bit DACs
Typical Operating Characteristics (continued)
(RL = , code = FFhex, VREFL_ = GND, TA = +25C, unless otherwise noted.)
MAX5105/MAX5106
POSITIVE SETTLING TIME
MAX5105/06 toc19
POSITIVE SETTLING TIME
MAX5105/06 toc20
3V CS 0 CS
5V
0
2.5V OUT1 0 1.0 s/div fCLK = 500kHz CODE = 00 HEX TO FF HEX RL = 10k 2.0 s/div fCLK = 500kHz CODE = 00 HEX TO FF HEX RL = 10k OUT1
4.096V
0
VDD = +3.0V VREFH1 = +2.5V CLOAD = 100pF
VDD = +5.0V VREFH1 = +4.096V CLOAD = 100pF
NEGATIVE SETTLING TIME
MAX5105/06 toc21
NEGATIVE SETTLING TIME
MAX5105/06 toc22
3V CS 0 CS
5V
0
2.5V OUT1 0 1.0 s/div fCLK = 500kHz CODE = FF HEX TO 00 HEX RL = 10k 2.0 s/div fCLK = 500kHz CODE = FF HEX TO 00 HEX RL = 10k OUT1
4.096V
0
VDD = +3.0V VREFH1 = +2.5V CLOAD = 100pF
VDD = +5.0V VREFH1 = +4.096V CLOAD = 100pF
_______________________________________________________________________________________
7
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
Pin Description
PIN NAME MAX5105 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MAX5106 1 2 3 -- 4 5 6 7 -- 8 9 10 -- -- 11 12 13 14 15 16 REFH1 REFH0 VDD RDY/BSY CLK CS DIN DOUT MUTE GND REFL0 REFL1 REFL2 REFL3 OUT3 OUT2 OUT1 OUT0 REFH3 REFH2 DAC1 High Reference Input DAC0 High Reference Input Positive Supply Voltage Ready/Busy Open-Drain Output. Indicates the state of the nonvolatile memory. Connect a 100k pullup resistor from RDY/BSY to VDD. Serial Clock Input Chip Select Input Serial Data Input Serial Data Output Mute Input. Drives all DAC outputs to their respective REFL_ voltages. Ground. Serves as REFL2 and REFL3 for the MAX5106. DAC0 Low Reference Input DAC1 Low Reference Input DAC2 Low Reference Input DAC3 Low Reference Input DAC3 Output DAC2 Output DAC1 Output DAC0 Output DAC3 High Reference Input DAC2 High Reference Input FUNCTION
Detailed Description
The MAX5105/MAX5106 quad, 8-bit DACs feature an internal, nonvolatile EEPROM, which stores the DAC states for initialization during power-up. These devices consist of four resistor string DACs, four rail-to-rail buffers, a 14-bit shift register, oscillator, power-on reset (POR) circuitry, and five volatile and five nonvolatile memory registers (Functional Diagram). The shift register decodes the control and address bits, routing the data to the proper memory registers. Data can be written to a selected volatile register, immediately updating
the DAC output, or can be written to a selected nonvolatile register for storage. The five volatile registers retain data as long as the device is enabled and powered. Once power is removed or the device is shut down, the volatile registers are cleared. The nonvolatile registers retain data even after power is removed. On power-up, the POR circuitry and internal oscillator control the transfer of data from the nonvolatile registers to the volatile registers, which automatically initializes the device upon startup. Data can be read from the nonvolatile registers through DOUT.
8
_______________________________________________________________________________________
Nonvolatile, Quad, 8-Bit DACs
Table 1. Mute/Shutdown Register Mapping
Bit in Register Controlling Function D7 (MSB) Mute DAC3 D6 Mute DAC2 D5 Mute DAC1 D4 Mute DAC0 D3 Shutdown DAC3 D2 Shutdown DAC2 D1 Shutdown DAC1 D0 (LSB) Shutdown DAC0
MAX5105/MAX5106
REFH R0 R1 R15
(mute) or to a high-impedance state (shutdown). Placing all four DACs in shutdown reduces supply current to 10A (max). The MAX5105 also provides an asynchronous MUTE input, simultaneously driving all DAC outputs to their respective REFL_ voltages.
D7 MSB DECODER R16 D6 D5 D4
Internal EEPROM
The MAX5105/MAX5106 internal EEPROM consists of five nonvolatile registers that retain the DAC output and operating states after the device is powered down. Four registers store data for each DAC, and one stores the mute and shutdown states for the device.
REFL
R255
DAC Registers
The MAX5105/MAX5106 have eight 8-bit DAC registers, four volatile and four nonvolatile, that store DAC data. The four volatile DAC registers hold the current value of each DAC. Data is written to these registers in two ways: directly from DIN or loaded from the respective nonvolatile registers (see Serial Input Data Format and Control Codes). These registers are cleared when the device is shut down or power is removed. The four nonvolatile registers retain the DAC values even after power is removed. Stored data is accessed in two ways: transferring data to a volatile register to update the respective DAC output or reading data through DOUT (see Serial Input Data Format and Control Codes). On power-up, the device is automatically initialized with data stored in the nonvolatile registers.
LSB DECODER D3 D2 D1 D0
DAC
Figure 1. DAC Simplified Circuit Diagram
DAC Operation
The MAX5105/MAX5106 use a matrix decoding architecture for the DACs, which saves power in the overall system. A resistor string placed in a matrix fashion divides down the difference between the external reference voltages, V REFH and V REFL. Row and column decoders select the appropriate tab from the resistor string, providing the needed analog voltages. The resistor string presents a code-independent input impedance to the reference and guarantees a monotonic output. Figure 1 shows a simplified diagram of one of the four DACs.
Mute/Shutdown Registers
The MAX5105/MAX5106 have two 8-bit mute/shutdown registers that store the operating state of each DAC. The four MSBs hold the mute states, and the four LSBs hold the shutdown states (Table 1). The volatile registers hold the current mute/shutdown state of each DAC. Like the DAC registers, the nonvolatile mute/shutdown register maintains its data after the device is powered down, and the contents can be read on DOUT. The volatile register is initialized with the nonvolatile data on power-up and can be loaded through DIN or from the nonvolatile register (see Serial Input Data Format and Control Codes).
Output Buffer Amplifiers
All MAX5105/MAX5106 analog outputs are internally buffered by precision unity-gain followers that slew at about 0.5V/s. The outputs can swing from GND to VDD. With a VREFL _ to VREFH_ (or VREFH_to VREFL_) output transition, the amplifier outputs typically settle to 1/2LSB in 6s when loaded with 10k in parallel with 100pF. The software mute/shutdown command independently drives each output to its respective REFL_ voltage
________________________________________________________________________________________
9
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
Table 2. Serial Interface Programming Commands
14-BIT SERIAL WORD START 1 1 1 1 C1 0 0 0 0 C0 0 0 0 0 A2 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1 D7-D0 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data 8-bit DAC data FUNCTION Write DAC data to DAC0 nonvolatile register. Output remains unchanged. Write DAC data to DAC1 nonvolatile register. Output remains unchanged. Write DAC data to DAC2 nonvolatile register. Output remains unchanged. Write DAC data to DAC3 nonvolatile register. Output remains unchanged. Write shutdown and mute states to nonvolatile register. A 1 in bits D7-D4 mutes the respective DAC; a 1 in bits D3-D0 shuts down the respective DAC (Table 1). Outputs remain unchanged. Write DAC data to DAC0 volatile register and update OUT0. All other DAC outputs remain unchanged. Write DAC data to DAC1 volatile register and update OUT1. All other DAC outputs remain unchanged. Write DAC data to DAC2 volatile register and update OUT2. All other DAC outputs remain unchanged. Write DAC data to DAC3 volatile register and update OUT3. All other DAC outputs remain unchanged. Write shutdown and mute states to volatile register. A 1 in bits D7-D4 mutes the respective DAC; a 1 in bits D3-D0 shuts down the respective DAC (Table 1). DAC outputs updated to their respective mute/shutdown states. Read DAC0 nonvolatile register. Contents of DAC0 nonvolatile register available on DOUT. D7-D0 are ignored, and all DAC outputs remain unchanged. Read DAC1 nonvolatile register. Contents of DAC1 nonvolatile register available on DOUT. D7-D0 are ignored, and all DAC outputs remain unchanged. Read DAC2 nonvolatile register. Contents of DAC2 nonvolatile register available on DOUT. D7-D0 are ignored, and all DAC outputs remain unchanged. Read DAC3 nonvolatile register. Contents of DAC3 nonvolatile register available on DOUT. D7-D0 are ignored, and all DAC outputs remain unchanged. Read mute/shutdown nonvolatile register. Contents of mute/shutdown nonvolatile register available on DOUT. D7-D0 are ignored, and all DAC outputs remain unchanged.
1
0
0
1
0
0
1 1 1 1
0 0 0 0
1 1 1 1
0 0 0 0
0 0 1 1
0 1 0 1
1
0
1
1
0
0
1
1
0
0
0
0
XXXXXXXX
1
1
0
0
0
1
XXXXXXXX
1
1
0
0
1
0
XXXXXXXX
1
1
0
0
1
1
XXXXXXXX
1
1
0
1
0
0
XXXXXXXX
10
______________________________________________________________________________________
Nonvolatile, Quad, 8-Bit DACs
Table 2. Serial Interface Programming Commands (continued)
14-BIT SERIAL WORD START C1 C0 A2 A1 A0 D7-D0 FUNCTION Load DAC0 nonvolatile register. Contents of DAC0 nonvolatile register are loaded into the corresponding volatile register and OUT0 updated. D7-D0 are ignored, and all other DAC outputs remain unchanged. Load DAC1 nonvolatile register. Contents of DAC1 nonvolatile register are loaded into the corresponding volatile register and OUT1 updated. D7-D0 are ignored, and all other DAC outputs remain unchanged. Load DAC2 nonvolatile register. Contents of DAC2 nonvolatile register are loaded into the corresponding volatile register and OUT2 updated. D7-D0 are ignored, and all other DAC outputs remain unchanged. Load DAC3 nonvolatile register. Contents of DAC3 nonvolatile register are loaded into the corresponding volatile register and OUT3 updated. D7-D0 are ignored, and all other DAC outputs remain unchanged. Load mute/shutdown nonvolatile register. Contents of mute/shutdown nonvolatile register are loaded into the mute/shutdown volatile register, and all DACs are placed into their respective mute/shutdown states. D7-D0 are ignored.
MAX5105/MAX5106
1
1
1
0
0
0
XXXXXXXX
1
1
1
0
0
1
XXXXXXXX
1
1
1
0
1
0
XXXXXXXX
1
1
1
0
1
1
XXXXXXXX
1
1
1
1
0
0
XXXXXXXX
Serial Interface
The MAX5105/MAX5106 communicate with microprocessors (Ps) through a synchronous, full-duplex 3wire interface (Figure 2). Data is sent MSB first and is transmitted in one 14-bit word. A 4-wire interface adds a line for RDY/BSY (MAX5105), indicating the status of the nonvolatile memory. Data is transmitted and received simultaneously. Figure 3 shows the detailed serial interface timing. Note that the clock should be low if it is stopped between updates. DOUT is high impedance until a valid read command and address is written to the device. Serial data is clocked into the 14-bit shift register in an MSB-first format, with the start-bit, configuration, and address information preceding the actual DAC data. Data is clocked in on CLK's rising edge while CS is low. CS must be low to enable the device. If CS is high, the interface is disabled and DOUT remains unchanged. CS must go low at least 100ns before the first rising edge of the clock pulse to properly clock in the first bit. With CS low, data is clocked into the shift register on the rising edge of the external serial clock.
Serial Input Data Format and Control Codes The 14-bit serial input format, shown in Figure 4, comprises one start bit, two control bits (C0, C1), three address bits (A0, A1, A2), and eight data bits (D7-D0). The 5-bit address/control code configures the DAC as shown in Table 2.
Nonvolatile Store Command
The nonvolatile store command loads the 8-bit DAC data into the selected nonvolatile DAC register, or the DAC operating states into the mute/shutdown nonvolatile register. The nonvolatile store command does not affect the current DAC outputs or operating states. Once the control and address bits are clocked in, RDY/BSY (MAX5105) goes low until the nonvolatile store operation is complete. For the MAX5106, wait the maximum 13ms store time before writing a new word to the device. Do not write new data to the device until RDY/BSY (MAX5105) returns high, or the 13ms store time (MAX5106) has elapsed. Figure 5 shows the nonvolatile store command timing diagram.
_______________________________________________________________________________________
11
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
INSTRUCTION EXECUTED
CS
SCLK
DIN S C1 C0 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DACO DACO
Figure 2. 3-Wire Interface Timing
CS tCHST tCSS tCL CLK tDS tDH DIN tCD tCDV DOUT tCH tCP tCSH
Figure 3. Detailed Serial-Interface Timing Diagram
THIS IS THE FIRST BIT SHIFTED IN MSB DOUT LSB DIN
START C1 C0 A2 A1 A0 D7 D6 . . . D1 D0 CONTROL AND ADDRESS BITS 8-BIT DAC DATA
Figure 4. Serial Input Format 12 ______________________________________________________________________________________
Nonvolatile, Quad, 8-Bit DACs
Table 3. Nonvolatile Store Command
START 1 C1 0 C0 0 A2 A1 Address A0 D7 D6 D5 D4 D3 D2 D1 D0 8-Bit Data
MAX5105/MAX5106
Table 4. Register Write Command
START 1 C1 0 C0 1 A2 A1 Address A0 D7 D6 D5 D4 D3 D2 D1 D0 8-Bit Data
Table 5. Nonvolatile Read Command
START 1 C1 1 C0 0 A2 A1 Address A0 D7 D6 D5 D4 D3 D2 D1 D0 Don't Care
Table 6. Nonvolatile Load Command
START 1 C1 1 C0 1 A2 A1 Address A0 D7 D6 D5 D4 D3 D2 D1 D0 Don't Care
Table 7. Mute/Shutdown Modes
START 1 C1 0 C0 0 A2 1 A1 0 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 Mute/Shutdown State
CS
CLK
DIN
START
C1
C0
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
HIGH IMPEDANCE tBUSY
RDY/BSY (MAX5105 ONLY)
Figure 5. Nonvolatile Store Command Timing Diagram
The nonvolatile store command is ignored if all DACs are muted or in shutdown.
Register Write Command
This command directly loads the DAC data to the selected DAC volatile register and updates the respec-
tive output on the rising edge CLK corresponding to D0. The mute/shutdown volatile register is also accessible through this command by setting A2 high. A 1 in any of the four MSBs (D7-D4) mutes the selected DAC; a 1 in any of the four LSBs (D3-D0) disables the selected DAC (Table 1). The DAC operating states change
_______________________________________________________________________________________
13
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
CS
CLK
DIN
START
C1
C0
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE DOUT tCOS
OUT_ AT VDD (MAX5105 ONLY)
RDY/BSY
Figure 6. Register Write Command Timing Diagram
CS
CLK
DIN
START
CI
CO
A2
A1
A0
HIGH IMPEDANCE DOUT AT VDD (MAX5105 ONLY)
D7
D6
D5
D4
D3
D2
D1
D0
RDY/BSY
Figure 7. Nonvolatile Read Command Timing Diagram
on the rising edge of CLK corresponding to D0. The register write command does not affect data stored in the nonvolatile memory. Figure 6 shows the register write command timing diagram.
contents of the nonvolatile registers. Figure 7 shows the nonvolatile read command timing diagram. RDY/BSY remains high while a read is taking place.
Nonvolatile Read Command
The nonvolatile read command makes the data from the selected nonvolatile register available to external devices. Data is clocked out on DOUT during the eight clock cycles following A0. DOUT returns to a highimpedance state when CS goes high. This command has no effect on the DAC outputs, operating states, or
14
______________________________________________________________________________________
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
CS
CLK
DIN
START
C1
C0
A2
A1
A0
HIGH IMPEDANCE DOUT tCOS OUT_ AT VDD RDY/BSY (MAX5105 ONLY)
Figure 8. Nonvolatile Load Command Timing Diagram
Mute/Shutdown Modes
The MAX5105/MAX5106 feature software-controlled mute and shutdown modes. The shutdown mode places the DAC outputs in a high-impedance state and reduces quiescent current consumption to 10A (max) with all DACs disabled. Mute drives the selected DAC output to the corresponding REFL_ voltage. The volatile DAC register retains its data, and the output returns to its previous state when mute is removed. The MAX5105 also features an asynchronous MUTE input that mutes all DACs. The output buffers are individually disabled/muted with ones in the proper data bits (D7-D0) (Table 1). When all DACs are muted or shut down, the nonvolatile store command is ignored. If the mute/shutdown novolatile register is used to shut down or mute all of the DACs, use the register write command to change the operating state of the device. Do this by executing a register write command that changes the contents of the mute/shutdown volatile register. Following this, the nonvolatile store command is again recognized.
OUTPUT VOLTAGE
O NEGATIVE OFFSET
DAC CODE
Figure 9. Effect of Negative Offset (Single Supply)
Nonvolatile Load Command
The nonvolatile load command writes the contents of the selected nonvolatile register to the corresponding volatile register during the eight clock cycles following A0. This updates the respective DAC output or changes the operating state of the device on the rising edge of CLK corresponding to A0. This command does not affect the data in the nonvolatile register. Figure 8 shows the nonvolatile load command timing diagram. RDY/BSY remains high while a volatile register load is taking place.
Power-On Reset
The power-on reset (POR) controls the initialization of the MAX5105/MAX5106. During this time, the on-chip oscillator is enabled and used to load the volatile DAC and mute/shutdown registers with data from the EEPROM.
_______________________________________________________________________________________
15
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
This initialization period takes about 80s with the DAC registers loading first and the mute/shutdown register loading last. During this time, the DAC outputs are held in the mute state and the serial interface is disabled. Once the mute/shutdown register is loaded, the DAC outputs are updated to their stored data and operating states, and the serial interface is enabled.
Power Sequencing
The voltage applied to REFH_ and REFL_ should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REFH_ and REFL_ and VDD to ensure compliance with the absolute maximum ratings. Do not apply signals to the digital inputs before the device is fully powered up.
Applications Information
DAC Linearity and Offset Voltage
The output buffer can have a negative input offset voltage that would normally drive the output negative, but since there is no negative supply, the output remains at GND (Figure 9). When linearity is determined using the end-point method, it is measured between code 10 (0Ahex) and full-scale code (FFhex) after the offset and gain error are calibrated out. With a single supply, negative offset causes the output not to change with an input code transition near zero (Figure 9). Thus, the lowest code that produces a positive output is the lower endpoint.
Power-Supply Bypassing and Ground Management
Digital or AC transient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass VDD with a 0.1F capacitor, located as close to the device as possible. Bypass REF_ to GND with a 0.1F capacitor. Carefully printed circuit board ground layout minimizes crosstalk between the DAC outputs and digital inputs.
Chip Information
TRANSISTOR COUNT: 32,000 PROCESS: CMOS
External Voltage Reference
The MAX5105/MAX5106 have two reference inputs for each DAC, REFH_, and REFL_. REFH_ sets the fullscale voltage, while REFL_ sets the zero code output. REFL2 and REFL3 are internally connected to GND in the MAX5106. A 256k typical input impedance at REFH_ is code independent. The output voltage from these devices can be represented by a digitally programmable voltage source as follows: VOUT = [(VREFH_ - VREFL_) x (N / 256)] + VREFL_ where N is the decimal value of the DAC's binary input code.
16
______________________________________________________________________________________
Nonvolatile, Quad, 8-Bit DACs
Functional Diagram
VDD MUTE*
MAX5105/MAX5106
OSCILLATOR
POWER-ON RESET CIRCUIT REFH0
MAX5105 MAX5106
DAC0 NONVOLATILE REGISTER
DAC0 VOLATILE REGISTER
DAC0 OUT0 REFL0
RDY/BSY* DAC1 NONVOLATILE REGISTER DOUT 14-BIT SHIFT REGISTER/ COMMAND DECODER DAC2 NONVOLATILE REGISTER DAC2 VOLATILE REGISTER DAC1 VOLATILE REGISTER
REFH1
DAC1 OUT1 REFL1 REFH2
DIN CLK
DAC2 OUT2 REFL2*
CS REFH3 DAC3 NONVOLATILE REGISTER DAC3 VOLATILE REGISTER
DAC3 OUT3 REFL3*
MUTE/ SHUTDOWN NONVOLATILE REGISTER
MUTE/ SHUTDOWN VOLATILE REGISTER
GND
*MAX5105 ONLY MAX5106: REFL2 AND REFL3 ARE INTERNALLY CONNECTED TO GND.
_______________________________________________________________________________________
17
Nonvolatile, Quad, 8-Bit DACs MAX5105/MAX5106
Package Information
QSOP.EPS
18
______________________________________________________________________________________
Nonvolatile, Quad, 8-Bit DACs
Package Information (continued)
20L, SOIC.EPS
MAX5105/MAX5106
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX5105

	To Download MAX5105 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .