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INTEGRATED CIRCUITS
74ABT833 Octal transceiver with parity generator/checker (3-State)
Product specification IC23 Data Handbook 1993 Jun 21
Philips Semiconductors
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
FEATURES
* Low static and dynamic power dissipation with high speed and
high output drive
The 74ABT833 is an octal transceiver with a parity generator/checker and is intended for bus-oriented applications. When Output Enable A (OEA) is High, it will place the A outputs in a high impedance state. Output Enable B (OEB) controls the B outputs in the same way. The parity generator creates an odd parity output (PARITY) when OEB is Low. When OEA is Low, the parity of the B port, including the PARITY input, is checked for odd parity. When an error is detected, the error data is sent to the input of a storage register. If a Low-to-High transition happens at the clock input (CP), the error data is stored in the register and the Open-collector error flag (ERROR) will go Low. The error flag register is cleared with a Low pulse on the CLEAR input. If both OEA and OEB are Low, data will flow from the A bus to the B bus and the part is forced into an error condition which creates an inverted PARITY output. This error condition can be used by the designer for system diagnostics.
* Open-collector ERROR output with flag register * Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec Std 17 * ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200 V per Machine Model
* Power up/down 3-State * Live insertion/extraction permitted
DESCRIPTION
The 74ABT833 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay An to Bn or Bn to An Propagation delay An to PARITY Input capacitance I/O capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 3.4 7.4 4 7 50 UNIT ns ns pF pF A
ORDERING INFORMATION
PACKAGES 24-Pin Plastic DIP 24-Pin plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT833 N 74ABT833 D 74ABT833 DB 74ABT833 PW NORTH AMERICA 74ABT833 N 74ABT833 D 74ABT833 DB 74ABT833PW DH DWG NUMBER SOT222-1 SOT137-1 SOT340-1 SOT355-1
PIN CONFIGURATION
OEA 1 24 V CC 23 B0 22 B1 21 B2
PIN DESCRIPTION
SYMBOL A0 - A7 B0 - B7 OEA PIN NUMBER 2, 3, 4, 5, 6, 7, 8, 9 23, 22, 21, 20, 19, 18, 17, 16 1 14 15 10 11 13 12 24 NAME AND FUNCTION A port 3-State inputs/outputs B port 3-State inputs/outputs Enables the A outputs when Low Enables the B outputs when Low Parity output/input Error output (open collector) Clears the error flag register when Low Clock input Ground (0V) Positive supply voltage
A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 ERROR 10 CLEAR 11 GND 12 TOP VIEW
20 B3 19 B4 18 B5 17 B6 16 B7 15 PARITY 14 OEB 13 CP
OEB PARITY ERROR CLEAR CP GND VCC
SA00212
1993 Jun 21
2
853-1619 10087
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
LOGIC SYMBOL
2
3
4
5
6
7
8
9
A0 A1 A2 A3 A4 A5 A6 A7 14 1 11 13 OEB OEA CLEAR CP B0 B1 B2 B3 B4 B5 B6 B7 PARITY ERROR 15 10
23 22 21 20 19 18 17 16
SA00213
FUNCTION TABLE
INPUTS MODE A data to B bus and generate odd parity output B data to A bus and check for parity error1 A bus and B bus disabled2 OEB L H H L OEA H L H L An of Highs Odd Even (output) X Odd Even Bn + Parity of Highs (output) X X (output) An (input) Bn Z (input) OUTPUTS Bn An (input) Z An PARITY L H (input) Z H L
A data to B bus and generate inverted parity output
NOTES: 1. Error checking is detailed in the Error Flag Function Table below. 2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS MODE CLEAR H H H H L High voltage level steady state Low voltage level steady state Don't care No change High impedance "off" state Low-to-High clock transition Not a Low-to-High clock transition CP X X Bn + Parity of Highs Odd Even X X X Internal node Point "P" H L X X X Output Pre-state ERRORn-1 H X L X X ERROR OUTPUT H L L NC H
Sample Hold Clear H L X NC Z = = = = = = =
1993 Jun 21
3
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
LOGIC DIAGRAM
8 A0 - A7 8 B0 - B7
8
OEB PARITY OEA
8
8 MUX 9-bit Odd Parity Tree "P" A
} }
B 9
Sel A/B
D CP CLEAR R
ERROR
SA00214
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1993 Jun 21
4
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER Min VCC VI VIH VIL VOH IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output voltage, ERROR High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 4.5 0 2.0 0.8 5.5 -32 64 5 +85 LIMITS Max 5.5 VCC V V V V V mA mA ns/V C UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C Min VIK IOH Input clamp voltage High-level output current ERROR ONLY VCC = 4.5V; IIK = -18mA VCC = 5.5V; VOH = 5.5V; VI = VIL or VIH VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage All outputs except ERROR VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL II IOFF IPUIPD IIH + IOZH IIL + IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Low-level output voltage Input leakage current Control pins Data pins VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; VI = GND or 5.5V VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VI or VO 4.5V VCC = 2.0V; or VO = 0.5V; VI = GND or VCC; V OE = Don't care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 2.5 3.0 2.0 3.5 4.0 2.6 0.42 0.01 5 5.0 5.0 5.0 -5.0 5.0 -80 50 20 50 0.3 0.55 1.0 100 100 50 50 -50 50 -180 250 30 250 1.5 -50 Typ -0.9 Max -1.2 20 2.5 3.0 2.0 0.55 1.0 100 100 50 50 -50 50 -180 250 30 250 1.5 Tamb = -40C to +85C Min Max -1.2 20 V A V V V V A A V V A A A mA A mA A mA UNIT
Power-off leakage current Power-up/down 3-State output current3 3-State output High current 3-State output Low current Output High leakage current Output current1
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. This parameter is valid for any VCC between 0V and 2.1, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10%, a transition of up to 100sec is permitted. The ERROR output pin 10 is not included in this spec due to the open collector design.
1993 Jun 21
5
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORMS Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay An to Bn or Bn to An Propagation delay An to PARITY Propagation delay OEA to PARITY Propagation delay CLEAR to ERROR Propagation delay CP to ERROR Output enable time OEA to An or OEB to Bn, PARITY Output disable time OEA to An or OEB to Bn, PARITY 2 1 2 1 2 5 1 3 4 3 4 1.2 1.0 2.1 2.5 2.6 3.1 1.0 2.5 1.0 2.1 3.1 3.2 Tamb = +25oC VCC = +5.0V Typ 3.4 2.6 7.4 7.4 6.6 6.7 2.9 4.2 3.2 4.1 5.1 5.6 Max 4.8 4.0 9.5 9.7 8.5 8.6 4.4 5.7 5.1 5.8 7.3 7.7 Tamb = -40 to +85oC VCC = +5.0V 10% Min 1.2 1.0 2.1 2.5 2.6 3.1 1.0 2.5 1.0 2.1 3.1 3.2 Max 5.3 4.5 11.2 11.0 10.5 10.0 5.2 6.2 6.2 6.7 7.9 8.1 ns ns ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORMS Tamb = +25oC VCC = +5.0V Min ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Setup time, High or Low Bn or PARITY to CP Hold time, High or Low Bn or PARITY to CP Pulse width, High or Low CP Pulse width, Low CLEAR Recovery time CLEAR to CP 6 6 6 5 5 9.8 8.1 0.0 0.0 3.0 3.0 3.0 2.0 Typ 6.9 4.0 -3.7 -6.7 1.5 1.0 1.0 -0.3 Tamb = -40 to +85oC VCC = +5.0V 10% Min 9.8 8.1 0.0 0.0 3.0 3.0 3.0 2.0 ns ns ns ns ns UNIT
1993 Jun 21
6
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
INPUT
VM tPHL
VM tPLH
INPUT
VM tPLH
VM tPHL
OUTPUT
VM
VM
OUTPUT
VM
VM
SA00216 SA00217
Waveform 1. Propagation Delay For Inverting Output
Waveform 2. Propagation Delay For Non-Inverting Output
OEA, OEB
VM tPZH
VM tPHZ VOH -0.3V
OEA, OEB
VM tPZL
VM
tPLZ
OUTPUT
VM 0V
OUTPUT
VM
VOL +0.3V 0V
SA00238
SA00239
Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
CLEAR
VM tw(L)
VM tREC VM
Bn, PARITY
CP tPLH ERROR VM
CP
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00205
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00240
Waveform 6. Data Setup and Hold Times and Clock Pulse Width
Waveform 5. CLEAR Pulse Width, CLEAR to ERROR Delay and CLEAR to Clock Recovery Time
1993 Jun 21
7
EEEEEEEEE EEE E EEEEEEEEE EEE E EEEEEEEEE EEE E
VM VM VM VM ts(H) th(H) ts(L) th(L) tw(H) tw(L) VM VM VM
EEE EEE EEE
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS
18 16 14 12 10 8 6 4 tPHL 2 0 0 100 200 300 Load resistor () NOTE: When using Open-Collector parts, the value of the pull-up resistor greatly affects the value of the tPLH. For example, changing the specified pull-up resistor value from 500 to 100 will improve the tPLH over 300% with only a slight change in the tPHL. However, if the value of the pull-up resistor is changed, the user must make certain that the total IOL current through the resistor and the total IIL's of the receivers does not exceed the IOL maximum specification. 400 500 600
Propagation delay (ns)
tPLH
SA00241
TEST CIRCUIT AND WAVEFORM
VCC VX VIN PULSE GENERATOR RT D.U.T CL RL VOUT RX
90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90%
tW VM 10%
90%
AMP (V)
0V tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V)
Test Circuit for 3-State Outputs
POSITIVE PULSE 10%
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
LOAD VALUES
OUTPUT ERROR All other RX VX 100 VCC 500 7.0V
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SA00242
1993 Jun 21
8
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
DIP24: plastic dual in-line package; 24 leads (300 mil) SO24: plastic small outline package; 24 leads; body width 7.5 mm SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT222-1 SOT137-1 SOT340-1 SOT355-1
1993 Jun 21
9
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
NOTES
1993 Jun 21
10
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT833
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1995 All rights reserved. Printed in U.S.A.

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