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PRELIMINARY
Z86193 CPS DC-4206-01
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
Z86193
CMOS Z8(R) MICROCONTROLLER MULTIPLIER/DIVIDER/SEARCH/MERGE
GENERAL DESCRIPTION
The Z86193 is a CMOS ROMless Z8(R) microcontroller enhanced with a hardwired 16-bit x 16-bit multiplier, 32-bit/16-bit divider, three 16-bit counter/timers, search and merge instructions, Evaluation mode and a Bus Request mode. The device is code compatible with other Z8 family devices, yet it offers more powerful mathematical capabilities, data searching capabilities, and bit manipulation. The Z86193 is offered in a 64-pin VQFP package. The Z86193 provides up to 16 output address lines permitting an address space of up to 64 Kbytes each of Program or Data memory. Eight address outputs are provided by a de-multiplexed 8-bit Address Bus (A7-A0) or by a multiplexed 8-bit Address/Data Bus (AD7-AD0). The remaining eight address lines (A15-A8) can be provided by the software configuration of Port0 to output address. The Z86193 includes a bus which differs from other Z8 devices. The Z86193 provides bus control signals /RD (Read Strobe), /WR (Write Strobe), and ALE (Address Latch Enable). There are 464 8-bit registers located on-chip and organized as 444 general-purpose registers, 16 control and status registers, one reserved register, and up to three I/O port registers. The Register File is partitioned into two Register Pages. Page0 contains 208 registers and Page1 contains 208 registers. The 48 other registers are common to both Register Pages. The Register file is also divided into 29 working register groups of 16 registers each. Configuration of the registers in this format allows the use of short format instructions. There are 17 additional registers implemented in the Expanded Register file in Banks D and E. Two of the registers may be used as general-purpose, while the other 15 are used to supply data and control for the multiplier/divider unit and the additional counter/timers.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD
VSS
DC-4206-01
(2-3-95)
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PRELIMINARY
Z86193 CPS DC-4206-01
GENERAL DESCRIPTION (Continued)
/RESET /BREQ /SYNC /BACK /WAIT SCLK EVAL Port 1 8 Low Address/Data XTAL IACK ALE /RD /WR
Output Input
VCC GND
Port 3
Machine Timing, Emulation and Instruction Control
UART
ALU
Three 16-Bit Counter/Timers
FLAGS
32 / 16 Divider
Register Pointers Register File Page 0 256 x 8-Bit Register File Page 1 208 x 8-Bit Program Counter SEARCH Machine MERGE Machine
16 x 16 Multiplier
Interrupt Control
Port 2
Demultiplexed Address 4
Port 0
4
I/O (Bit Programmable)
Low Address
Address or I/O (Nibble Programmable)
Z86193 Functional Block Diagram
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PRELIMINARY
Z86193 CPS DC-4206-01
PIN CONFIGURATION
P33 P34//DM A7 P17//AD7 A6 P16/AD6 A5 P15/AD5 N/C /WAIT P24 P23 P22 P21 GND P20
N/C N/C P25 P26 P27 P31 P36 GND VCC XTAL2 XTAL1 SCLK P37 P30 /EVAL N/C
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 Z86193 24 57 VQFP 23 58 22 59 21 60 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
/BACK P14/AD4 A4 P13/AD3 A3 P12/AD2 A2 P11/AD1 A1 P10/AD0 A0 P07/A15 P06/A14 P05/A13 P04/A12 P03/A11
N/C /RESET /WR /RD ALE
/SYNC P35 VCC GND
P00/A8
64-Pin VQFP Package
P01/A9 P02/A10 /BREQ N/C
IACK
P32
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PRELIMINARY
Z86193 CPS DC-4206-01
ABSOLUTE MAXIMUM RATINGS
Symbol Description VCC TSTG TA Supply Voltage* Storage Temp Oper Ambient Temp Min -0.3 -65 Max +7.0 +150 Units V C C Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
* Voltages on all pins with respect to GND. See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram).
I OL
DUT Device Under T est V Commutation
50 pf
I OH
Test Load Diagram
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PRELIMINARY
Z86193 CPS DC-4206-01
DC ELECTRICAL CHARACTERISTICS VCC = 5.0V 10%
T A = 0C to +70C Max 7 VCC 0.8 VCC VCC 0.8 Typical @ 25C U n i t s V V V V V V V V V V V A A A mA mA A A
Sym VCH VCL VIH VIH VIL VOH VOH VOL VRH VRl IIL IOL IIR ICC ICC1 ICC2 IAL
Note:
Parameter
Min
Conditions IIN 250 A Driven by External Clock Generator Driven by External Clock Generator
Max Input Voltage Clock Input High Voltage 3.8 Clock Input Low Voltage -0.03 Input High Voltage (P0,P1,P2) 2.0 Input High Voltage (P3) 2.2 Input Low Voltage -0.3 Output High Voltge 2.4 Output High Voltage VCC -100mV Output Low Voltage Reset Input High Voltage 3.8 Reset Input Low Voltage -0.03 Input Leakage Output Leakage Reset Input Current Supply Current -2 -2
0.4 VCC 0.8 2 2 -180 120 30 20 16
IOH= -2.0 mA IOH = -100 A IOL = + 4 mA
70 20 6 5
Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 40 MHz [1] HALT Mode VIN = OV, VCC @ 40 MHz [1] STOP Mode VIN = OV, VCC [1]
Standby Current (HALT Mode) Standby Current Auto Latch Current -16
[1] All inputs driven to 0V, or Vcc and outputs floating. [2] Values are preliminary engineering estimates.
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PRELIMINARY
Z86193 CPS DC-4206-01
AC CHARACTERISTICS External Memory Read/Write Timing Diagram
/DM
20 19
Port 0
A8 - A15
16 21
Port 1
A0 - A7
2 3
D0 - D7 IN
9 10
A0 - A7
ALE
4 5
8
11
6
/RD
1 17
Port1
A0 - A7
14
D0 - D7 OUT
A0-A7
15
7
/WR
External I/O or Memory Read/Write Timing Diagram
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PRELIMINARY
Z86193 CPS DC-4206-01
AC CHARACTERISTICS External I/O or Memory Read/Write Timing Table
No 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 30 Sym TdA(ALE) ThALE(A) TdALE(DI) TwALE TdAZ(RD) TwRD TwWR TdRD(DI) ThRD(DI) TdRDWR(A) TdRDWR(ALE) TdDO(WR) ThWR(DO) TdA(DI) TdALE(RD) TdDM(ALE) TdRDWR(DM) ThRDWR(A) TdXT(SCR) TdXT(SCF) TdXT(RDF) TdXT(RDR) TdXT(WRF) TdXT(WRR) TsW(XT) ThW(XT) TsW Parameter Address Valid To ALE Fall Delay ALE Fall To Address Hold Time ALE Fall To Data In Req'd Valid Delay ALE HIGH Width Address Float To /RD Fall /RD Low Width /WR Low Width /RD Fall To Data in Req'd Valid Delay /RD Rise to Data In Hold Time /RD or /WR Rise To Address Active Delay /RD or /WR Rise To ALE Delay Data Out To /WR Fall Delay /WR Rise To Data Out Hold Time Address Valid To Data In Req'd Valid Delay ALE Fall To /RD Fall Delay /DM Valid To ALE Fall Delay /RD or /WR Rise To /DM Valid Delay /RD or /WR Rise To Adress Valid Hold Time XTAL Falling To SCLK Rising XTAL Falling To SCLK Falling XTAL Falling To /RD Falling XTAL Falling To /RD Rising XTAL Falling To/WR Falling XTAL Falling To/WR Rising Wait Set Up Time Wait Hold Time Wait Width (One Wait Time) Max 8 15 75 10 0 60 35 40 0 20 16 12 12 90 20 10 15 15 30 30 40 30 40 30 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Values based on external clock drive with a clock frequency. 2. Values are preliminary and are to be characterized. 3. When using extended memory timing, add 2TpC. 4. Timing numbers are given for minimum TpC.
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PRELIMINARY
Z86193 CPS DC-4206-01
XTAL1 (External Clock Drive) 22 23
SCLK 24 /RD 25
26 /WR
27
XTAL/SCLK To DSR and DSW Timing
T1
T2
TW
TW
TW
T3
T1
XTAL1
SCLK
ALE
/RD
32
WAIT
30
31
XTAL/SCLK To WAIT Timing
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PRELIMINARY
Z86193 CPS DC-4206-01
AC CHARACTERISTICS Additional Timing Diagram
1 3
Clock
2 7 7 2 3
T IN
4 6 5
IRQ N
8 9
Additional Timing
AC CHARACTERISTICS Additional Timing Table
TA = 0C to +70C 40 MHz Min Max 25 8 75 3 TpC 8 TpC 100 70 5 TpC 3 TpC 1000 4
No 1 2 3 4 5 6 7 8A 8B 9
Symbol Parameter TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Input Clock Period Clock Imput Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Times Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times
Units ns ns ns ns ns ns ns ns ns ns
Notes [1] [1] [1] [2] [2] [2] [2] [2,4] [2,5] [2,3]
Notes: [1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request through Port 3. [4] Interrupt request through Port 3 (P33-P31). [5] Interrupt request through Port 30.
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PRELIMINARY
Z86193 CPS DC-4206-01
AC CHARACTERISTICS Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
1
3
2
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Output Handshake Timing
10
PRELIMINARY
Z86193 CPS DC-4206-01
AC CHARACTERISTICS Handshake Timing Table
No Direction 1 2 3 4 5 6 7 8 9 10 11 TsDI(DAV) ThDI(DAV) TwDAV TdDAVIf(RDYf) TdDAVIr(RDYr) TdRDYOr(DAVIf) TdD0(DAV) TdDAV0f(RDYIf) TdRDYIf(DAVOr) TwRDY TdRDYIr(DAVOf) Symbol Data In Setup Time to /DAV RDY to Data In Hold Time /DAV Width /DAV to RDY Delay DAV Rise to RDY Wait Time RDY Rise to DAV Delay Data Out to DAV Delay /DAV to RDY Delay RDY to /DAV Rise Delay RDY Width RDY Rise to DAV Wait Time T A = 0C to +70C Parameter Min 0 0 80 120 40 0 TpC 0 120 80 40 Max ns ns ns ns ns ns ns ns ns ns ns Data Units In In In In In In Out Out Out Out Out
Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-conformance with some aspects of the CPS may be Low Margin: Customer is advised that since this is a Preliminary CPS, this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other
(c) 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues.
limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056
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