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| MT90500 Multi-Channel ATM AAL1 SAR Features * AAL1 Segmentation and Reassembly device compatible with Structured Data Transfer (SDT) as per ANSI T1.630 and ITU I.363 standards Transports 64kbps and N x 64kbps traffic over ATM AAL1 cells (also over AAL5 or AAL0) Simultaneous processing of up to 1024 bidirectional Virtual Circuits Flexible aggregation capabilities (Nx64) to allow any combination of 64 kbps channels while maintaining frame integrity (DS0 grooming) Support for clock recovery - Adaptive Clock Recovery, Synchronous Residual Time Stamp (SRTS), or external Primary UTOPIA port (Level 1, 25 MHz) for connection to external PHY devices with data throughput of up to 155 Mbps Secondary UTOPIA port for connection to an external AAL5 SAR processor, or for chaining multiple MT90500 devices 16-bit microprocessor port, configurable to Motorola or Intel timing TDM bus provides 16 bidirectional serial TDM DS5171 ISSUE 4 April 1999 Ordering Information MT90500AL 240 Pin Plastic QFP -40 to +85 C streams at 2.048, 4.096, or 8.192 Mbps for up to 2048 TDM 64 kbps channels Compatible with ST-BUS, MVIP, H-MVIP and SCSA interfaces Supports master and slave TDM bus clock operation Loopback function at TDM bus interface Local TDM bus provides clocks, input pin and output pin for 2.048 Mbps operation Master clock rate up to 60 MHz Dual rails (3.3V for power minimization, 5V for standard I/O) IEEE1149 (JTAG) interface * * * * * * * * * * * * * * * VC Lookup Tables TX / RX Control Structures and Circular Buffers External Synchronous SRAM TDM Bus 16 Lines 2048 x 64 kbps (max.) Local TDM Bus 32 x 64 kbps in 32 x 64 kbps out Clock Signals TDM Module External Memory Controller TDM Bus Interface TX UTOPIA MUX TX AAL1 SAR Internal TDM Frame Buffer TDM Clock Logic To/From External PHY Main UTOPIA Interface RX UTOPIA UTOPIA Module From External ATM SAR Secondary UTOPIA Interface RX AAL1 SAR Clock Recovery Registers Microprocessor Interface Boundary Scan JTAG Interface 16-bit Microprocessor Address and Data Buses Figure A - MT90500 Block Diagram 1 MT90500 Applications * * * B-ISDN (Broadband ISDN) systems requiring flexible N x 64kbps transport Connecting TDM backplane to TDM backplane over ATM network (GO-MVIP MC4, or other) Systems requiring ANSI T1.630 Structured Data Transfer services for 1 to 122 TDM channels per VC Systems requiring ITU-T I.363.1 circuit transport over Structured Data Transfer for 1 to 96 TDM channels per VC Systems requiring AF-VTOA-0078.000 (ATM Forum CES v2.0) "Logical Nx64 Basic Service" Systems requiring AF-VTOA-0083.000 Voice and Telephony over ATM (CBR-AAL5). Mapping between CBR-AAL0, CBR-AAL5, and AAL1 Mapping between CBR partially-filled cells and full cells Mapping between CBR single-voice cells and Nx64 cells ATM uplink for expansion of COs, PBXs, or open switching platforms using an adjunct ATM switch ATM Public Network access for PBX or CO ATM Edge Switches and CPE IntegratedAccess over ATM TDM traffic transfer over an asynchronous cell bus Systems requiring Nx64 over CBR-AAL5. Description The MT90500 Multi-Channel AAL1 SAR is a highly integrated solution which allows systems based on a telecom bus to be interfaced to ATM networks using ATM Adaptation Layer 1 (AAL1), ATM Adaptation Layer 5 (AAL5) and ATM Adaptation Layer 0 (AAL0). The MT90500 can be connected directly to a ST-BUS time division multiplexed (TDM) backplane containing up to 1024 full duplex 64kbps channels. Up to 1024 bi-directional ATM VC connections can be simultaneously processed by the MT90500 AAL1 SAR device. On the synchronous TDM bus side, the MT90500 device interfaces with sixteen bidirectional ST-BUS serial links operating at 2.048, 4.096 or 8.192 Mbps. TDM bus compatibility with MVIP-90, H-MVIP, and SCSA interfaces is also provided. On the ATM interface side, the MT90500 device meets the ATM Forum standard UTOPIA Bus Level 1. This supports connection to a range of standard physical layer (PHY) transceivers. The MT90500 provides a built-in UTOPIA multiplexer which allows external ATM cells to be multiplexed with internally-generated cells in the transmit direction. This feature can be used to connect another MT90500 (to expand the TDM bandwidth of the system to 4096 TDM channels), or to connect an external AAL5 SAR (to multiplex non-CBR ATM cell traffic with the MT90500 CBR stream). * * * * * * * * * * * Off-the-shelf ATM PHY Device Primary UTOPIA Port Local Memory External Synchronous SRAM 16-bit CPU port for internal register and external memory programming MT90500 CPU AAL1 SAR Secondary UTOPIA Port Off-the-shelf SAR Device (AAL5) TDM Data, Clock and Sync Lines MVIP-90 H-MVIP ST-BUS SCSA IDL Figure B - MT90500 Device Application Block Diagram 2 MT90500 Table of Contents 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3 ATM Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2. Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Serial TDM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 CBR ATM Cell Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 UTOPIA Interface and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.1 Module Level Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.2 TX_SAR Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.3 RX_SAR Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.4 UTOPIA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.5 TDM Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8.6 Timing Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9 Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9.1 RX_SAR Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9.2 TDM Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9.3 Timing Recovery Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 TDM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1 TDM Clock Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1.1 TDM Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1.2 REF8KCLK Selection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1.1.3 Main TDM Bus Timing and Clock Generation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1.4 TDM Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1.5 Clock Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.2 TDM Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.1 Main TDM Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.2 TDM Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.3 Per-channel Output Enable Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.4 Local Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.5 Local Bus Data Transfer Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.3 TDM Data to External Memory Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.3.2 Transmit Circular Buffer Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.3.3 Transmit Circular Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.4 External Memory to TDM Data Output Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.4.2 External Memory to Internal Memory Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 External Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 TX_SAR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1 TX_SAR Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1.2 Supported ATM Cell Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1.3 Transmit Event Scheduler Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.1.3.2 Fixed TDM Payload Schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.1.3.3 AAL1 Long/Short Schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.1.3.4 Other Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3 MT90500 4.3.2 TX_SAR Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.3.2.1 Transmit Event Schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.3.2.2 Transmit Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.3.3 Non-CBR Data Cell Transmission Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.4 The RX_SAR Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.4.1 RX_SAR Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.4.2 RX_SAR Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.4.2.1 RX_SAR Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.4.2.2 RX_SAR Error Counter and Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.4.2.3 Receive Overruns and Underruns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4.4.2.4 Lost Cell Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.5 UTOPIA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 4.5.1 UTOPIA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 4.5.2 Cell Transmission and Mux Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.5.3 Receive Cell Selection Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.5.4 Non-CBR Data Cell Reception Ability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4.6 Clock Recovery from ATM Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.6.1 Adaptive Clock Recovery Sub-Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.6.2 SRTS Clock Recovery Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.6.2.1 Transmit SRTS Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.6.2.2 Receive SRTS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4.7 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.2 A Programming Example - How to Set Up a VC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.7.3 Microprocessor Access and Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.8 Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.8.1 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.8.2 JTAG ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 4.8.3 Boundary Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 4.8.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.1.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.1.2 Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.1.3 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.2 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.2.1 Microprocessor Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.2.2 TX_SAR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 5.2.3 RX_SAR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 5.2.4 UTOPIA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 5.2.5 TDM Interface and Clock Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 5.2.6 TDM Time Slot Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 6. Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 6.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 6.2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.2.1 Main TDM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.2.2 Local TDM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 6.2.3 CPU Interface - Accessing Registers and External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 6.2.4 Interface with External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 6.2.5 UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 6.2.5.1 Primary UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 6.2.5.2 Secondary UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 6.2.6 SRTS User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 6.2.7 Message Channel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 6.2.8 Boundary-Scan Test Access Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 7. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 7.1 Board Level Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 4 MT90500 7.2 System Level Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.3 TDM Clock Recovery Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.3.2 SRTS Clock Recovery Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.3.3 Free-running Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7.4 External Memory Space and Bandwidth Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.4.1 External Memory Space Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.4.2 Memory Structure Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7.4.3 External Memory Bandwidth Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.5 CBR Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.6 Other Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.6.1 Payload Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.6.2 TDM Switching and Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.6.3 DS0 Trunking, or Dynamic TDM channel re-mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 7.6.4 SCSA Message Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8. Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5 MT90500 List of Figures Figure 1 Figure 2. Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 17 Figure 16 Figure 18 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38. Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 6 MT90500 Block Diagram...................................................................................................................12 Pin Connections ................................................................................................................................26 TDM Clock Selection and Generation Logic .....................................................................................29 TDM Frame Buffer to External Memory Transfer..............................................................................33 Transmit Circular Buffer Control Structure ........................................................................................34 External Memory to TDM Frame Buffer Transfer..............................................................................35 External Memory to Internal Memory Control Structure....................................................................37 Memory Read Pipeline Length..........................................................................................................38 Logical Byte Address vs. Physical Address and Memory Banks ......................................................39 Read / Write Turnaround Cycles.......................................................................................................40 Read / Read Turnaround Cycles.......................................................................................................41 Read / Write turnaround Cycles ........................................................................................................41 AAL1 ATM Cell Format .....................................................................................................................42 Partially-Filled AAL1 and CBR-AAL0 Cell Formats...........................................................................43 CBR-AAL5 Cell Format ....................................................................................................................44 Transmit Event Scheduler.................................................................................................................49 Transmit Control Structure Format (CBR-AAL5)...............................................................................50 Transmit Control Structure Format (AAL1 & CBR-AAL0) .................................................................51 a: Sample Three-Channel Transmit Control Structure (AAL1/CBR-AAL0) .......................................53 b: Sample One-Channel Transmit Control Structure (CBR-AAL5) ...................................................53 Overview of CBR Data Transmission Process..................................................................................54 VC Pointer For Scheduler-Controlled Non-CBR Data Cell ...............................................................55 Transmit Non-CBR Data Cell Structure Format ................................................................................56 RX_SAR Control Structure................................................................................................................58 Overrun and Underrun Situations .....................................................................................................60 MT90500 Daisy Chain Example........................................................................................................62 Mux and Internal FIFO Sub-Module Block Diagram .........................................................................63 Receive Cell Selection Process ........................................................................................................65 MT90500 Cell Receive Process........................................................................................................66 Look-up Table Non-CBR Data Entry.................................................................................................67 Received Non-CBR Data Cell Internal Format..................................................................................68 Overview of CBR Data Reception Process.......................................................................................69 Adaptive Clock Recovery Sub-Module (Simplified Functional Block Diagram).................................70 Timing Reference Cell Processing State Machine............................................................................71 Transmit SRTS Operation.................................................................................................................73 Receive SRTS Operation..................................................................................................................74 Clock Recovery Using SRTS Method (Hardware) ............................................................................75 Clock Recovery Using SRTS Method (CPU) ....................................................................................76 A Typical JTAG Test Connection ......................................................................................................79 MT90500 Interrupt Structure .............................................................................................................81 Nominal TDM Bus Timing ...............................................................................................................114 Main TDM Bus Output Clocking Parameters - Positive Frame Pulse .............................................115 Main TDM Bus Output Clocking Parameters - Negative Frame Pulse ...........................................115 Main TDM Bus - Serial Output Timing ............................................................................................116 Main TDM Bus - 2/4 Sampling ........................................................................................................118 Main TDM Bus - 3/4 Sampling ........................................................................................................118 Main TDM Bus - 4/4 Sampling ........................................................................................................119 Local TDM Bus Output Parameters - Positive Frame Pulse ...........................................................121 MT90500 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Local TDM Bus Output Parameters - Negative Frame Pulse ........................................................ 121 Local TDM Bus - Positive Frame Pulse, 2/4 Sampling .................................................................. 122 Local TDM Bus - Negative Frame Pulse, 3/4 Sampling................................................................. 123 Local TDM Bus - Negative Frame Pulse, 4/4 Sampling................................................................. 123 Intel CPU Interface Timing - Read Access..................................................................................... 124 Intel CPU Interface Timing - Write Access..................................................................................... 125 Motorola CPU Interface Timing - Read Access ............................................................................. 126 Motorola CPU Interface Timing - Write Access.............................................................................. 127 External Memory Interface Timing - Read Cycle ........................................................................... 129 External Memory Interface Timing - Write Cycle............................................................................ 130 Primary UTOPIA Bus - Transmit Timing ........................................................................................ 131 Primary UTOPIA Bus - Receive Timing ......................................................................................... 132 Secondary UTOPIA Interface......................................................................................................... 133 SRTS User Interface Timing .......................................................................................................... 134 Message Channel Timing .............................................................................................................. 135 MT90500 Device Application Block Diagram ................................................................................. 137 UTOPIA Bus Interconnections for Two MT90500s and an AAL5 SAR .......................................... 139 The MT90500 within a LAN Hub .................................................................................................... 141 Using the MT90500 with External SAR and ATM Links in a LAN Environment............................. 142 Access Product using Internal High Speed Cell Bus on the Backplane......................................... 142 TDM Traffic Transport Over a Cell Bus.......................................................................................... 143 Connecting CTI Platforms to ATM LANs........................................................................................ 143 The GO-MVIP, PC-ATM Bus Standard Architecture...................................................................... 144 SRTS Clocking Application ............................................................................................................ 146 TDM Payload Switching ................................................................................................................. 154 TDM-to-TDM Loopback/Switching ................................................................................................. 155 SCSA Message Bus Application ................................................................................................... 156 7 MT90500 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 8 Primary UTOPIA Bus Pins ................................................................................................................19 Secondary UTOPIA Bus Pins ...........................................................................................................20 Microprocessor Bus Interface Pins ...................................................................................................20 External Memory Interface Pins ........................................................................................................21 Master Clock, Test, and Power Pins .................................................................................................22 TDM Port Pins...................................................................................................................................23 Reset State of I/O and Output Pins...................................................................................................24 Pinout Summary................................................................................................................................25 Memory Size Combinations ..............................................................................................................39 Effect of PSEL Field on P-byte Generation.......................................................................................53 Register Summary ............................................................................................................................82 Main Control Register .......................................................................................................................84 Main Status Register.........................................................................................................................84 Window to External Memory Register - CPU ....................................................................................85 Read Parity Register .........................................................................................................................85 Memory Configuration Register ........................................................................................................86 TX_SAR Control Register .................................................................................................................87 TX_SAR Status Register...................................................................................................................87 TX_SAR Scheduler Base Register ...................................................................................................88 TX_SAR Frame End Register ...........................................................................................................88 TX_SAR End Ratio Register .............................................................................................................88 TX_SAR Control Structure Base Address Register ..........................................................................89 Transmit Data Cell FIFO Base Address Register .............................................................................89 Transmit Data Cell FIFO Write Pointer Register ...............................................................................89 Transmit Data Cell FIFO Read Pointer Register...............................................................................90 RX_SAR Control Register.................................................................................................................91 RX_SAR Status Register ..................................................................................................................92 RX_SAR Misc. Event ID Register .....................................................................................................92 RX_SAR Misc. Event Counter Register ............................................................................................92 RX_SAR Underrun Event ID Register...............................................................................................93 RX_SAR Underrun Event Counter Register .....................................................................................93 RX_SAR Overrun Event ID Register.................................................................................................93 RX_SAR Overrun Event Counter Register .......................................................................................93 UTOPIA Control Register..................................................................................................................94 UTOPIA Status Register ...................................................................................................................94 VPI / VCI Concatenation Register.....................................................................................................95 VPI Match Register ...........................................................................................................................95 VPI Mask Register ............................................................................................................................95 VCI Match Register ...........................................................................................................................95 VCI Mask Register ............................................................................................................................96 VPI Timing Register ..........................................................................................................................96 VCI Timing Register ..........................................................................................................................96 Lookup Table Base Address Register...............................................................................................96 Receive Data Cell FIFO Base Address Register ..............................................................................97 Receive Data Cell FIFO Write Pointer Register ................................................................................97 Receive Data Cell FIFO Read Pointer Register................................................................................97 TDM Interface Control Register ........................................................................................................98 TDM Interface Status Register..........................................................................................................99 MT90500 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 TDM I/O Register ........................................................................................................................... 100 TDM Bus Type Register................................................................................................................. 101 Local Bus Type Register ................................................................................................................ 102 TDM Bus to Local Bus Transfer Register....................................................................................... 102 Local Bus to TDM Bus Transfer Register....................................................................................... 103 TX Circular Buffer Control Structure Base Register....................................................................... 103 External to Internal Memory Control Structure Base Register ....................................................... 103 TX Circular Buffer Base Address Register..................................................................................... 104 TDM Read Underrun Address Register ......................................................................................... 104 TDM Read Underrun Count Register............................................................................................. 104 Clock Module General Control Register......................................................................................... 104 Clock Module General Status Register .......................................................................................... 105 Master Clock Generation Control Register .................................................................................... 106 Master Clock / CLKx2 Division Factor............................................................................................ 107 Timing Reference Processing Control Register ............................................................................. 107 Event Count Register ..................................................................................................................... 108 CLKx1 Count - Low Register.......................................................................................................... 108 CLKx1 Count - High Register......................................................................................................... 108 DIVX Register ................................................................................................................................ 109 DIVX Ratio Register ....................................................................................................................... 109 SRTS Transmit Gapping Divider Register ..................................................................................... 109 SRTS Transmit Byte Counter Register .......................................................................................... 110 SRTS Receive Gapping Divider Register ...................................................................................... 110 SRTS Receive Byte Counter Register ........................................................................................... 110 Output Enable Registers ................................................................................................................ 111 Absolute Maximum Ratings ........................................................................................................... 112 Recommended Operating Conditions ............................................................................................ 112 DC Characteristics ......................................................................................................................... 112 Main TDM Bus Output Clock Parameters ...................................................................................... 114 Main TDM Bus Data Output Parameters ....................................................................................... 116 Main TDM Bus Input Clock Parameters......................................................................................... 117 Main TDM Bus Input Data Parameters .......................................................................................... 117 Local TDM Bus Clock Parameters ................................................................................................. 120 Local TDM Bus Data Output Parameters....................................................................................... 120 Local TDM Bus Data Input Parameters ......................................................................................... 122 Intel Microprocessor Interface Timing - Read Cycle Parameters................................................... 124 Intel Microprocessor Interface Timing - Write Cycle Parameters................................................... 125 Motorola Microprocessor Interface Timing - Read Cycle Parameters ........................................... 126 Motorola Microprocessor Interface Timing - Write Cycle Parameters............................................ 127 MCLK - Master Clock Input Parameters ........................................................................................ 128 External Memory Interface Timing - Clock Parameters ................................................................. 128 External Memory Interface Timing - Read Cycle Parameters........................................................ 128 External Memory Interface Timing - Write Cycle Parameters ........................................................ 128 Primary UTOPIA Interface Parameters - Transmit......................................................................... 131 Primary UTOPIA Interface Parameters - Receive.......................................................................... 132 Secondary UTOPIA Parameters Timing ........................................................................................ 133 SRTS Interface Parameters ........................................................................................................... 134 Message Channel Parameters....................................................................................................... 134 Boundary-Scan Test Access Port Timing ...................................................................................... 136 MT90500 Connections to 18-bit Synchronous SRAM.................................................................... 138 9 MT90500 Table 99 Table 100 Table 101 Table 102 Table 103 MT90500 Connections to 32/36-bit Synchronous SRAM................................................................138 MT90500 UTOPIA Signal Directions...............................................................................................140 Recommended TDM Channel Numbers for SRTS VCs .................................................................145 Limits on CDV on Receive SRTS VC..............................................................................................146 Summary of External Memory Structures .......................................................................................149 10 MT90500 1. 1.1 Introduction Functional Overview The Mitel MT90500 Multi-Channel AAL1 SAR bridges a standard isochronous TDM (Time Division Multiplexed) backplane to a standard ATM (Asynchronous Transfer Mode) bus. On the TDM bus side, the MT90500 can interface to 16 bidirectional TDM bus links operating at 2.048, 4.096 or 8.192 Mbps (compatible with MVIP / HMVIP, SCSA and Mitel ST-BUS). On the ATM interface side, the MT90500 provides the UTOPIA bus standardized by the ATM Forum. The device provides the AAL1 Structured Data Transfer (referred to as SDT from now on in this document) and pointerless Structured Data Transfer mappings defined by ANSI T1.6301993 and ITU-T I.363. In addition, the MT90500 provides CBR (Constant Bit Rate) mapping of TDM to AAL0, and to AAL5 (CBR-AAL5). In all data transfer formats, the user simply ports the T1/E1, T3/E3, etc. traffic onto the TDM backplane before applying it to the MT90500. As well, the device also supports TDM clock recovery using adaptive, SRTS, or external clock recovery. In the receive direction, ATM cells with VCs destined for the MT90500 are extracted from the UTOPIA bus and sent toward the TDM interface. In the transmit direction, the MT90500 provides multiplexing capabilities at the UTOPIA interface to allow the use of an external AAL5 SAR device, or multiple MT90500 devices. This is useful when CBR data and VBR/ABR/UBR data traffic must be transmitted from the local node on the same physical link. As well, the ability to multiplex internal AAL1 cells with external AAL5 cells can be used to interleave associated signalling cells and control messages with the AAL1 CBR traffic. The MT90500 also offers some internal support for non-CBR data traffic. If the application's signalling (nonCBR) data throughput is not high, the MT90500 can transmit and receive AAL5 (or other non-CBR data) to / from a pair of FIFOs. This requires the microprocessor to perform SAR functions via software, but may remove the requirement for an external data SAR. Alternatively, if standard AAL5 signalling is not required by the system, the user can use some TDM channels for HDLC or proprietary signalling. Segmentation and reassembly of TDM data to / from ATM cells is highly flexible. The MT90500 allows the user to select one or more TDM channels to be carried on an ATM logical connection with associated VPI/VCI. The number of TDM channels (1 to 122), the VPI/VCI, the data transfer method (SDT or pointerless Structured Data Transfer), cell partial-fill level, and the AAL (AAL1, CBR-AAL5, or CBR-AAL0) are all programmable. The time slot assignment circuit has 64 kbps granularity and allows a group of TDM channels to be carried on a single ATM logical channel (channel grooming). There is no limitation for distributing n x 64 channels on the TDM bus (i.e. TDM channels on a given VC can be concatenated or dispersed anywhere on the 16 serial data streams). Up to 1024 bidirectional virtual circuits (VCs) can be handled simultaneously by the internal AAL1 processors. At the maximum TDM rate of 8.192 Mbps, up to 2048 input/output 64 kbps channels are available (1024 bidirectional TDM channels). If the ATM VCs are carrying multiple TDM channels (n x 64), less VCs will be created. The user is given the ability to flexibly define which 64 kbps channels will be converted into ATM VCs. It should be noted that since the MT90500's serial TDM port is fully bidirectional, the ATM logical connections can be defined as full duplex channels (e.g. voice conversation) or one-way connections (e.g. video playback). Using the full duplex capabilities, up to 1024 simultaneous phone calls could be handled by the MT90500. The MT90500 allows the user to scale the size of the external synchronous memory to suit the application. The external memory's size is influenced by the number of virtual circuits required, the number of TDM channels being handled, and the amount of cell delay variation (CDV) tolerance required for the receive VCs. Userdefined lookup tables, data cell FIFOs, and multiple event schedulers also influence the amount of external memory required. The MT90500 supports two clocking schemes on the TDM bus: clock master and clock slave. In clock master, the MT90500 drives the clocks onto the TDM backplane (the TDM clock is recovered from an incoming ATM VC, or from an external source). In clock slave mode, the MT90500 receives its 8 kHz framing and clocks (4.096, 8.192 or 16.384 MHz) from the TDM backplane, and times its internal functions from that. Figure 1 on page 12 shows the MT90500 block diagram. The Applications section of this document illustrates several connectivity options with external PHY and SAR devices. 11 MT90500 VC Look-up Tables TX / RX Control Structures and Circular Buffers External Synchronous SRAM MT90500 External Memory Controller TDM Module TDM Bus Interface Logic To/From External PHY Main UTOPIA Interface TX UTOPIA MUX TX AAL1 SAR TDM Bus 16 lines 2048 x 64kbps (max.) Local TDM Bus 32 x 64 kbps in / 32 x 64 kbps out Clock Signals Internal TDM Frame Buffer TDM Clock Logic RX UTOPIA BLOCK RX AAL1 SAR Clock Recovery From External SAR Secondary UTOPIA Interface UTOPIA Module Registers BoundaryScan Logic Microprocessor Interface Logic JTAG Interface 16-bit Microprocessor Interface Figure 1 - MT90500 Block Diagram 1.2 Reference Documents MT90500 Programmer's Manual. MSAN-171 - TDM Clock Recovery from CBR-over-ATM Links Using the MT90500. ITU-T Rec. I.363.1, "B-ISDN ATM Adaptation Layer Specification: Type 1 AAL," 08/1996. ANSI T1.630, "Broadband ISDN - ATM Adaptation Layer for Constant Bit Rate Services Functionality and Specification," 1993. AF-PHY-0017, "UTOPIA, An ATM-PHY Interface Specification: Level 1, Version 2.01," March 21, 1994. AF-VTOA-0078.000, "Circuit Emulation Service Interoperability Specification, Version 2.0," Jan. 1997. AF-VTOA-0083.000, "Voice and Telephony Over ATM to the Desktop Specification, Version 2.0," May 1997. M. Noorchasm et al., "Buffer Design for Constant Bit Rate Services in Presence of Cell Delay Variation," ATM Forum Contribution 95-1454. Paul E. Fleischer and Chi-Leung Lau, "Synchronous Residual Time Stamp for Timing Recovery in a Broadband Network," United States Patent 5,260,978, Nov. 1993. IEEE Std. 1149.1a-1993, "IEEE Standard Test Access Port and Boundary Scan Architecture." 12 MT90500 1.3 ATM Glossary AAL - ATM Adaptation Layer; standardized protocols used to translate higher layer services from multiple applications into the size and format of an ATM cell. AAL0 - native ATM cell transmission; proprietary protocol featuring 5-byte header and 48-byte user payload. AAL1 - ATM Adaptation Layer used for the transport of constant bit rate, time-dependent traffic (e.g. voice, video); requires transfer of timing information between source and destination; maximum of 47-bytes of user data permitted in payload as an additional header byte is required to provide sequencing information. AAL5 - ATM Adaptation Layer usually used for the transport of variable bit rate, delay-tolerant data traffic and signalling which requires little sequencing or error-detection support. ANSI T1.630 - American National Standards Institute specification: Broadband ISDN - ATM Adaptation Layer for Constant Bit Rate Services Functionality and Specification. Asynchronous - 1. Not synchronous; not periodic. 2. The temporal property of being sourced from independent timing references. Asynchronous signals have different frequencies, and no fixed phase relationship. 3. In telecom, data which is not synchronized to the public network clock. 4. The condition or state when an entity is unable to determine, prior to its occurrence, exactly when an event will transpire. ATM - Asynchronous Transfer Mode; a method in which information to be transferred is organized into fixedlength cells; asynchronous in the sense that the recurrence of cells containing information from an individual user is not necessarily periodic. (While ATM cells are transmitted synchronously to maintain clock between sender and receiver, the sender transmits data cells when it has something to send and transmits empty cells when idle, and is not limited to transmitting data every Nth cell.) Cell - fixed-size information package consisting of 53 bytes (octets) of data; of these, 5 bytes represent the cell header and 48 bytes carry the user payload and required overhead. CBR - Constant Bit Rate; an ATM service category supporting a constant or guaranteed rate, with timing control and strict performance parameters. Used for services such as voice, video, or circuit emulation. CDV - Cell Delay Variation; a QoS parameter that measures the peak-to-peak cell delay through the network; results from buffering and cell scheduling. CES - Circuit Emulation Service; ATM Forum service providing a virtual circuit which emulates the characteristics of a constant bit rate, dedicated-bandwidth circuit (e.g. T1). CLP - Cell Loss Priority; a 1-bit field in the ATM cell header that corresponds to the loss priority of a cell; cells with CLP = 1 can be discarded in a congestion situation. CSI - Convergence Sublayer Indication bit in the AAL1 header byte; when present in an even-numbered cell using SDT, indicates the presence of a pointer byte; used to transport RTS values in odd-numbered cells using SRTS for clock recovery. GFC - Generic Flow Control; 4-bit field in the ATM header used for local functions (not carried end-to-end); default value is "0000", meaning that GFC protocol is not enforced. HEC - Header Error Control; using the fifth octet in the ATM cell header, ATM equipment (usually the PHY) may check for an error and correct the contents of the header; CRC algorithm allows for single-error correction and multiple-error detection. I.363 - ITU-T Recommendation specifying the AALs for B-ISDN (Broadband ISDN). Isochronous - The temporal property of an event or signal recurring at known periodic time intervals (e.g. 125 s). Isochronous signals are dependent on some uniform timing, or carry their own timing information embedded as part of the signal. Examples are DS-1/T1, E1 and TDM in general. From the root words, "iso" meaning equal, and "chronous" meaning time. OAM bit - Operations, Administration and Maintenance; MSB within the PTI field of the ATM cell header which indicates if the ATM cell carries management information such as fault indications. Plesiochronous - The temporal property of being arbitrarily close in frequency to some defined precision. Plesiochronous signals occur at nominally the same rate, any variation in rate being constrained within specific limits. Since they are not identical, over the long term they will be skewed from each other. This will force a 13 MT90500 switch to occasionally repeat or delete data in order to handle buffer underflow or overflow. (In telecommunications, this is known as a frame slip). PHY - Physical Layer; bottom layer of the ATM Reference Model; provides ATM cell transmission over the physical interfaces that interconnect the various ATM devices. PTI - Payload Type Identifier; 3-bit field in the ATM cell header - MSB indicates if the cell contains OAM information or user data; LSB indicates that a AAL5 cell is the final cell in a frame. QoS - Quality of Service; ATM performance parameters that characterize the transmission quality over a given VC (e.g cell delay variation; cell transfer delay, cell loss ratio). RTS - Residual Time Stamp; see SRTS. SAR - Segmentation and Reassembly; method of partitioning, at the source, frames into ATM cells and reassembling, at the destination, these cells back into information frames; lower sublayer of the AAL which inserts data from the information frames into cells and then adds the required header, trailer, and/or padding bytes to create 48-byte payloads to be transmitted to the ATM layer. SDT - Structured Data Transfer; format used within AAL1 for blocks consisting of N * 64 kbps channels; blocks are segmented into cells for transfer and additional overhead bytes (pointers) are used to indicate structure boundaries within cells (therefore aiding clock recovery). SN - Sequence Number; 4-bit field in the AAL1 header byte used as a sequence counter for detecting lost or misinserted ATM cells. SNP - Sequence Number Protection; 4-bit field in the AAL1 header byte consisting of a CRC and a parity bit which are designed to provide error-correction on the SN. SRTS - Synchronous Residual Time Stamp; method for clock recovery in which difference signals between a source clock and the network reference clock (time stamps) are transmitted to allow reconstruction of the source clock. The destination reconstructs the source clock based on the time stamps and the network reference clock. (Note that the same network reference clock is required at both ends.) SSRAM - Synchronous Static RAM. Synchronous - 1. The temporal property of being sourced from the same timing reference. Synchronous signals have the same frequency, and a fixed (often implied to be zero) phase offset. 2. A mode of transmission in which the sending and receiving terminal equipment are operating continually at the same rate and are maintained in a desired phase relationship by an appropriate means. UDT - Unstructured Data Transfer; format used within AAL1 for transmission of user data without regard for structure boundaries (e.g. circuit emulation); term used within ANSI standard - not explicitly stated in ITU. UTOPIA - Universal Test and Operations Physical Interface for ATM; a PHY-level interface to provide connectivity between ATM components. VC - Virtual Channel; one of several logical connections defined within a virtual path (VP) between two ATM devices; provides sequential, unidirectional transport of ATM cells. Also Virtual Circuit. VCI - Virtual Channel Identifier; 16-bit value in the ATM cell header that provides a unique identifier for the virtual channel (VC) within a virtual path (VP) that carries a particular cell. VP - Virtual Path; a unidirectional logical connection between two ATM devices; consists of a set of virtual channels (VC). VPI - Virtual Path Identifier; 8-bit value in the ATM cell header that indicates the virtual path (VP) to which a cell belongs. VTOA - Voice and Telephony over ATM; intended to provide voice connectivity to the desktop, and to provide interoperability with existing N-ISDN and PBX services. Glossary References: The ATM Glossary - ATM Year 97 - Version 2.1, March 1997 The ATM Forum Glossary - May 1997 ATM and Networking Glossary (http://www.techguide.com/comm/index.html) Mitel Semiconductor Glossary of Telecommunications Terms - May 1995. 14 MT90500 2. 2.1 Features General * TDM (Time Division Multiplexed) bus composed of 16 serial streams running at up to 8.192 Mbps, plus related clocks and control signals, configurable by software. This interface also includes various signals for TDM clock signal generation. This bus carries telecom or other data in N x 64 kbps streams. Local serial TDM bus interface (a TDM input pin, a TDM output pin, and clocks). A primary UTOPIA bus running at up to 25 MHz, suitable for connection to a 25 Mbps or 155 Mbps PHY device. A secondary UTOPIA bus, for connection of an optional external SAR (e.g. data) device running at up to 25 MHz. In this case, the MT90500 device emulates a PHY device for the external SAR. A synchronous 36-bit wide memory interface running at up to 60 MHz. A 16-bit microprocessor interface used for device configuration, status, and control. Signals for general clocking, reset, and JTAG boundary-scan. The MT90500 device external interfaces are: * * * * * * 2.2 Serial TDM Bus * * * Compatible with ST-BUS, MVIP, H-MVIP, IDL, and SCSA interfaces. Provides 16 bidirectional serial streams that can operate at TDM data rates of 2.048, 4.096 or 8.192 Mbps for up to 2048 TDM 64 kbps channels (1024 bidirectional DS0 channels: supports 32 E1 framers, or 42 T1 framers, or 10 J2 framers). Serial TDM bus clocking schemes: TDM timing bus slave (MT90500 slaved to TDM bus), TDM timing bus master (MT90500 drives clocks onto TDM bus - freerun, or synchronized to 8 kHz reference) and TDM bus master-alternate (MT90500 slaved to TDM bus, but ready to switch to 8 kHz reference). Additional Local TDM Bus interface (2.048 Mbps) allows local TDM devices to access the main TDM bus. * 2.3 CBR ATM Cell Processor * * * * * * * * * * * Independent Segmentation and Reassembly blocks for receive and transmit (RX_SAR and TX_SAR) support CBR (Constant Bit Rate) transport of half- or full-duplex TDM channels. Compatible with "Structured Data Transfer (SDT) services" as per ANSI T1.630 standard for 1 to 122 TDM channels per VC. Compatible with ITU-T I.363.1 "circuit transport" of 8 kHz structured data using Structured Data Transfer (SDT) for 1 to 96 TDM channels per VC (using buffer-fill level monitoring). Compatible with ITU-T I.363.1 "voiceband signal transport." Compatible with AF-VTOA-0078.000 "N x 64 Basic Service" (non-CAS) Circuit Emulation (using buffer-level monitoring, rather than lost cell insertion). Compatible with AF-VTOA-0078.000 for SDT of partially-filled AAL1 cells with N-channel structures (where N does not exceed the value of the partial-fill). AAL1 SAR-PDU Header processing (AAL1 Sequence Number checking). Supports up to 1024 bidirectional VCs (virtual circuits) simultaneously. Supports up to 1024 transmit TDM channels and 1024 receive TDM channels simultaneously. Supports CBR-AAL0 (48 byte cell payload). Supports CBR-AAL5 as per AF-VTOA-0083.000, also supports Nx64 trunking over CBR-AAL5. 15 MT90500 * * * * * * * * Supports partially-filled cells (AAL1, CBR-AAL5, and CBR-AAL0). User-defined, per-VC, Cell Delay Variation tolerance: 8 to 128 ms buffer size (up to 64 ms CDV). Handles TDM channels at 64 kbps granularity. Each individual VC can be composed of N x 64 kbps wideband channels (N = 1, 2, ..., 122). Flexible aggregation capability (N x 64 kbps) maintains frame integrity, while allowing any combination of 64 kbps channels (DS0 grooming). Supports "multi-casting" of one TDM DS0 input channel to multiple Transmit ATM VCs, and of one Receive ATM DS0 to multiple TDM outputs. A VC can contain any combination of TDM channels from any combination of TDM streams (Nx64) and maintain frame integrity for those channels. Supports several 8 kHz synchronisation operations: synchronized to external 8 kHz reference, synchronized to network clock, and synchronized to timing derived from an ATM VC (including ITU-T I.363.1 Adaptive and SRTS clock recovery mechanisms). 2.4 External Memory Interface * * To implement SAR functions and buffers, the MT90500 device uses external Synchronous SRAM. External Synchronous SRAM size is chosen by user, and depends on Cell Delay Variation (CDV) and the number of simultaneous 64 kbps channels handled. The amount of Synchronous SRAM is scalable to suit the application, and may range from 128 Kbytes to 2,048 Kbytes. 2.5 UTOPIA Interface and Multiplexer * * * * * * * UTOPIA Level 1 compatible 8-bit bus, running at up to 25 Mbyte/s, for connection to PHY devices with data throughput of up to 155 Mbps. Transmit multiplexer mixes cells from TX_SAR and Secondary UTOPIA port, supporting another MT90500, and/or an external SAR device (e.g. AAL5) connected to a single PHY device. Programmable multiplexer priority gives internally generated AAL1 cells equal, or higher, priority than cells coming from Secondary UTOPIA port. Supports non-CBR data cells and OAM cells destined for microprocessor with Receive and Transmit Data Cell FIFOs. Flexible receive cell handling: AAL1 (as well as CBR-AAL0 and CBR-AAL5) cells are sent to the TDM port; data cells (non-CBR data and OAM cells) are sent to the Receive Data Cell FIFO; cells with unrecognized VCs may be queued or ignored. Cell reception based on look-up-table allows flexible VC assignment for CBR VCs (allows noncontiguous VC assignment). Programmable VPI/VCI Match and Mask filtering reduces unnecessary look-up-table accesses. 2.6 Microprocessor Interface * * * * 16-bit microprocessor port, configurable to Motorola or Intel timing. Programmable interrupts for control and statistics. Allows access to internal registers for initialization, control, and statistics. Allows access to external SSRAM for initialization, control, and observation. 2.7 Miscellaneous * * * Master clock rate up to 60 MHz. Dual rails (3.3V for power minimization, 5V for standard I/O). Loopback function provided at the TDM interface. 16 MT90500 * * 2.8 IEEE 1149 (JTAG) Boundary-Scan Test Access Port for testing board-level interconnect. Packaging: 240-pin PQFP. Interrupts The MT90500 provides a wide variety of interrupt source bits, allowing for easy monitoring of MT90500 operation. All interrupt source bits, including the module level interrupt bits, have an associated mask bit which enables or disables assertion of the interrupt pin. This enables the user to tailor the interrupt pin activity to the application. Interrupt source bits are set regardless of the state of the associated mask bit, so even source bits which are disabled from causing an interrupt pin assertion may be polled by the CPU by reading the appropriate register. 2.8.1 Module Level Interrupts The following interrupt bits are used to indicate which MT90500 circuit module is the source of the interrupt. They are set when one or more interrupt source bits in the particular circuit module is set. The CPU can find the source of an interrupt by reading the register containing these bits and then reading the indicated module's interrupt register. * * * * * 2.8.2 TX_SAR Module Interrupt RX_SAR Module Interrupt UTOPIA Module Interrupt TDM Module Interrupt Timing (TDM Clock Generation) Module Interrupt TX_SAR Interrupts * * Transmit Non-CBR Data Cell FIFO Overrun Interrupt Scheduler error (Indicates that the TX_SAR has too heavy a work load.) 2.8.3 RX_SAR Interrupts * * * * * * * * * * AAL1-byte Parity Error Interrupt AAL1-byte CRC Error Interrupt AAL1-byte Sequence Number Error Interrupt Pointer-byte Parity Error Interrupt Pointer-byte Out of Range Error Interrupt Underrun Error Interrupt Overrun Error Interrupt Miscellaneous Counter Rollover Interrupt Underrun Counter Rollover Interrupt Overrun Counter Rollover Interrupt 2.8.4 UTOPIA Interrupts * * * Receive Non-CBR Data Cell FIFO Overrun Interrupt RX UTOPIA Module Internal FIFO Overrun Interrupt Receive Non-CBR Data Cell FIFO Receive Cell Interrupt 2.8.5 TDM Interrupts * * * Clock Absent Interrupt Clock Fail Interrupt TDM Out of Bandwidth Interrupt 17 MT90500 * * 2.8.6 TDM Read Underrun Error Interrupt TDM Read Underrun Counter Rollover Interrupt Timing Module Interrupts * * * * * * * 8 kHz Reference Failure Interrupt SRTS TX Underrun Interrupt SRTS TX Overrun Interrupt SRTS RX Underrun Interrupt SRTS RX Overrun Interrupt Adaptive Clock Loss of Timing Reference Cell Interrupt Adaptive Clock Loss of Synchronization Interrupt 2.9 Statistics The MT90500 provides a number of statistics to allow monitoring of the MT90500. These statistics generally parallel the operation of some of the interrupt source bits. The counters (except the Timing Recovery counters) also set rollover interrupt source bits when they reach their terminal counts and return to zero. 2.9.1 RX_SAR Statistics * Miscellaneous Event Counter: This 16-bit register's value is incremented each time a (maskselected) miscellaneous error occurs. * * * * * * * * * * 2.9.2 AAL1-byte Parity Error AAL1-byte CRC Error AAL1 Sequence Number Error Pointer-byte Parity Error Pointer-byte Out of Range Error Miscellaneous Event ID Register: The address of the RX Control Structure that caused the last miscellaneous error. Underrun Count: This 16-bit register's value is incremented each time a CBR Receive Underrun occurs. Underrun ID Number: The address of the RX Control Structure that caused the last underrun error. Overrun Count: This 16-bit register is incremented each time a CBR Receive Overrun occurs. Overrun ID Number: The address of the RX Control Structure that caused the last overrun error. TDM Statistics * * TDM Read Underrun Time Slot Stream. Contains the time slot and stream on which the last TDM read underrun was detected. TDM Read Underrun Counter. Each time a TDM read underrun occurs, this register's value is incremented. 2.9.3 Timing Recovery Statistics * * Event Counter: Counts the reception of timing reference cells or 8 kHz markers. CLKx1 Counter: 24-bit counter which keeps a running count of TDM byte-periods. 18 MT90500 3. Pin Descriptions I/O types are: Output (O), Input (I), Bidirectional (I/O), Power (PWR), or Ground (GND). Input pad types are: TTL, CMOS, Differential, or Schmitt. The notations "PU" and "PD" are used, respectively, to indicate that a pad has an internal pullup or pulldown resistor. TTL (5V) inputs are pulled-up to the 5V rail, CMOS (3.3V) inputs are pulled-up to the 3.3V rail. These weak internal resistors should not be relied upon for fast data transitions. The 3.3V CMOS inputs have a switching threshold of 1.6V, and tolerate input levels of up to 5V; therefore they are 5V TTL compatible (with the exception of the TRISTATE pin, which is not 5V tolerant). Output pad types are generally described by voltage and current capability. Output types used are: 3.3V, 4mA; 5V, 4mA; 5V, 12mA; and open-drain. A notation of "SR" indicates that the pad is slew-rate limited. 3.3V CMOS outputs will satisfy 5V TTL input thresholds at the rated current. Table 1 - Primary UTOPIA Bus Pins Pin # 49, 48, 47, 46, 45, 44, 39, 38 52 51 53 Pin Name PTXDATA[7:0] PTXSOC PTXEN PTXCLAV I/O O O O I Type 5V, 4mA 5V, 4mA 5V, 4mA TTL PU Description Primary UTOPIA transmit data bus. Byte-wide data driven from MT90500 to PHY device. Bit 7 is the MSB. Primary UTOPIA transmit start of cell signal. Asserted by the MT90500 when PTXDATA[7:0] contains the first valid byte of the cell. Primary UTOPIA transmit data enable. Active LOW signal asserted by the MT90500 during cycles when PTXDATA[7:0] contains valid cell data. Primary UTOPIA transmit cell available indication signal. For cell level flow control, PTXCLAV is asserted by the PHY to indicate to the MT90500 that the PHY can accept the transfer of a complete cell. Primary UTOPIA transmit clock. Data transfer & synchronization clock provided by the MT90500 to the PHY for transmitting data on PTXDATA[7:0]; software configurable (in Main Control Register at 0000h) to run at up to 25 MHz. Note that this pin should be configured as an output for exact compliance with UTOPIA Level 1, V2.01. Primary UTOPIA transmit parity. This signal is the odd parity bit over PTXDATA[7:0]. Primary UTOPIA receive data bus. Byte-wide data driven from the PHY to the MT90500. PRXDATA[7] is the MSB. Primary UTOPIA receive start of cell signal. Asserted by the PHY when PRXDATA[7:0] contains the first valid byte of a cell. Primary UTOPIA bus data enable. Active LOW signal normally asserted by the secondary SAR to indicate that PRXDATA[7:0], PRXSOC, and PRXCLAV will be sampled at the end of the next clock cycle. If no secondary SAR is used, ground this pin at the MT90500 and PHY devices. Note that the UTOPIA standard permits this signal to be permanently asserted (see UTOPIA Level 1, V2.01, footnote 6). Primary UTOPIA receive cell available indication signal. For cell level flow control, PRXCLAV is asserted by the PHY to indicate it has a complete cell available for transfer to the RX UTOPIA port. Primary UTOPIA bus receive clock. This clock, which can run at up to 25 MHz, is provided by the secondary SAR device. If no secondary SAR is used, connect to PTXCLK (this will provide exact compliance with the UTOPIA Level 1, V2.01 specification). 82 PTXCLK I/O TTL PU / 5V, 4mA SR 50 57, 58, 59, 62, 63, 64, 65, 66 56 55 PTXPAR PRXDATA[7:0] PRXSOC PRXEN O I I I 5V, 4mA TTL PU TTL PU TTL PU 54 PRXCLAV I TTL PU 79 PRXCLK I TTL PU Refer to Figure 63 on page 139 for implementation details regarding the interface between two MT90500s and an external AAL5 SAR. 19 MT90500 Table 2 - Secondary UTOPIA Bus Pins Pin # 70, 71, 72, 73, 74, 75, 76, 77 69 68 67 Pin Name STXDATA[7:0] STXSOC STXEN STXCLAV I/O I I I O Type TTL PU TTL PU TTL PU 5V, 4mA Description Secondary UTOPIA transmit data bus. Byte-wide data driven from the external SAR to the MT90500. Bit 7 is the MSB. Secondary UTOPIA transmit start of cell signal. Asserted by the external SAR device when STXDATA[7:0] contains the first valid byte of the cell. Secondary UTOPIA transmit data enable. Active LOW signal asserted by the external SAR during cycles when STXDATA[7:0] contains valid cell data. Secondary UTOPIA transmit cell available indication signal. For cell level flow control, STXCLAV is asserted by the MT90500 to indicate to the external SAR that the MT90500 can accept the transfer of a complete cell. Secondary UTOPIA transmit clock, which can run at up to 25 MHz. Data transfer & synchronization clock provided by the external SAR to the MT90500 for transmitting data over STXDATA[7:0]. 85 STXCLK I TTL PU Note: MT90500 Secondary UTOPIA port emulates a PHY device for connection to an external SAR (ATM-layer device). Refer to Figure 63 on page 139 for implementation details regarding the interface between the MT90500 and an external AAL5 SAR. Table 3 - Microprocessor Bus Interface Pins Pin # 37 36 203 237 239 238 Pin Name Intel/Motorola IC CS WR/R\W RD/DS RDY/DTACK I/O I I I I I O Type TTL PU TTL PU TTL PU TTL PU TTL PU 5V, 4mA Description Intel interface (1) / Motorola interface (0) Internal connection (must be HIGH). Active LOW chip select signal. Active LOW Write Strobe (Intel) / Read-Write (Motorola). Active LOW Read Strobe (Intel) / Active LOW Data Strobe (Motorola). Ready (Intel) / Data Transfer Acknowledge (Motorola). Acts as active LOW pseudo-open-drain in Motorola mode (DTACK, see Figure 53 on page 126). Acts as normal output in Intel mode, high impedance when CS is HIGH (RDY). Active LOW interrupt line. CPU data bus. 84 223, 222, 219, 218, 217, 216, 215, 214, 212, 211, 210, 209, 208, 206, 205, 204 184 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 198, 199, 202 INT D[15:0] O I/O 5V, 4mA SR (Open-Drain) TTL PU / 5V, 4mA SR AEM A[15:1] I I TTL PU TTL PU Access External Memory - CPU accesses external memory when HIGH (internal memory and registers when LOW). CPU Address lines A15-A1. All microprocessor accesses to the device are word-wide, but addresses in this document are given as byte-addresses. The virtual A[0] bit selects between high and low bytes in a word. Note: MT90500 TTL inputs are pulled up to the 5 Volt rail. See Table 76 on page 112. 20 MT90500 Table 4 - External Memory Interface Pins Pin # 98 147 Pin Name MEMCLK MEM_CS0L I/O O O Type 3.3V, 4mA 3.3V, 4mA Description Memory Clock. Internally connected to MCLK. Active LOW memory chip select signal. This chip select is used in all memory modes. When there are two chips per bank, MEM_CS0L is associated with MEM_DAT[15:0] of Bank 0. Active LOW memory chip select signal. This chip select is used when there are two 16-bit memory chips per bank. MEM_CS0H is associated with MEM_DAT[31:16] of Bank 0. Active LOW memory chip select signal. This chip select is used when there are two banks and two chips per bank. MEM_CS1L is associated with MEM_DAT[15:0] of Bank 1. Active LOW memory chip select signal. This chip select is used when there are two banks and two chips per bank. MEM_CS1H is associated with MEM_DAT[31:16] of Bank 1. Active LOW byte-write enables. MEM_WR[3] is associated with MEM_DAT[31:24]; MEM_WR[2] is associated with MEM_DAT[23:16]; MEM_WR[1] is associated with MEM_DAT[15:8]; MEM_WR[0] is associated with MEM_DAT[7:0]. Active LOW output enable. Memory address lines. 176 MEM_CS0H O 3.3V, 4mA 148 MEM_CS1L O 3.3V, 4mA 177 MEM_CS1H O 3.3V, 4mA 178, 179, 149, 150 MEM_WR[3:0] O 3.3V, 4mA 180 123, 122, 121, 118, 117, 116, 115, 103, 102, 99, 146, 144, 130, 128, 127, 126, 125, 124 166, 167, 168, 170, 171, 173, 174, 175, 153, 154, 155, 156, 158, 159, 162, 164, 133, 134, 135, 136, 137, 138, 142, 143, 105, 106, 107, 108, 109, 112, 113, 114 165, 152, 131, 104 MEM_OE MEM_ADD[17:0] O O 3.3V, 4mA 3.3V, 4mA MEM_DAT[31:0] I/O 3.3V CMOS Memory data lines. MEM_DAT[31:24] represent the upper byte; PU / 3.3V 4mA MEM_DAT[23:16] represent the upper-middle byte; MEM_DAT[15:8] represent the lower-middle byte; MEM_DAT[7:0] represent the lower byte. MEM_PAR[3:0] I/O 3.3V CMOS Memory parity lines. MEM_PAR[3:0] are the optional "parity" bits that allow PU / 3.3V 4mA TDM Read Underrun detection. MEM_PAR[3] is related to MEM_DAT[31:24], MEM_PAR[2] is related to MEM_DAT[23:16], MEM_PAR[1] is related to MEM_DAT[15:8], and MEM_PAR[0] is related to MEM_DAT[7:0]. When unused, these pins must be pulled up via external resistors. Note: MT90500 3.3 V CMOS inputs are pulled up to the 3.3 Volt rail. See Table 76 on page 112. 21 MT90500 Table 5 - Master Clock, Test, and Power Pins Pin # 87 Pin Name MCLK I/O I Type TTL PU Description Master Clock. This signal drives the internal logic (including the RX_SAR and the TX_SAR) and the external memory (through MEMCLK). 60 MHz for most applications. MCLK should be more than 5 times CLKx1, and should be more than 3 times FNXI. Chip reset signal (active LOW). Note that the MT90500 is synchronously reset, and that MCLK should be applied during reset. To asynchronously tristate outputs, assert the TRISTATE pin. The TRST pin (JTAG reset) should also be asserted LOW during chip reset. Reset should last at least 2 s when MCLK is 60 MHz. Also see SRES bit in register 0000h. 78 RESET I 5V TTL Schmitt PU 97 93 95 96 94 TMS TCK TDI TDO TRST I I I O I 3.3V CMOS JTAG Test Mode Select signal. PU 3.3V CMOS JTAG Test Clock. PU 3.3V CMOS JTAG Test Data In. PU 3.3V, 4mA SR JTAG Test Data Out. Note: TDO is tristated by TRISTATE pin. 3.3V CMOS JTAG Test Reset input (active LOW). Should be asserted LOW on power-up PD and during reset. Must be HIGH for JTAG boundary-scan operation. Note: This pin has an internal pull-down. Ground for I/O logic. 1, 7, 16, 29, 43, 61, 86, 91, 110, 119, 129, 139, 151, 163, 172, 182, 197, 213, 229 100, 141, 161 20, 40, 80, 201, 221 92, 111, 120, 132, 145, 157, 169, 181 2, 13, 24, 42, 60, 88, 183, 207, 225, 240 101, 140, 160 21, 41, 81, 200, 220 89 90 IO_VSS GND CORE_VSS RING_VSS IO_VDD_3V GND GND PWR Ground for core logic. Ground for core logic. Power for I/O logic (3.3 V). IO_VDD_5V PWR Power for I/O logic (5 V). CORE_VDD_3V RING_VDD_3V IC TRISTATE PWR PWR I I Power for core logic (3.3 V). Power for core logic (3.3 V). IC TEST, must be grounded. 3.3V CMOS Output Tristate Control. Asynchronously tristates all output pins when LOW. PU Can be asserted LOW on power-up and during reset. Pull up to 3.3V for 3.3V ONLY normal operation. NOT 5V TOLERANT. 22 MT90500 Table 6 - TDM Port Pins Pin # 25, 23, 22, 19, 18, 17, 15, 14, 12, 11, 10, 9, 8, 6, 5, 4 230 Pin Name ST[15:0] I/O I/O Type TTL PU / 5V, 12mA SR Description TDM data streams. Used to pass PCM (voice) bytes or other data types. In order to enable any of these pins as outputs, the GENOE bit in the TDM Interface Control Register (6000h) must be set, as well as the appropriate channel bits in the Output Enable Registers. Differential clock signal input (+) running at twice the serial TDM data stream frequency. This pin is used only in differential clock mode (H-MVIP) and should be tied HIGH when not in use. For normal (non-differential) clock mode input, use CLKx2/CLX2PO pin. Differential clock signal input (-) running at twice the serial TDM data stream frequency. This pin is used only in differential clock mode (H-MVIP) and should be grounded when not in use. Clockx1. This signal represents the CLKx2 signal divided by 2. Frame sync. Bidirectional 8 kHz reference to/from main TDM Bus. Internal connection (must be HIGH). CORSIGA I/O when not used by the TDM bus. Clock fail on SCSA bus. CORSIGB I/O when not used by the TDM bus. Message Channel (I/O) on the SCSA bus. SRTS FNX Network Clock Input - this input line is required when SRTS clock recovery mode is used. Note: When used for clock recovery, this clock must be < MCLK / 3. CORSIGC I/O when not used by the TDM bus. Message Channel Transmit (input) toward SCSA bus from HDLC controller. This signal represents SRTS ENA output when SRTS clock recovery mode is selected. CORSIGD I/O when not used by the TDM bus. Message Channel Receive (output) from SCSA bus toward HDLC controller. This signal represents SRTS DATA output serial line when SRTS clock recovery mode is selected. CORSIGE I/O when not used by the TDM bus. Message Channel HDLC controller clock (output) from the SCSA bus. An 8 kHz clock input that can be used as reference in the generation of the REF8KCLK or SEC8K lines. Secondary alternate 8 kHz clock. Compatible with MVIP and H-MVIP modes. An 8 kHz clock generated internally. This signal is generated from one of several internal sources which are programmed by the user. This output can provide a reference clock to an external PLL to generate the 16.384 / 32.768 MHz required for the operation of the IC in master mode. 16.384 / 32.768 MHz TDM clock reference from external PLL. Active HIGH external PLL freerun indication. Local TDM Bus Clockx2. Local TDM Bus Clockx1. Local TDM Bus Frame Sync. Local TDM Bus Serial Data Out Stream. Local TDM Bus Serial Data In Stream. CLKx2 Input/Output / CLKx2 Positive Output. Normal (non-differential) CLKx2 input in TDM Clock Slave mode. CLKx2 output (differential and nondifferential) in TDM Clock Master mode. CLKx2 Negative Output. Differential negative output clock. (Inverse of CLKx2PO). Used in TDM Clock Master, differential clock mode (H-MVIP); active whenever MT90500 is TDM Clock Master. (Leave unconnected if non-differential clock desired.) 23 CLKx2PI I Diff + 227 CLKx2NI I Diff - 233 232 30 32 235 CLKx1 FSYNC IC CORSIGA / CLKFAIL CORSIGB / MC / FNXI I/O I/O I I/O I/O TTL PU / 5V, 12mA SR TTL PU / 5V, 12mA SR TTL PU TTL PU / 5V, 12mA SR TTL PU / 5V, 12mA SR 33 CORSIGC / MCTX / SRTSENA CORSIGD / MCRX / SRTSDATA CORSIGE / MCCLK EX_8KA SEC8K REF8KCLK I/O TTL PU / 5V, 4mA SR TTL PU / 5V, 4mA SR 34 I/O 35 83 234 226 I/O I I/O O TTL PU / 5V, 4mA SR TTL PU TTL PU / 5V, 12mA 5V, 12mA SR 224 31 236 3 28 26 27 231 PLLCLK FREERUN LOCx2 LOCx1 LSYNC LOCSTo LOCSTi CLKx2/ CLKx2PO CLKx2NO I O O O O O I I/O TTL PU 5V, 12mA SR 5V, 4mA SR 5V, 4mA SR 5V, 4mA SR 5V, 4mA SR TTL PU TTL PU / 5V, 12mA 5V, 12mA 228 O MT90500 Table 7 - Reset State of I/O and Output Pins Pin Name PTXDATA[7:0] PTXPAR PTXCLK PTXEN PTXSOC STXCLAV MEMCLK MEM_CS[1:0][H:L] MEM_WR[3:0] MEM_OE MEM_ADD[17:0] MEM_DAT[31:0] MEM_PAR[3:0] RDY/DTACK INT D[15:0] TDO ST[15:0] CLKx1 FSYNC CORSIGA/ CLKFAIL CORSIGB / MC / FNXI CORSIGC / MCTX / SRTSENA CORSIGD / MCRX / SRTSDATA CORSIGE / MCCLK SEC8K REF8KCLK I/O O O I/O O O O O O O O O I/O I/O O O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O O Reset State Active during and after reset. Active during and after reset. High-impedance Active during and after reset. Active during and after reset. Active during and after reset. Continues to drive at MCLK rate during reset. Active during and after reset. Active during and after reset. Active HIGH during reset. Active during and after reset. High-impedance High-impedance Active during and after reset. Tristated when CS is HIGH. High-impedance High-impedance Determined by TRST and / or TAP controller state High-impedance Input Input Input Input Input Input Input Input Active during and after reset. N/A N/A The PTXCLK_SEL bits in the Main Control Register (0000h) are LOW after reset; PTXCLK is tristated and an input. N/A N/A N/A N/A N/A N/A RESET LOW forces this pin HIGH. After reset, this pin goes LOW. N/A N/A N/A In Motorola mode, pin drives HIGH during reset. In Intel mode, drives LOW during reset. The interrupt enable bits in the Main Control Register at 0000h are reset to zero; interrupts are masked after reset. N/A N/A The GENOE bit in the TDM Interface Control Register (6000h) is LOW after reset; these TDM data pins are tristated and in loopback mode. The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to `0'; the MT90500 is TDM Slave, and CLKx1 is input from the TDM bus. The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to `0'; the MT90500 is TDM Slave and FSYNC is input from the TDM bus. The TDM I/O Register at 6004h resets to all zeroes; all CORSIGxCNF are set to "00" and all CORSIGx pins are configured as inputs. See CORSIGA. See CORSIGA. See CORSIGA. See CORSIGA. The SEC8KEN bit in the Master Clock Generation Control Register (6090h) resets to `0'; SEC8K is an input. Due to the reset values of the Master Clock Generation Control Register (6090h) and the Master Clock / CLKx2 Division Factor (6092h), REF8KCLK is initially equal to MCLK / 8194. The FREERUN bits in the Master Clock Generation Control Register at 6090h are "00" after reset; the FREERUN pin is reset to active HIGH. N/A N/A Additional Control Information FREERUN LOCx2 LOCx1 O O O Active HIGH during and after reset. Active during and after reset. Active during and after reset. 24 MT90500 Table 7 - Reset State of I/O and Output Pins Pin Name LSYNC LOCSTo CLKx2/CLKx2PO CLKx2NO I/O O O I/O O Reset State Active during and after reset. Active during and after reset. Input High-impedance N/A N/A The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to `0'; the MT90500 is TDM Slave and CLKx2 is input from the TDM bus. The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to `0'; the MT90500 is TDM Slave and therefore no clock signals are driven from the MT90500. Additional Control Information Note: All pins are placed in high-impedance by asserting the TRISTATE pin. Table 8 - Pinout Summary Type Primary UTOPIA Secondary UTOPIA External Memory Interface Microprocessor Interface Miscellaneous TDM Interface Power Ground Total 187 + 26 + 27 = 240 59 50 78 26 21 8 6 Input 13 11 Output 11 1 28 2 1 7 25 26 27 27 36 16 I/O 1 Power Ground 25 MT90500 MEM_OE MEM_WR2 MEM_WR3 MEM_CS1H MEM_CS0H MEM_DAT24 MEM_DAT25 MEM_DAT26 IO_VSS MEM_DAT27 MEM_DAT28 IO_VDD_3V MEM_DAT29 MEM_DAT30 MEM_DAT31 MEM_PAR3 MEM_DAT16 IO_VSS MEM_DAT17 CORE_VSS CORE_VDD_3V MEM_DAT18 MEM_DAT19 IO_VDD_3V MEM_DAT20 MEM_DAT21 MEM_DAT22 MEM_DAT23 MEM_PAR2 IO_VSS IO_VDD_3V IO_VSS IO_VDD_5V AEM A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 IO_VSS A3 A2 RING_VDD_3V RING_VSS A1 CS D0 D1 D2 IO_VDD_5V D3 D4 D5 D6 D7 IO_VSS D8 D9 D10 D11 D12 D13 RING_VDD_3V RING_VSS D14 D15 PLLCLK IO_VDD_5V REF8KCLK CLKx2NI CLKx2NO IO_VSS CLKx2PI CLKx2/CLKx2PO FSYNC CLKx1 SEC8K CORSIGB LOCx2 WR/R\W RDY/DTACK RD/DS IO_VDD_5V 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 240 PIN PQFP Figure 2. Pin Connections 26 IO_VSS IO_VDD_5V LOCx1 ST0 ST1 ST2 IO_VSS ST3 ST4 ST5 ST6 ST7 IO_VDD_5V ST8 ST9 IO_VSS ST10 ST11 ST12 RING_VSS RING_VDD_3V ST13 ST14 IO_VDD_5V ST15 LOCSTo LOCSTi LSYNC IO_VSS IC MT90500 MEM_WR0 MEM_WR1 MEM_CS1L MEM_CS0L MEM_ADD7 IO_VDD_3V MEM_ADD6 MEM_DAT8 MEM_DAT9 CORE_VSS CORE_VDD_3V IO_VSS MEM_DAT10 MEM_DAT11 MEM_DAT12 MEM_DAT13 MEM_DAT14 MEM_DAT15 IO_VDD_3V MEM_PAR1 MEM_ADD5 IO_VSS MEM_ADD4 MEM_ADD3 MEM_ADD2 MEM_ADD1 MEM_ADD0 MEM_ADD17 MEM_ADD16 MEM_ADD15 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 240 PIN PQFP 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 IO_VDD_3V IO_VSS MEM_ADD14 MEM_ADD13 MEM_ADD12 MEM_ADD11 MEM_DAT0 MEM_DAT1 MEM_DAT2 IO_VDD_3V IO_VSS MEM_DAT3 MEM_DAT4 MEM_DAT5 MEM_DAT6 MEM_DAT7 MEMPAR0 MEM_ADD10 MEM_ADD9 CORE_VDD_3V CORE_VSS MEM_ADD8 MEMCLK TMS TDO TDI TRST TCK IO_VDD_3V IO_VSS TRISTATE IC IO_VDD_5V MCLK IO_VSS STXCLK INT EX_8KA PTXCLK RING_VDD_3V RING_VSS PRXCLK RESET STXDATA0 STXDATA1 STXDATA2 STXDATA3 STXDATA4 STXDATA5 STXDATA6 STXDATA7 STXSOC STXEN STXCLAV PRXDATA0 PRXDATA1 PRXDATA2 PRXDATA3 PRXDATA4 IO_VSS 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 FREERUN CORSIGA CORSIGC CORSIGD CORSIGE IC INTEL/MOTOROLA PTXDATA0 PTXDATA1 RING_VSS RING_VDD_3V IO_VDD_5V IO_VSS PTXDATA2 PTXDATA3 PTXDATA4 PTXDATA5 PTXDATA6 PTXDATA7 PTXPAR PTXEN PTXSOC PTXCLAV PRXCLAV PRXEN PRXSOC PRXDATA7 PRXDATA6 PRXDATA5 IO_VDD_5V 27 MT90500 4. Functional Description As shown in Figure 1, "MT90500 Block Diagram," on page 12, the MT90500 device consists of the following major components: TDM Module, External Memory Controller, TX_SAR, RX_SAR, UTOPIA Module, Clock Recovery, Microprocessor Interface, and Test Interface. This section describes each module in detail. 4.1 TDM Module This circuit module is the interface to the Time Division Multiplexed (TDM) buses, which carry N x 64kbps data. The TDM module interfaces are: * 16 bidirectional TDM data streams on pins ST[15:0]; these pins can be configured through software registers to support various bus formats (ST-BUS, MVIP, H-MVIP, SCSA, or IDL) and data rates of 2.048 Mbps, 4.096 Mbps, or 8.192 Mbps; (For the selection of the bus type, see TDM Bus Type Register at address 6010h in Section 5.) the TDM bus clocks (CLKx2, CLKx1) and frame synchronization signal (FSYNC); the TDM bus ancillary signals such as SEC8K (MVIP) and CLKFAIL (SCSA); a local TDM bus (LOCx2, LOCx1, LSYNC, LOCSTi, and LOCSTo); the format of the bus, which runs at 2.048 Mbps (LOCx2 = 4.096 Mbps), is user-programmable via software (see Local Bus Type Register at address 6020h). * * * The TDM module moves TDM data from the TDM serial inputs to the external memory (where it is read by the TX_SAR) in the transmit direction, and from the external memory (where it was written by the RX_SAR) to the TDM outputs in the receive direction. This is done with the aid of an internal TDM frame buffer, which is used to buffer 4 frames of each TDM channel in both directions; i.e. four frames in the receive direction (ATM to TDM), and four frames in the transmit direction (TDM to ATM). The TDM module can be divided into four main processes: * * * * TDM Clock Logic, which controls all the operations related to clock generation and clock signal monitoring on the TDM bus; TDM Interface Operation, which controls the input and output of the serial TDM data; TDM Data to External Memory Process, which transfers TDM input data into Transmit Circular Buffers in the external memory; External Memory to TDM Data Output Process, which transfers TDM output data from Receive Circular Buffers in the external memory to the TDM output bus. Each of these processes are described in detail below. 4.1.1 TDM Clock Logic The TDM Clock Logic controls all of the operations related to clock generation and clock signal monitoring on the TDM bus. The block diagram of the TDM Clock Logic is shown in Figure 3. This module consists of several blocks, including: selection logic for an 8 kHz reference for the external PLL (REF8KCLK), the main TDM bus clock generation logic, the local TDM bus clock generation logic, the clock drivers & clock selection for the SEC8K signal, and the clock failure detection logic. 4.1.1.1 TDM Timing Modes The MT90500 supports 4 major TDM timing modes. There are also a number of TDM timing features which are independent of the TDM timing mode being used: * The SEC8K pin (MVIP compatibility) can be programmed as either output or input. The SEC8KEN bit in the MCGCR Register (6090h) enables the SEC8K pin driver. If the SEC8K pin is enabled as an output, the SEC8KSEL bit in the same register selects the source for this signal (the EX_8KA input, or the internal 8 kHz FS_INT signal which is derived from CLK16). 28 MT90500 Main TDM Bus PHLEN CLKx1 Main TDM Bus Timing and Clock Generation Logic FS_INT Local TDM Bus Clock Generation Logic LOCx1 LSYNC CLK16 (16.384 MHz) Divide by 1,2,4,or 8 DIV1...8 BEPLL 1 0 FREERUN PLLCLK MT9041 or other PLL External PLL (Optional) FSYNC Master/Slave FSYNC DIVCLK_SRC MCLK SEC8KEN SEC8K 1 0 FS_INT EX_8KA_INT SEC8KSEL 0 Square SEC8K_SQ 1 ATM Cells Internal CPU Bus Adaptive Clock Recovery SRTS Clock Recovery FNXI SRTS Square 10 REFSEL<1:0> 0 1 REF8KCLK Detection Logic Divide by 2 to 16384 RXVCLK SEC8K_INT EX_8KA_INT 0 1 2 3 REF8KCLK EX_8KA_SQ CLKx2 CLKx1 FSYNC EX_8KA All control bits shown are in Master Clock Generation Control Register (6090h). Clock Absent Detection Logic MT90500 External CPU Bus Figure 3 - TDM Clock Selection and Generation Logic * The CLKx2 signal can be selected as single-ended or differential. (Differential CLKx2 allows compatibility with the H-MVIP bus.) In TDM Timing Slave, the CLKx2 signal can be input on the CLKx2 pin, or the differential CLKx2PI and CLKx2NI pins. This selection is made with CLKTYPE in the TDM Bus Type Register at address 6010h. In TDM Timing Master, the CLKx2 signal is output on the CLKx2/CLKx2PO pin, and an inverted clock is available on the CLKx2NO pin. The MT90500 supports the following TDM timing modes: * TDM Timing Bus Slave - CLKx2 Reference (CLKMASTER = `0' in TDM Bus Type Register at 6010h) In this mode, the MT90500 is configured as a TDM Timing Slave and all internal TDM timing is synchronized to the TDM clock inputs: CLKx2, CLKx1, and FSYNC. The following sub-modes are also selectable: * * The CLKx1 can be an input at the CLKx1 pin, or it can be derived internally from CLKx2. This is controlled by TCLKSYN (address 6010h). If the CLKx1 pin is not used as an input in TDM Slave mode, it remains high-impedance. TDM Timing Slave operation takes its 8 kHz framing from the FSYNC input pin, which would usually be driven by the TDM bus. To support other implementations, the REF8KCLK output remains active in TDM Slave mode. An 8 kHz reference output can be made available at REF8KCLK, selectable from the EX_8KA input, the SEC8K pin, or one of the internal dividers. In addition, the FREERUN output can be used to monitor the presence of REF8KCLK. Local TDM Bus CLKx2 LOCx2 29 MT90500 * TDM Timing Bus Master - Freerun (CLKMASTER = `1' in TDM Bus Type Register at 6010h) In this mode, the MT90500 is configured as the TDM Timing Master and the MT90500 drives the three TDM bus clocks: CLKx2, CLKx1, and FSYNC. The MT90500 clock generator block uses either the MCLK input or the PLLCLK input to generate all of the required clocks. Typically in this mode MCLK or PLLCLK is connected to an oscillator, and no other synchronization source is used. Several selections must be made: * * The selection of MCLK or PLLCLK is determined by the BEPLL bits in the Master Clock Generation Control Register at 6090h. * The selected clock is divided by 1, 2, 4, or 8 to obtain a 16.384 MHz clock, called CLK16. This division is controlled by the DIV1...8 bits at 6090h. TDM Timing Bus Master - 8 kHz Reference (CLKMASTER = `1' in TDM Bus Type Register at 6010h) In this mode, the MT90500 is configured as the TDM Timing Master and the MT90500 drives the three TDM bus clocks, synchronized to one of several possible 8 kHz references. Typically, in this mode, the PLLCLK input is driven by an external PLL (such as the Mitel MT9041), which is controlled by the REF8KCLK and FREERUN outputs. The following options are also selectable: * * One of four 8 kHz reference sources must be selected, using the REFSEL bits at 6090h. (See Figure 3 and Section 4.1.1.2 for further details.) * If the external PLL is controlled by the FREERUN output pin, the pin's operation must be specified by the FREERUN bits at 6090h. The CPU can force the FREERUN pin to either state, or allow the FREERUN pin to follow the REF8KCLK failure-detection bit (REFFAIL at 6082h). Bus Master-Alternate (CLKMASTER = `0', CLKALT = `1' in TDM Bus Type Register at 6010h) In this mode, the MT90500 is configured as a TDM Timing Slave, but stands ready to become the Timing Master, should the timing on the TDM bus fail. The switch is normally automatic (based on the CLKFAIL input), but can also performed by the CPU (for instance: by programming the chip into TDM Timing Master following a Clock Absent interrupt). The following options are also selectable: * * * * To make the switch from Alternate to Master automatic, several settings are required: CLKALT at 6010h is set HIGH, and the CORSIGA pin is configured as the CLKFAIL input (CORSIGACNF = "11" at 6004h). The Master-Alternate operates normally as a TDM Timing Slave, and has the same options as the TDM Timing Slave listed above. The Master-Alternate can be set up to switch to Master-Freerun operation, should the TDM bus clocks fail. The same options as listed above for Master-Freerun apply to this mode. The Master-Alternate can be set up to switch to Master-8 kHz Reference operation, should the TDM bus clocks fail. The same options as listed above for Master-8 kHz Reference apply to this mode. Additionally, REF8KCLK can be obtained from the TDM bus by dividing CLKx2. This allows the external PLL to be phase-locked to the TDM bus clocks. Note that in this case the FREERUN output should be set up to automatically place the external PLL in freerun should the TDM bus clocks fail. The internal 8 kHz (FS_INT) of the Master-Alternate can be phase-locked to the TDM bus FSYNC by setting PHLEN = `1' at 6090h. (This is only valid when the FSYNC type at 6010h is set to "00".) This will align the internal "stand-by" FSYNC, CLKx2, and CLKx1 to the TDM bus to within a clock cycle of the internal 16.384 MHz clock, allowing for minimal phase-shift should the Master-Alternate MT90500 take over the TDM bus clocks. * 4.1.1.2 REF8KCLK Selection Logic The REF8KCLK output pin of the MT90500 is intended to provide a clock reference to an optional external PLL. This signal would usually be an 8 kHz frame pulse, but other signals are possible. The external PLL (e.g. Mitel MT9041) can be used to multiply the REF8KCLK output to 16.384 MHz (or 32.768 MHz) and attenuate jitter. The 16.384 MHz can then be applied to the PLLCLK input pin to allow the MT90500 to generate the TDM 30 MT90500 clocks: CLKx2, CLKx1 and FSYNC. The source for the REF8KCLK signal is selected via the REFSEL bits at address 6090h. The four possible sources for REF8KCLK are: * * * * a clock input signal pin operating at 8 kHz (EX_8KA) a secondary 8 kHz reference from the TDM bus (SEC8K, compatible with MVIP/H-MVIP) a freerun mode clock, which is a divided-down version of CLKx2 or MCLK; selected by DIVCLK_SRC in register 6090h, and divided as specified in register 6092h RXVCLK, a more precisely divided-down version of MCLK from the Adaptive Clock Recovery block. The division is controlled by registers 60A8h and 60AAh. The REF8KCLK signal is made available on the output pin whether the MT90500 is programmed to be TDM Timing Master or Slave. Also included in the MT90500 is circuitry to convert the SEC8K signal and the EX_8KA signal into square waves. If the SEC8K_SQ control bit in register 6090h is set HIGH, internal logic will convert the SEC8K input signal into a square wave before passing it to the REF8KCLK selection multiplexer. The EX_8KA_SQ bit controls the squaring function for the EX_8KA signal. See the register 6090h. Mitel PLLs will typically work with either a pulse 8 kHz, or a square 8 kHz, but other PLL implementations may require a square 8 kHz reference input. 4.1.1.3 Main TDM Bus Timing and Clock Generation Logic When the MT90500 is in the TDM Timing Master mode, this logic generates the main TDM bus clocks (CLKx2, CLKx1, and FSYNC). This block receives CLK16 (a 16.384 MHz clock which is a divided-down version of either PLLCLK or MCLK, as set in register 6090h) and outputs the generated TDM bus clocks. By programming the appropriate software registers (i.e. TDMTYP at address 6010h), the generated signals can be 16.384MHz/ 8.192MHz/4.096MHz, 8.192MHz/4.096MHz/2.048MHz, and 8 kHz respectively. Additionally, the TDM Bus Clock Generation Logic generates a source signal to the SEC8K output line when the SEC8KEN register bit is enabled. When in TDM Timing Slave mode, or in Master-Alternate mode, this logic generates an internal stand-by 8 kHz signal (FS_INT), from the clock selected by BEPLL in register 6090h. This can be driven out on SEC8K if enabled by SEC8KEN. 4.1.1.4 TDM Clock Drivers If the MT90500 is the TDM Timing Master, this block enables the clock drivers for CLKx2, CLKx1, and FSYNC. If the MT90500 is in Slave mode, the drivers are disabled and CLKx2, CLKx1, and FSYNC are inputs to the MT90500. In Slave mode, the CLKx1 source can be separately selected between the CLKx1 input or internally provided CLKx2/2. These options are controlled by the TDM Bus Type Register at 6010h. 4.1.1.5 Clock Failure Detection There are three status bits related to the detection of clock failure: REFFAIL (6082h), and CABS and CFAIL (6002h). These bits will cause an interrupt if their respective enable bits are set (REFFAILIE at 6080h, and CABSIE and CFAILIE at 6000h) and the TDM_INTE bit is set at 0000h. The REFFAIL bit monitors the absence of the REF8KCLK signal. When this signal is absent, the clock detect logic can activate the FREERUN output signal which is used to place the external PLL in freerun mode. Once the REF8KCLK signal goes back to normal (due to the CPU changing the timing source), the CPU can disable the FREERUN output signal by clearing the REFFAIL bit in the Clock Module General Status Register at 6082h. With proper selection of the external PLL, this clock failure detection circuit can help to guarantee that the TDM clocks do not glitch when the REF8KCLK reference to the external PLL changes. The CABS bit indicates that one or more of the TDM bus clock signals (CLKx2, CLKx1, or FSYNC) are absent. This block uses MCLK to check for activity on the above signals. In the case of clock absence, the Clock Absent (CABS) bit in the TDM Interface Status (TIS) Register at address 6002h is activated. The CFAIL bit monitors the CLKFAIL pin (a SCSA bus signal) and requires that the CORSIGA pin be configured as the CLKFAIL input. If the CLKFAIL input goes HIGH when the MT90500 is operating in MasterAlternate mode (CLK_ALT at 6010h), the MT90500 will take over the TDM bus and become the Master TDM clock source (see the Bus Master-Alternate description in Section 4.1.1). 31 MT90500 4.1.2 4.1.2.1 TDM Interface Operation Main TDM Bus Operation The main TDM bus (pins ST[15:0]) supports SCSA, MVIP, H-MVIP, ST-BUS, and IDL protocols. These buses have different frame sync pulse orientations and different data sampling specifications, as well as different pin requirements. However, all of these buses are composed of 16 data pins, as well as CLKx2, CLKx1, and FSYNC lines. The TDM bus type is controlled by the TDM Bus Type Register at 6010h. In all bus types, outputs change on the rising edge of CLKx1. Inputs can be sampled at the 2/4, 3/4 or 4/4 point of the CLKx1 signal. MVIP/SCSA/ ST-BUS all use a negative FSYNC that is asserted for one CLKx2 cycle, straddling the frame boundary. The IDL bus uses a positive FSYNC which is asserted for one cycle of CLKx1, preceding the frame boundary. (See Figure 39, "Nominal TDM Bus Timing," on page 114.) 4.1.2.2 TDM Loopback The General Output Enable bit (GENOE in the TDM Interface Control Register at 6000h) is used to enable data to be driven out on the TDM output streams. When this bit it not set (i.e. it is LOW), the internal TDM transmit buses are connected to the internal TDM receive buses (while the internal TDM buses are disconnected from the external TDM buses) giving a TDM loopback from ATM receive back to ATM transmit. In this mode, the internally-generated TDM clocks and synchronization signals are used. This allows the user to test the MT90500 in stand-alone mode by passing receive ATM cells through the SAR, through the internal loopback at the TDM interface, and back through the SAR and out as transmit ATM cells. 4.1.2.3 Per-channel Output Enable Feature The ST[15:0] pins are bidirectional, and are able to switch between input and output directions on a perchannel basis. The Output Enable Registers located at addresses 7000 + 2N (N = 0, 1, ..., 127) are used for individual time slot output enable control. Depending on the TDM bus rate, up to 128 registers (256 bytes) are used to provide up to 2048 individual channel-output-enable bits. At 2.048 Mbps, 32 registers are used; at 4.096 Mbps, 64 registers are used; and at 8.192 Mbps, 128 registers are used. During each channel period (TDM time slot), 16 output enable bits (one register) are read from the Output Enable Registers. Within each frame, 32, 64, or 128 registers are read (depending on the TDM bus rate). The GENOE bit must be set HIGH, as well as the individual channel-output-enable bit, in order for a TDM channel to be transmitted from the MT90500 onto the TDM bus. In order to prevent data collisions on the TDM bus, the user should clear all Output Enable Register bits for channels not used as outputs, prior to setting the GENOE bit. The GENOE signal, when inactive, asynchronously deactivates the tristate buffers on the data pins and routes the output paths back into the input paths, causing the TDM bus to enter the TDM Loopback mode (see Section 4.1.2.2). Since the ST pins are bidirectional, the input sampling is always active and output data can be re-sampled back into the MT90500. This re-sampling is used when LOCSTi channels are output on a ST pin and then resampled for ATM transmission, when ST outputs are re-sampled for transfer to the LOCSTo pin, or for test and verification purposes. 4.1.2.4 Local Bus Operation * * LOCx2, LOCx1, LSYNC - clock output signals; LOCSTi, LOCSTo - Local Serial TDM data in and data out. The local bus signals are: The MT90500 provides three output clocks for the local TDM bus: LOCx2, LOCx1 and LSYNC. These clocks are derived from CLKx2, and controlled by the relevant bits in the Local Bus Type Register (register 6020h). The LCLKDIV bits allow LOCx2 to be equal to CLKx2, CLKx2 / 2, or CLKx2 / 4 (note that the local bus rate is 2.048 Mbps, which is always equal to, or less than, the main TDM bus rate). Also in register 6020h are the control bits to select the LSYNC frame-pulse type, the routing of TDM streams onto and from the local bus, and the LOCSTi sampling point.Except for the rate, the local bus type can be configured independently of the main TDM bus type. 32 MT90500 4.1.2.5 Local Bus Data Transfer Process A local bus data transfer process is provided, which allows local serial TDM input (LOCSTi) data to be output on the main TDM bus (ST[15:0]) in place of the usual data from the internal frame memory. Similarly, data from the main TDM bus can be routed directly onto the local TDM output (LOCSTo), without affecting the TDM to internal frame memory transfer. The local bus pins on the MT90500 are an extension of the main TDM bus. The data on any stream of the main TDM bus may be passed to the local bus output (LOCSTo). The source pin (one of ST[15:0]) is controlled with the STi2LOCSTo bits at 6020h, and the time slots to be transferred are indicated by the TDM Bus to Local Bus Transfer Register (6022h). Note that this TDM data can be from two sources: either externally-sourced data being driven into the selected ST pin, or data from the ATM link being driven out by the RX_SAR, and copied to the LOCSTo pin. When fewer than the maximum number of available time slots are transferred between the main TDM bus and the local bus, the unused LOCSTo output time slots are filled with data fed back internally from LOCSTi. Similarly, the data input on LOCSTi may be passed to any stream of the TDM bus as indicated by the Local Bus to TDM Bus Transfer Register (6024h), and the LOCSTi2STo bits at 6020h. Note that when the local bus to TDM process is enabled, from 1 to 32 data bytes from the RX_SAR will be replaced by local bus data. The enable bits for the main TDM bus channels are the normal bits in the Output Enable Registers (7000h + 2N). Data from the LOCSTi input pin can be transferred to the ATM link through the TX_SAR, by re-sampling the channels on which the local bus data is output as inputs to the TX_SAR. 4.1.3 4.1.3.1 TDM Data to External Memory Process General The segmentation of serial TDM input data into ATM cells starts by copying the TDM data into Transmit Circular Buffers. The data is then read out of the Transmit Circular Buffers by the TX_SAR (see Section 4.3.2, "TX_SAR Process," on page 48). The initial step of copying the serial TDM input data into the Transmit Circular Buffers is performed by the TDM Data to External Memory Process described in this section. Internal Memory External Memory TXCBBASE (Register 6044h) Tx Circular Buffer 1 TXCBBASE+64 Tx Circular Buffer 2 TDM Buses TDM Input Frame Buffer Tx Circular Buffer 3 TXCBBASE+128 Each active DS0 channel occupies a 64-byte Transmit Circular Buffer. Tx Circular Buffer n-1 Tx Circular Buffer n Figure 4 - TDM Frame Buffer to External Memory Transfer All of the serial TDM input data available on the TDM buses is first written to an internal frame buffer which holds 4 frames of TDM data per input channel. As shown in Figure 4, this internal frame memory (which is used in both the receive and transmit directions simultaneously) is used as a pingpong buffer. While one page of the memory is being loaded with input TDM data, the other page of the memory is being transferred to the Transmit Circular Buffers in external memory. This transfer occurs every 500 s (4 frames * 125 s per frame). 33 MT90500 4.1.3.2 Transmit Circular Buffer Control Structures To minimize the amount of external memory required for the TDM Data to External Memory Process, only the TDM channels assigned to be transmitted over the ATM link are transferred to external memory. Each TDM channel to be transmitted over the ATM link occupies a 64-byte Transmit Circular Buffer in external memory. As shown in Figure 5, the MT90500 fetches control data from the Transmit Circular Buffer Control Structure in external memory in order to determine which TDM channels to transfer to external memory and where to put the data. The Transmit Circular Buffer Control Structure is a sequential control table consisting of 16-bit entries: * * * Bit<15> indicates that the entry is valid (active HIGH). Bits<14:11> are not used, and should be set to zeroes. Bits<10:0> identify a channel number. * * Bits<10:4> identify a TDM channel within a stream. The channels are numbered from 0 to 127. Bits<3:0> identify a stream number, from 0 to 15. Internal Memory B "0_0000_0000" 12 <20:9> TXCBCS 15 6040h TXCBCSBASE 4 TXCBCSL Minimum of 128 entries (i.e. words) Maximum of 2048 entries 0 9 <8:0> 21 <20:0> External Memory Pointer to Start of TX Circular Buffer Control Structure 15 10 43 0 +000 V R R R R +002 V R R R R +004 V R R R R +006 V R R R R Time Slot Time Slot Time Slot Time Slot Stream Stream Stream Stream VRRRR +FFE V R R R R Time Slot Time Slot Stream Stream TDM Channels Control Data V = Entry Valid (bit<15>) R = Reserved (bits<14:11> - set to all zeroes) Time Slot = 7-bit TDM time slot select (bits<10:4>) Stream = 4-bit TDM stream select (bits<3:0>) Figure 5 - Transmit Circular Buffer Control Structure The first entry in the Transmit Circular Buffer Control Structure tells the hardware from which TDM channel it will fill the first 64-byte Transmit Circular Buffer, the second entry tells the hardware from which TDM channel it will fill the second Transmit Circular Buffer, and so on. If the entry is not valid (i.e. the V bit is not asserted), the transfer is not executed. In order to prevent unnecessary transfer of TDM data to external memory, the user should zero-out all unused entries within the TX Circular Buffer Control Structure. 34 MT90500 4.1.3.3 Transmit Circular Buffers The location of the Transmit Circular Buffers in external memory is determined by TXCBBASE (TX Circular Buffer Base Address), found in register 6044h. The first Transmit Circular Buffer is located at TXCBBASE. The second is located at TXCBBASE + 64, the third at TXCBBASE + 128, etc., as seen in Figure 4. All Transmit Circular Buffers are 64 bytes long, so buffer addresses are not included in the control structure but are considered to follow each other linearly, one after the other, corresponding to the order of the entries in the control structure. Therefore, if the base address of the TX Circular Buffers was 10000h (as defined by the TXCBBASE entry at 6044h), the first entry in the control structure (be it valid or not) would correspond to the buffer at 10000h, the next to 10040h, the one after to 10080h, etc. The last step of the TDM Data to External Memory Process transfers data from the internal frame buffer to the Transmit Circular Buffers in external memory. The write pointer to all Transmit Circular Buffers is a single 8-bit counter that increments every four frames as the Internal to External Memory transfer is performed. The 4 least significant bits in this counter are used as the TDM Circular Buffer Write Pointer. All the desired TDM channels in the internal frame buffer will be transferred into the Transmit Circular Buffers as specified by the Transmit Circular Buffer Control Structure. Note that the Transmit Circular Buffer Control Structure must be initialized before the Internal/External Memory Process is enabled (via the IEENA bit in register 6000h). 4.1.4 4.1.4.1 External Memory to TDM Data Output Process General The reassembly of received CBR (Constant Bit Rate) ATM cells into serial TDM output data is completed by reading the data out of Receive Circular Buffers and placing the data on the TDM outputs. The data is written to the Receive Circular Buffers by the RX_SAR (see Section 4.4.2, "RX_SAR Process," on page 57). Then the reading of serial TDM output data from the Receive Circular Buffers is performed by the External Memory to TDM Data Output Process. This process will be outlined here. The same internal frame buffer used in the TDM Data to External Memory Process is used to buffer the received data to be transferred to the TDM output bus. As shown in Figure 6, this internal frame buffer holds 4 frames of output data for each TDM channel (to a maximum of 2,048 channels). This frame buffer is used in a pingpong scheme where alternately half the memory is used to transfer data to the TDM buses while the other half is being used to transfer data from the external memory. TDM data is transferred from the Receive Circular Buffers in external memory to the internal frame buffer. As in the TDM Data to External Memory Process described previously, the pointer to all Receive Circular Buffers is a single 8-bit counter that increments every four frames as the External to Internal Memory transfer is performed. The least significant 4 to 8 bits of the counter are used as the TDM Circular Buffer Read Pointer, depending on the size of the Receive Circular Buffers. External Memory Rx Circular Buffer 1 Rx Circular Buffer 2 Each active DS0 channel occupies a programmable-size Receive Circular Buffer (64, 128, 256, 512, or 1024 bytes) Rx Circular Buffer 3 Internal Memory TDM Output Frame Buffer TDM Buses Rx Circular Buffer n-1 Rx Circular Buffer n Figure 6 - External Memory to TDM Frame Buffer Transfer 35 MT90500 4.1.4.2 External Memory to Internal Memory Control Structures To know which internal frame buffer TDM channels need to be written (generally, only the TDM channels scheduled for transmission on the TDM bus), the MT90500 uses control data from the External to Internal Memory Control Structure. The External to Internal Memory Control Structure is located in external memory, and is depicted in Figure 7. The control data in the External to Internal Memory Control Structure tells the hardware where in external memory the receive data is located (Rx Circ. Buf. Address), the size of the Receive Circular Buffer used, and to which TDM channel (TDM Channel #) this data must be written. The External to Internal Memory Control Structure uses a 32-bit control word, as indicated below and in Figure 7: * * Bit<15> - V - Valid bit. If HIGH, indicates that this entry is valid, and the associated Receive Circular Buffer is active. If an entry is not valid, it is simply bypassed and the next entry is read. Bit<14> - D - Write-back Disable bit. If HIGH, the receive TDM data will be left unaltered in the Receive Circular Buffer. If LOW, FFh will be written over each byte of the receive TDM data once it has been transferred to the internal frame memory. (This has the effect of putting FFh - silence - on the TDM bus if the Receive Circular Buffer underruns and the same byte is read again before new TDM output data is written to the Receive Circular Buffer by the RX_SAR.) Bit<13> - U - TDM read Underrun detection enable. If this bit is HIGH, and the External Memory to Internal Memory Process tries to transfer a byte which has already been transferred, an underrun event is detected and an interrupt may be generated. See registers 6000h, 6002h, 6046h and 6048h. This bit (and TDM Read Underrun Detection circuit) work independently of the state of the `D' bit. If this bit is written low, TDM Read Underrun detection stops for this TDM channel on the present TDM frame. Bits<12:11> - R - Not used. Bits<10:0> - TDM Channel # - identifies a destination TDM channel number and stream * * * * Bits<10:4> identify a TDM channel within a TDM stream. The channels are numbered from 0 to 127. * * Bits<3:0> identify a TDM stream number, from 0 to 15 (corresponding to the ST[0:15] pins). Rx Circ. Buff. Address and Size - indicates the Receive Circular Buffer address, and the size of the Receive Circular Buffer (64, 128, 256, 512, or 1,024 bytes). The leading bits in the field, when appended by a number of least-significant zeroes, indicate the Receive Circular Buffer address. The total number of bits representing an address should be 21 bits. For example, for a 128-byte buffer, the 14-bit address given in the structure will be appended by 7 zeroes, resulting in a 21-bit address. It is important to consider this control structure when determining the location of Receive Circular Buffers in external memory. Examining the configuration shown in Figure 7 on the next page, it can be seen that the number of bits available to identify the address of Receive Circular Buffers differs depending on the size of the buffer. Due to this restriction, it is essential that each buffer be located only on a boundary corresponding to the size of the buffer (i.e. 64-byte buffers must be located on 64-byte boundaries, 128-byte buffers must be located on 128-byte boundaries, and so on...). Once all of the entries have been scanned, the internal frame memory is filled and the External Memory to Internal Memory process terminates. If the process is still active four frames after being started, a "TDM Out of Bandwidth Error" (found in the TDM Interface Status Register at 6002h) is generated. The final step is for the MT90500 to drive the TDM data out on the TDM pins, ST[15:0]. Since not all time slots are designated as outputs, separate Output Enable Registers located at addresses 7000 + 2N (N = 0, 1, ..., 127) are used for individual time slot output enable control. In addition, the GENOE bit in the TDM Interface Control Register at 6000h must be set HIGH to enable the general Internal Memory to TDM Output Process (see Section 4.1.2.3 for more details). 36 MT90500 Internal Memory B "0_0000_0000" 9 12 <20:9> EMIM 15 6042h EIMCSBASE 4 EIMCSL Minimum of 128 entries Maximum of 2048 entries 0 +002 <8:0> Pointer to Start of External to Internal Memory Control Structure 21 15 <20:0> External Memory 11 10 TDM Channel # 0 +000 V D U R Rx Circ. Buff. Address & Size TDM Channel # +004 V D U R +006 +008 +00A Rx Circ. Buff. Address & Size VDU R TDM Channel # Rx Circ. Buff. Address & Size +1FFC V D U R +1FFE TDM Channel # Rx Circ. Buff. Address & Size Structure of the Receive Circular Buffer Address and Size Fields 15 Rx Circular Buffer Address (15 bits) address bits<20:6> 15 Rx Circular Buffer Address (14 bits) address bits<20:7> 15 Rx Circular Buffer Address (13 bits) address bits<20:8> 15 Rx Circular Buffer Address (12 bits) address bits<20:9> 15 Rx Circular Buffer Address (11 bits) address bits<20:10> 10000 10 0 100 0 1000 0 1024 bytes 512 bytes 256 bytes 1 0 128 bytes 0 64 bytes Figure 7 - External Memory to Internal Memory Control Structure 37 MT90500 4.2 External Memory Controller The external memory controller block of the MT90500 resides between the internal blocks and the external memory. It receives memory access requests from the internal blocks (TDM Interface, TX_SAR, RX_SAR, UTOPIA, and Microprocessor modules) and services them by reading data from, or writing data to, the external memory. The MT90500 pins connecting to the external memory consist of: 18 address bits (MEM_ADD[17:0]), 4 memory bank/chip selection bits (MEM_CS[1:0][H/L]), 32 data bits (MEM_DAT[31:0]), 4 parity bits (MEM_PAR[3:0]) used as TDM Read Underrun flags, 4 write enable bits (MEM_WR[3:0]), a memory output enable bit (MEM_OE), and a memory clock (MEMCLK). The external memory controller block ensures the proper timing of all memory signals and the flow control of the external memory's data bus. The external memory controller block also converts a 21-bit internal byte-oriented address to a memory bank selection and a physical address. (The 2 LSBs select one byte within the 4-byte/double-word wide data bus, up to 18 bits select a particular double-word address, and the MSB selects one of two possible memory banks.) The external memory controller block implements memory accesses to an external 36-bit Synchronous Static Random Access Memory (SSRAM or Sync SRAM). It supports one or two banks of external memory, each bank having a total capacity ranging from 32K x 36 bits to 256K x 36 bits. Thus the MT90500 can operate with external memory ranging from 128 Kbytes to 2,048 Kbytes. The external memory controller can interface with several different types of Sync SRAM, but they must support synchronous bus enabling. Synchronous bus enabling means that the Sync SRAM chip must ONLY enable its data output buffers one cycle after a read (two cycles for pipelined SSRAM), regardless of the state of the asynchronous output enable pin (MEM_OE). A read is indicated by MEM_WR[3:0] all HIGH, and the appropriate MEM_CS[1:0][H/L] asserted. The SSRAM must also support single cycle writes ("early" write, or ADSC type writes). The SSRAM can be a registered-input type ("Synchronous," "Synchronous Flow-Through," or "Synchronous Burst") or a registered-input/registered-output type ("Synchronous Pipelined"). Although the MT90500 uses the synchronous access feature of these memories, it does not use the burst access features of these memories, since most MT90500 memory accesses are random rather than sequential. Although write accesses to Synchronous SRAM and to Synchronous Pipelined SRAM are identical, there is a difference in the number of clock cycles before data is returned on the data bus during read accesses. The MT90500 supports memories with 1, 2 and 3 stages of pipelining (see Figure 8). Both 18-bit and 36-bit data bus memories are supported, but in the first case, two chips must be used in parallel to form a 36-bit data bus. Also, two 36-bit wide memory banks can be joined to double the memory's capacity (see Figure 9). Table 9 lists most of the possible memory size combinations. (Note: 16-bit and 32-bit memories can be used, but in that case the TDM Read Underrun indication will not be available.) All chips used must be of the same type. CLOCK ADDRESS ADDRESS1 ADDRESS2 DATA ADDRESS1 Captured DATA1 (Flow Through) DATA1 (Pipelined) DATA1 READLEN = 3 Note: The number of clock cycles between an address (ADDRESS1) and its read data (DATA1) is set according to READLEN in the Memory Configuration Register at address 0040h. Values greater than 3 are reserved. Figure 8 - Memory Read Pipeline Length READLEN = 1 READLEN = 2 38 MT90500 Byte Address 0 - 128K 128K - 256K 256K - 384K 384K - 512K 512K - 640K 640K - 768K 768K - 896K 896K - 1024K 1024K - 1152K 1152K - 1280K 1280K - 1408K 1408K - 1536K 1536K - 1664K 1664K - 1792K 1792K - 1920K 1920K - 2048K 32K Addressing Mode MEM_ADD[14:0] Bank 1 Bank 2 32K*4bytes 32K*4bytes 64K Addressing Mode MEM_ADD[15:0] Bank 1 64K*4bytes 128K Addressing Mode MEM_ADD[16:0] Bank 1 128K*4bytes 256K Addressing Mode MEM_ADD[17:0] Bank 1 256K*4bytes Bank 2 64K*4bytes Bank 2 128K*4bytes Bank 2 256K*4bytes Figure 9 - Logical Byte Address vs. Physical Address and Memory Banks Note: The addressing mode, which indicates the number of address lines connected to the external memory, is selected via the ADDMODE<1:0> bits in the Memory Configuration Register (0040h). CPBANK in the same register indicates the number of memory chips per bank. Table 9 - Memory Size Combinations Total Memory Size 64 Kbyte 128 Kbyte 192 Kbyte 256 Kbyte 384 Kbyte 512 Kbyte 768 Kbyte 1024 Kbyte 1536 Kbyte 2048 Kbyte External Memory Address Lines Used (Double-word Address) 13:0 14:0 14:0 14:0 15:0 15:0 15:0 16:0 16:0 16:0 17:0 17:0 17:0 Memory Addressing Mode 32K 32K 32K 32K 64K 64K 64K 128K 128K 128K 256K 256K 256K Memory Chip Size Bank 1 64 Kbyte 128 Kbyte 128 Kbyte 128 Kbyte 256 Kbyte 256 Kbyte 256 Kbyte 512 Kbyte 512 Kbyte 512 Kbyte 1024 Kbyte 1024 Kbyte 1024 Kbyte Memory Chip Size Bank 2 -- -- 64 Kbyte 128 Kbyte -- 128 Kbyte 256 Kbyte -- 256 Kbyte 512 Kbyte -- 512 Kbyte 1024 Kbyte Because of the bidirectional data bus, some synchronous SRAM devices may require a turnaround cycle. The MT90500 can be programmed to insert a turnaround cycle between a read access and a write access, as required (see Figure 10). Similarly, the MT90500 can be programmed to insert a turnaround cycle between a read access and a read access to the other memory bank. Some memories have an output disable time that is shorter than the output enable time (so a turnaround cycle between reads to different banks is not necessary), meanwhile other memories require a turnaround cycle. This type of turnaround cycle is illustrated in Figure 11. 39 MT90500 No Turnaround Cycle (Flow-Through SSRAM) MEMCLK MEM_CSnx MEM_WR ADDRESS DATA READ Address1 READ Address2 READ 1 READ 2 WRITE Address1 WRITE 1 WRITE Address2 WRITE 2 1 Turnaround Cycle (Flow-Through SSRAM) MEMCLK MEM_CSnx MEM_WR ADDRESS DATA READ Address1 READ Address2 READ 1 WRITE Address1 WRITE 1 READ 2 No Turnaround Cycle (Pipelined SSRAM) MEMCLK MEM_CSnx MEM_WR ADDRESS DATA READ Address1 READ Address2 READ 1 READ 2 WRITE Address1 WRITE 1 1 Turnaround Cycle (Pipelined SSRAM) MEMCLK MEM_CSnx MEM_WR ADDRESS DATA READ Address1 READ 1 WRITE Address1 WRITE 1 Figure 10 - Read / Write Turnaround Cycles It should be noted that turnaround cycles, in effect, restrict the memory bandwidth, and therefore the operation of the MT90500. Maximum throughput is achieved with full clock speed on the MCLK input (which drives MEMCLK), and with non-pipelined synchronous SRAM without turnaround cycles (easiest achieved by using a single bank). Maximum throughput is only required in applications requiring a full 1024 transmit TDM and 1024 receive TDM channels and extra CPU accesses for data or frequent setup. 40 MT90500 No Turnaround Cycle (Flow-Through Read) MEMCLK MEM_CS0x MEM_CS1x ADDRESS DATA Bank 0 Bank 0 Bank 0 Bank 1 Bank 0 Bank 1 Bank 1 Bank 1 1 Turnaround Cycle (Flow-Through Read) MEMCLK MEM_CS0x MEM_CS1x ADDRESS DATA Bank 0 Bank 0 Bank 0 Bank 0 Bank 1 Bank 1 Bank 1 1 Turnaround Cycle (Pipelined Read) MEMCLK MEM_CS0x MEM_CS1x Bank 0 Bank 1 Bank 0 Bank 1 Bank 1 ADDRESS DATA Figure 11 - Read / Read Turnaround Cycles All of the above features are programmable by the software controlling the MT90500. The Memory Configuration Register (0040h) must be set before any memory process can be enabled. Before any accesses are done to the external memory, the RRTA, RWTA, READLEN, CPBANK and ADDMODE fields in this register must be written and must represent the actual memory configuration. 41 MT90500 4.3 4.3.1 4.3.1.1 TX_SAR Module TX_SAR Overview General The TX_SAR block is responsible for performing CBR (Constant Bit Rate) cell assembly functions from the TDM port towards the ATM Primary UTOPIA interface, which is typically connected to a PHY device. According to a user-programmable timing algorithm, the TX_SAR circuit fetches data from the Transmit Circular Buffers located in external memory and builds CBR ATM cells (AAL1, CBR-AAL0, or CBR-AAL5) which are subsequently transferred to the MT90500 internal UTOPIA module and then to the Primary UTOPIA port. The TX_SAR block has no direct interface to the pins of the MT90500, but ties together the TDM module and the UTOPIA module. To construct CBR ATM cells, which must be periodically formed at the correct rate, an "event scheduler" is used. To support different cell payload lengths and CBR AAL types, three programmable event schedulers are provided by the TX_SAR to manage the cell transmission timing. The TX_SAR provides enough bandwidth to allow the transmission of 1024 channels. The RX_SAR allows reception of 1024 channels simultaneously. (For a total device capacity of 1024 bidirectional channels - all 2048 TDM time slots.) The amount of external memory required to support the TX_SAR process depends on the number of TDM time slots that need to be transmitted, as well as the number of simultaneous VCs. For example, the transmission of 1024 time slots over 1024 simultaneous VCs requires up to 100 Kbytes of external memory for the TX_SAR process. Less memory is required if fewer VC connections or fewer TDM time slots are used. 4.3.1.2 Supported ATM Cell Formats The AAL1 cell generation process supports TDM transport and trunking over standardized SDT (Structured Data Transfer) with pointer bytes for up to n = 122 TDM channels; over pointerless Structured Data Transfer for Cell with Pointer 46 Payload Bytes 8 7 6 5 4 3 2 VPI VCI VCI VCI HEC CSI Even Parity Sequence Count Pointer Payload Byte #1 Payload Byte #2 CRC field Even Parity CSI Sequence Count PTI CLP VCI HEC CRC field Even Parity 1 8 Cell without Pointer 47 Payload Bytes 7 6 5 4 3 VPI VCI VCI PTI CLP 2 1 GFC / VPI VPI GFC / VPI VPI Payload Byte #1 Payload Byte #2 Payload Byte #3 Payload Byte #45 Payload Byte #46 Payload Byte #46 Payload Byte #47 Figure 12 - AAL1 ATM Cell Format 42 MT90500 n =1; and over partially-filled cells (where n is less than, or equal to, the payload size). The cell parameters are configured through the microprocessor port. Figure 12 gives examples of the ATM AAL1 cell formats. The MT90500 meets the ITU I.363.1 standard for SDT for 1 to 96 octets per structure (1 to 96 TDM channels per VC). The MT90500 meets the ANSI.630 standard for SDT for 1 to 122 octets per structure (1 to 122 TDM channels per VC). TDM traffic over AAL0 is also supported (referred to in this document as CBR-AAL0). AAL0 is the "bare" or "null" adaptation layer (5 bytes of header plus 48 bytes of direct user payload). Figure 13 shows CBR-AAL0 and AAL1 partially-filled cell formats. In addition, TDM traffic over AAL5 can also be transmitted (referred to in this document as CBR-AAL5). The cell format for CBR-AAL5 is shown in Figure 14. Partially-Filled AAL1 Cell < 47 Payload Bytes 8 7 6 5 4 3 VPI VCI VCI VCI HEC CSI Sequence Count CRC field Even Parity PTI CLP VCI HEC Payload Byte #1 Payload Byte #2 Payload Byte #3 Payload Byte #4 2 1 8 7 CBR-AAL0 Cell 1 - 48 Payload Bytes 6 5 4 3 VPI VCI VCI PTI CLP 2 1 GFC / VPI VPI GFC / VPI VPI Payload Byte #1 Payload Byte #2 Payload Byte #3 Pad Byte or Payload Byte #46 Pad Byte Pad Byte or Payload Byte #47 Pad Byte or Payload Byte #48 Figure 13 - Partially-Filled AAL1 and CBR-AAL0 Cell Formats The AAL1 cell differs from the CBR-AAL0 cell in that it contains an AAL1 byte, and it may also contain a pointer byte. The AAL1 byte contains a sequence count (0 to 7), a CSI bit and the SNP (Sequence Number Protection) field. The sequence count is used to identify cell ordering, and to aid in the detection of lost cells. The CSI bit indicates the presence (CSI = 1) or absence (CSI = 0) of a pointer byte in even-numbered cells. In oddnumbered cells, the CSI bits serve to carry the SRTS nibble. The pointer byte indicates the start of the next structure (since structures may be shorter or longer than 47 bytes, and therefore move through the AAL1 payload). Also worth noting is the high-order bit of the header's PTI field, which can be set to indicate an OAM cell (a cell whose payload contains signalling rather than TDM data). The CBR-AAL5 cell differs from AAL1 and CBR-AAL0 in that its TDM payload is 40 bytes (where TDM data can occupy 8, 16, 24, 32, or 40 payload bytes), and the remaining 8 bytes are devoted to AAL5 overhead. Every cell in a CBR-AAL5 VC is an end-of-frame cell, as identified by the LSB of the PTI field in the cell header being set. In addition, each cell contains a CPCS-UU byte and a CPI byte (both unused here), two length bytes and four CRC bytes (all inserted by the MT90500). The MT90500 supports TDM trunking over AAL5, for n = 1, 8, 16, 24, 32, or 40. For n = 1, the MT90500 meets the cell format in the ATM Forum standard AF-VTOA-0083.000. 43 MT90500 CBR-AAL5 Cell 8 7 6 5 4 3 VPI VCI VCI VCI HEC Payload Byte #1 Payload Byte #2 Payload Byte #3 Payload Byte #4 PTI CLP 2 1 GFC / VPI VPI - The least-significant bit of the PTI field must be set HIGH to indicate the presence of the CRC-32 bytes (this bit indicates that this is the last cell of a data frame) - The MT90500 supports 8, 16, 24, 32 or 40 payload bytes. Thus the MT90500 will support N =1 (payload = 8, 16, 24, 32 or 40 bytes) and N = 8, 16, 24, 32 or 40 (payload = N bytes) Payload Byte #40 or Pad Byte CPCS-UU Byte = 00 CPI Byte = 00 Length Byte 1/2 = 00 Length Byte 2/2 = 8, 16, 24, 32, or 40 CRC Byte 1/4 CRC Byte 2/4 CRC Byte 3/4 CRC Byte 4/4 Figure 14 - CBR-AAL5 Cell Format 44 MT90500 4.3.1.3 Transmit Event Scheduler Overview Introduction 4.3.1.3.1 The distinctive characteristic of AAL1, and the other Constant Bit Rate techniques supported by the MT90500, is that they carry isochronous data, i.e. data that arrives at the SAR at a constant rate. For AAL1 Nx64 (an AAL1 VC carrying `N' TDM channels), the SAR has to transmit exactly N bytes in ATM cells for every N bytes that arrive in TDM frames. The TDM port delivers one byte for each of N TDM channels every frame, 8000 times a second. If "on average" the SAR transmits less than, or more than, N * 8000 bytes/s the Transmit Circular Buffer will eventually overrun or underrun (where "on average" is determined by the size of the Transmit Circular Buffer). The MT90500 TX_SAR meets this requirement by using "schedulers" that are tied to the TDM frame rate (125 s). The MT90500 scheduler ensures that N bytes are sent out in ATM cells for every frame of the TDM port. 4.3.1.3.2 Fixed TDM Payload Schedulers The simplest case of Constant Bit Rate traffic is a VC using cells of fixed TDM payload size. This includes * * * * CBR-AAL0 cells, which always carry 48 TDM payload bytes or a fixed partial-fill TDM payload, AAL1 N=1 cells, which always carry 47 TDM payload bytes or a fixed partial-fill TDM payload, partially-filled cells, which always carry the same number of TDM payload bytes (4 to 47), CBR-AAL5 cells, which always carry the same number of TDM payload bytes (8, 16, 24, 32 or 40). For a cell of constant TDM payload size `M' carrying `N' TDM channels, it can be seen that one cell of `M' bytes must be sent every M/N frames: TDM in = M/N frames * N bytes/frame = M bytes ATM out = one M-byte cell = M bytes TDM in = ATM out For this case of fixed TDM payload size, we could create a scheduler that was M/N frames long, and program it to send one cell. Let us consider a simple example (simpler than typically required of a MT90500 scheduler). If, for example, the SAR was to carry 6 TDM channels (N = 6) in a CBR-AAL0 48-byte cell (M = 48), we could use a 8 frame scheduler (48/6 = 8) with one cell event programmed: 8 frames * 6 bytes/frame = 48 bytes = one 48-byte cell If the Transmit Circular Buffers are considered, it can be seen that after one frame the six Transmit Circular Buffer will each contain one byte of TDM data. After two frames, each of the six Transmit Circular Buffers will contain two bytes of TDM data. After 8 frames each of the six Transmit Circular Buffers will contain eight bytes, enough TDM bytes to fill a 48-byte cell, therefore the scheduler is programmed send a 48-byte cell every 8 frames. For many values of N, however, M/N will not be an integer number of frames. So we could use a scheduler M frames long, and program it to send N cells (spread out over M frames). Over M frames, with N bytes arriving each frame, the SAR receives M * N bytes: TDM in = M frames * N bytes/frame = M * N bytes The SAR will send N cells of M bytes: ATM out = N cells * M bytes/cell = M * N bytes TDM in = ATM out In our example of 6 TDM channels over CBR-AAL0, we could use a 48 frame scheduler, programmed with 6 cell events: 48 frames * 6 bytes/frame = 288 bytes = 6 cells * 48 bytes/cell So over the course of 48 TDM frames the SAR receives 288 TDM bytes, and the SAR sends exactly 6 cells containing a total of exactly 288 bytes. The Transmit Circular Buffers return to a constant level, and the scheduler meets the requirements for CBR. To support CBR-AAL0, one of the MT90500 schedulers can be set to a length of 48 (long end = 47, long/short = 0), and N cell events programmed in. A typical application of the MT90500 would use a longer scheduler, set to a multiple of 48 (see below). To support AAL1 N=1, (TDM payload `M' = 47) one of the MT90500 schedulers 45 MT90500 can be set to a length of 47 (long end = 46, long/short = 0), and programmed with one cell event, as we have described. A typical application of the MT90500 might have the first of the three schedulers set this way to support AAL1 N=1. It can be seen that for N not equal to one, we can program our CBR-AAL0 scheduler a number of different ways. The most nearly constant cell rate will occur when we space the N cells evenly over the 48 frames. In our example of N = 6, we can send 6 cells together, wait 48 frames, send 6 cells, etc. But to achieve a more constant cell rate (to lower cell delay variation) we would want to send a cell and wait 8 frames, send another cell and wait 8 frames etc. By spacing the cell events 8 frames apart, our 48 frame scheduler example works identically to our 8 frame scheduler example. Thus it is always desirable to space the N cells as evenly as possible over the scheduler (remembering that the end of the scheduler will wrap back to the beginning of the scheduler). It can be seen that where a scheduler of length M is required, a scheduler of length K*M may be used (K is an integer). In an M frame scheduler we would program N cell events, in a K*M scheduler we would program K*N events. This allows us to use one scheduler to support several different cell sizes M. In the MT90500, a scheduler may be up to 256 frames long. A scheduler of length 240 (long end = 239, long/short = 0), for example, supports cell sizes of 48, 40, 30, 24, 20,16, 12, 10, 8, and 5. A scheduler of length 160 (long end = 159, long/short = 0) supports cell sizes of 40, 32, 30, 20, 16, 10, 8, and 5. A typical application of the MT90500 might have the second of the three schedulers set to 240 or 160 to support various lengths of partially-filled cells, CBR-AAL0, and/or CBR-AAL5. 4.3.1.3.3 AAL1 Long/Short Schedulers A scheduler for AAL1 may need to be slightly more complex than a scheduler for CBR-AAL0. When N is not equal to one, Nx64 AAL1 cells are not all of the same TDM payload size. When following the ITU-T Rec. I.363.1 standard, one cell in eight will carry a pointer. Cells without pointers carry 47 TDM bytes, and cells with pointers carry 46 TDM bytes. (An AAL1 sequence number byte is always present, completing the 48-byte ATM cell payload.) Although the individual cell length varies, the AAL1 eight-cell sequence contains a constant 375 bytes of TDM payload (46 + 7 * 47 = 375) for an average TDM payload of 46.875 bytes per cell. For the AAL1 case, we therefore wish to fit the N TDM bytes per frame into the 375 TDM payload bytes of an eight-cell sequence, at a constant rate. We could create a scheduler 375 frames long, and program it to send N eight-cell sequences: 375 frames * N bytes/frame = 375 * N bytes = N eight-cell sequences * 375 bytes / eight-cell sequence or 375 frames * N bytes/frame = 375 * N bytes = N * 8 cells * 46.875 bytes/cell Our scheduler of 375 frames length would be programmed for N * 8 cells, and achieve constant bit rate. It can be seen that we always program a multiple of 8 cell events into the scheduler, (N * 8 cells) this means that we can take a short-cut, and divide everything by 8. The schedulers in the MT90500 can be said to "fold" the 375 frames into 8 turns of the long/short scheduler (1 "short" turn of 46 frames, and 7 "long" turns of 47 frames). Instead of programming N * 8 cells into the 375 long scheduler, we program N cells into the 375/8 scheduler: (7 turns * 47 frames/turn + 1 turn * 46 frames/turn) * N bytes/frame = 375 frames * N bytes/frame = (375 * N) bytes and N cells/turn * (7 turns * 47 bytes/cell + 1 turn * 46 bytes/cell) = N cells/turn * (8 turns * 46.875 bytes/cell) = (375 * N) bytes Note that the "short" turn of the scheduler must still contain N cells, this means that we can not program a cell into the last frame of the "long" turn, because this last frame is not used during the "short" turn, and this cell would not be sent. 46 MT90500 Using for an example the case of N=6, we would program the AAL1 scheduler with 6 cell events over 46/47 frames: (7 turns * 47 frames/turn * 6 bytes/frame) + (1 turn * 46 frames/turn * 6 bytes/frame) = 375 frames * 6 bytes/frame = 2250 bytes and 6 cells/turn * (7 turns * 47 bytes/cell + 1 turn * 46 bytes/cell) = 6 cells/turn * (375 bytes/turn) = 2250 bytes To support AAL1 Nx64, one of the MT90500 schedulers can be set up with one turn of 46 and 7 turns of 47 (long end = 46, short end = 45, long/short = 7). We program N cells into the first 46 frames of the scheduler, and we know that the 8 turns of the scheduler will take 375 frames, during which we will send N * 8 cells, containing N * 375 bytes of TDM data. A typical application of the MT90500 might have the last of the three schedulers set this way to support AAL1 Nx64. 4.3.1.3.4 Other Considerations The Transmit Circular Buffer operation of the MT90500 is slightly more complex than the theoretical examples above. The MT90500 uses a four-frame buffer to optimize TDM data transfers, and this means that the Transmit Circular Buffers are actually written four bytes at a time, every four frames. For this reason the schedulers in the MT90500 operate on the quad-frame by default. In addition, the long/short operation of the AAL1 scheduler requires that an extra byte be held in the Transmit Circular Buffer. Finally, the number of frames between cells must be an integer. These extra considerations mean that in general a cell will not be transmitted when there are exactly M/N bytes in the Transmit Circular Buffer, but at some point afterwards. This adds slightly to the transmission delay, but does not require attention on the part of the user, except in the programming of the "Circ. Buff. Pnt." field of the Transmit Control Structure (see below). 47 MT90500 4.3.2 TX_SAR Process Figure 19 at the end of this section gives an overview of the processes explained below. A theoretical overview of scheduler operation is given above, in Section 4.3.1.3. 4.3.2.1 Transmit Event Schedulers As discussed in Section 4.1.3, a 64-byte Transmit Circular Buffer is maintained in external memory for each TDM channel whose data needs to be transmitted on the ATM link. Structures known as "transmit event schedulers" are used to tell the hardware when a cell needs to be assembled for transmission. The three transmit event schedulers all have similar properties and individual configuration registers. Each transmit scheduler is divided into a programmable number of "frames". The circuitry operates to constrain each scheduler frame to last an average of 125 s, which is the time required for 1 byte to be received / transmitted on each TDM channel. Within each frame 8, 16, or 32 VC Pointers can be programmed to transmit cells. When multiple schedulers are used simultaneously, one must assume that any frame in one scheduler can be superposed onto any frame in another scheduler. To limit cell delay variation, each frame (composed of events from one, two, or three schedulers) should contain no more than 45 VC Pointers (or transmission events) for 155 Mbps systems, and no more than 7 VC Pointers for 25 Mbps systems. For example, if three schedulers are programmed and each scheduler's most-filled frame contains respectively 22, 8, and 28 VC Pointers, the worst case scenario is a frame with 58 cells, thus over the 45 VC Pointers per frame limit for 155 Mbps. This type of situation must be avoided to minimize the cell delay variation resulting from an unbalanced or temporarily overloaded transmit scheduler. The TX_SAR will generate a fatal "SCHEDULE" error (see TX_SAR Status Register at 2002h) if the schedulers fall behind in their scheduled cell transmission by 8 frames. This would be caused when more than 8 consecutive frames contain more than 7 (25 Mbps) or 45 (155 Mbps) VC Pointers. The same error may also occur when the TX_SAR is heavily loaded and other processes are using more bandwidth than they normally do. The RX_SAR and UTOPIA modules use the external memory's bandwidth unevenly over time, depending on the rate at which cells arrive. They can cause "SCHEDULE" errors in the TX_SAR when the MT90500 is near its maximum load. This error is generated by the TX_SAR when it is at least 8 frames (1 ms) late. To prevent cell delay variation, "SCHEDULE" errors, and TDM data unavailability, the software that configures the TX_SAR should use an efficient algorithm to fill the event schedulers. Events that send cells on the same VC must be evenly distributed in the event scheduler. The distance between two events associated with the same VC must be as constant as possible. For an 8-channel AAL1-SDT type cell (with a pointer byte sent in cell #0 of each sequence), the distance between two events must be 46.975/8 ~ 5.86 frames. Since this number must be an integer, the event spacing should be 6-6-6-5-6-6-6-5 frames. This regular transmission of cells is also important in limiting the CDV (Cell Delay Variation) of the transmitted cells. Each programmable event scheduler is composed of a "base address", a "short end", a "long end", a "long/ short ratio" and a certain number of events per frame, as shown in Figure 15. This information is set in the TX_SAR registers located at addresses 2010h/2020h/2030h, 2012h/2022h/2032h, and 2014h/2024h/2034h. The key to supporting different cell types is to have a programmable short and long end for each scheduler. For AAL1-SDT type cells, the scheduler ends at frame 45 for P-Type cells (short end) and at frame 46 for non PType cells (long end). The ratio between the long and short end can be programmed to either 1 (to generate PType cells every even-numbered cell), 3 (to generate P-Type cells every other even-numbered cell), or 7 (to generate P-Type cells once in every 8-cell sequence). The PSEL field in the Transmit Control Structure (Figure 16) must represent the long/short ratio in the event scheduler, except in the case of partially-filled cells. For a VC which is to carry partially filled cells, the long/short ratio is set to 0. When the long/short ratio is equal to 0, the scheduler always counts to the long end before returning to frame 0. This mode is used for CBR-AAL0, CBR-AAL5, pointerless AAL1 Structured Data Transfer, and partially-filled cell formats, since the number of CBR payload bytes in these cells is constant (regardless of the value of the PSEL field). For a partially filled P-type cell (i.e. containing an AAL1 pointer-byte) one less pad byte is inserted after the TDM data than for a partially filled cell without a pointer byte. The event scheduler can be truncated down to as few frames as necessary to support the desired partially-filled cell length. On the other hand, the event scheduler can also be enlarged so that its length is an integer number which is a multiple of all the partial length formats that need to be supported. For example a scheduler of length 96 will support the following cell fill sizes: 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, and 48. For specific examples regarding scheduler configuration, please refer to the MT90500 Programmers' Manual. 48 MT90500 TESBAA TESBAB TESBAC 2010h 2020h 2030h 15 12 11 SBASE <20:9> 12 0 ENTRY 21 <20:0> <8:0> B"0_0000_0000" number of entries per frame given by ENTRY<3:0> Pointer to Start of Event Scheduler Frame 0 Frame 1 Frame 2 Frame 3 +00 VC Pointer #1 VC Pointer #2 VC Pointer #3 VC Pointer #4 Programmable size (8, 16, or 32 entries per frame) Minimum Scheduler Length - 1 frame Maximum Scheduler Length - 256 frames Frame 4 Frame 5 Frame 44 Pointer Short End Pointer Long End Frame 45 Frame 46 Frame 47 +3E VC Pointer #29 VC Pointer #30 VC Pointer #31 VC Pointer #32 Frame 252 Frame 253 Frame 254 Frame 255 15 TX_Struct_Pnt 432 R T 0 R = Reserved (must be set to `0') T = Entry Type: 000 = inactive; 001 = non-CBR data; 010 = AAL1/CBR-AAL0; 111 = CBR-AAL5; all other values = Reserved Pointer to Start of Event Scheduler 20 SBASE (from 2010h,2020h,2030h) 98 0 Pointer to Start of Transmit Control Structure - see Figure 16 16 15 20 TXBASE (from 2040h) 43 TX_Struct_Pnt 0 000000000 0000 Figure 15 - Transmit Event Scheduler When the MT90500 is used to transmit CBR-AAL5 cells, additional register programming is required to properly initialize the TX_SAR and the schedulers to send cells containing 32-bit CRCs. Regardless of which scheduler(s) is (are) to be used for transmission of the ATM cells, the following initialization settings must be made: * * * TX_SAR End Ratio Register - Scheduler A at 0x2014: set bits<7:6> = "01". TX_SAR End Ratio Register - Scheduler B at 0x2024: set bits<7:6> = "10" TX_SAR End Ratio Register - Scheduler C at 0x2034: set bits<7:6> = "11" 49 MT90500 4.3.2.2 Transmit Control Structures Within each frame within a transmit event scheduler 8, 16, or 32 VC Pointers can be programmed. Each entry represents a request to the hardware to generate a cell on that VC. An entry can be active or not, depending on the T bits located in the three LSBs of the entry word. An inactive entry is skipped. An active entry either tells the hardware to transmit the next non-CBR data cell held in the Transmit Data Cell FIFO in the external memory, (as explained in Section 4.3.3) or to transmit a CBR cell characterized by the Transmit Control Structure at the address pointed to by "TX_Struct_Pnt". This latter process will be outlined in this section. Once an active CBR VC Pointer is found in the event scheduler, the TX_SAR reads the Transmit Control Structure (Figure 16 for CBR-AAL0 and AAL1 type cells, Figure 17 for CBR-AAL5 type cells) and may either send a cell or not. The `A' bit in the Transmit Control Structure indicates whether the structure is active (an inactive structure will never generate a cell). When opening a VC, this three step procedure must always be followed: first, the software must write the Transmit Control Structure into the memory and clear both the `A' and `S' bits in that structure; second, all events pointing to the Transmit Control Structure must be written in the event scheduler; finally, the `A' bit must be set by the software. This procedure forces the hardware to ignore all events pointing to a Transmit Control Structure until its `A' bit is set. When the `A' bit is set, all scheduler events for this VC immediately become active and the transmission process for this VC is enabled. Please refer to the MT90500 Programmers' Manual, for detailed information on setting up a VC for the TDM to ATM Transmit Process. 15 +00 +02 +04 +06 +08 +0A +0C +0E +10 V +12 V +14 V +16 V First Entry HEC Current Entry Offset GFC / VPI(11:8) 87 A AS SEQ Last Entry Payload Size Circ. Buf. Pnt. PSEL VCI(15:12) PTI C1 0 R S 00 VPI(7:0) Special Notes: First Entry: indicates location of the first TX Circular Buffer Address within the Transmit Control Structure (lower bits are always 1000). Note difference between first entry location in CBR-AAL5 Transmit Control Structure and AAL1/CBR-AAL0 Transmit Control Structure. AS: AAL Type. "00"= CBR-AAL5 (AAL5 cells are a special case of AAL0). PSEL: P-Byte Selection. "0000" for CBR-AAL5. PTI: LSB of field must be set to `1' to identify this as a CBR-AAL5 type cell. VCI(11:0) 0000 0000 0000 0000 0000 0000 0000 0000 TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) Minimum Structure Size - 18 bytes Maximum Structure Size - 96 bytes +58 V +5A V +5C V +5E V TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) Figure 17 - Transmit Control Structure Format (CBR-AAL5) If the Transmit Control Structure has never been updated by the hardware, the "Circ. Buf. Pnt" field must indicate "how old" (in terms of 125s TDM frames) the first byte in the first cell should be. For instance, if a cell contains 47 bytes, and the age of the first byte to be sent is 46, the last byte to be sent in the cell will have an 50 MT90500 15 +00 +02 +04 +06 +08 +0A +0C V +0E V +10 V +12 V +14 V +16 V First Entry HEC Current Entry Offset GFC / VPI(11:8) 87 A AS SEQ Last Entry Payload Size Circ. Buf. Pnt. PSEL VCI(15:12) PTI C1 0 First Entry: indicates location of the first TX Circular Buffer Address within the Transmit Control Structure (lower bits are always 110). A: Structure Active bit. `0' = inactive; `1' = active. Last Entry: indicates where last TX Circular Buffer Address is located within the Transmit Control Structure. HEC: HEC value (optional). AS: AAL Type. "00"= CBR-AAL0/AAL5; "01"=Reserved; "10"=AAL1; "11"=AAL1SRTS Payload Size: Indicates the number of payload bytes within an ATM cell. Full cell = 2Fh. Partially-filled cells = 03h to 2Eh. Current Entry: indicates location of the current Transmit Circular Buffer. Must be initialized to First Entry value and is incremented by hardware. SEQ: Indicates AAL1 sequence number. Possible sequence values are "000" to "111". Must be initialized by software to "000". Circ. Buf. Pnt: This field must be initialized by software to initial offset required between TX_SAR Read Pointer and TDM Circular Buffer Write Pointer. Offset: Offset value between the TDM Circular Buffer Write Pointer and the TX_SAR Read Pointer is stored in this field. Should be set to initial value of `0'. R: Reserved (set to `0'). S: Structure Initialized. `0' = uninitialized; `1' = initialized. Must be set as `0' by S/ W. PSEL: P-Byte Selection. `0' for pointerless AAL1 Structured Data Transfer and CBR-AAL0; `8' for standardized SDT (see text for more details). GFC: Cell Header GFC field (UNI). VPI: Cell Header VPI field. VCI: Cell Header VCI field. PTI: Cell Header PTI field. LSB of field, when set to `1', indicates OAM-type cell. C1: Cell Header CLP bit. V: TX Circular Buffer Valid Bit. `0' = invalid entry; `1' = valid TX Circular Buffer address. TX Circular Buffer Address: This is the upper part of the address that points to a Transmit Circular Buffer (bits 20:6). The buffer must be located relative to the TX Circular Buffer Base Address (TXCBBASE) set in register 6044h. R S 00 VPI(7:0) VCI(11:0) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) Minimum Structure Size - 14 bytes Maximum Structure Size - 256 bytes +F8 V +FA V +FC V +FE V TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) TX Circular Buffer Address (bits<20:6>) Pointer to First TX Circular Buffer Entry 87 20 Upper Structure Address First Entry 0 0 Pointer to Start of Transmit Control Structure 16 15 43 0 20 TXBASE TX Struct Pointer (see 0000 (from 2040) Figure 15) Note: Transmit Control Structures must start on 16-byte boundaries and cannot overlap 256-byte boundaries. Pointer to Current TX Circular Buffer Entry 87 20 Upper Structure Address Current Entry 0 0 Pointer to Last TX Circular Buffer Entry 87 20 Upper Structure Address Last Entry 0 0 Note: Upper Structure Address is obtained from the upper 13 bits (i.e. bits<20:8>) of the Pointer to Start of Transmit Control Structure. Figure 16 - Transmit Control Structure Format (AAL1 & CBR-AAL0) age of -1 (i.e. it hasn't arrived at the MT90500 yet). Thus, in the case of a single channel AAL1-SDT VC, the software must initialize the value of the Circ. Buf. Pnt. to at least 47, ensuring that at least 47 bytes are available for cell assembly when the scheduler is ready to transmit an event. This will also ensure that the most recent 47 bytes of data are sent. A value greater than 56, however, is not recommended because the oldest data to be sent in a cell may be overwritten by the TDM module and replaced by new data. A value of 51 to 56 is recommended for any single channel AAL1 or CBR-AAL0 fully-filled cell. When using hyper-channels or 51 MT90500 partially-filled cells, much lower values should be written in this field, thus reducing transmission delay. The following equations (used to calculate the initial "Circ. Buf. Pnt." to be written by the software) are valid for most cell types: AAL1 SDT-type Cells: Circ. Buf. Pointer = ROUNDUP ((max. # of payload bytes per cell / # of channels per VC) * ROUNDUP (# of channels per VC / min. # of payload bytes per cell * 4)) + 5 All other cells: Circ. Buf. Pointer = ROUNDUP ((max. # of payload bytes per cell / # of channels per VC) * ROUNDUP (# of channels per VC / min. # of payload bytes per cell * 4)) + 4 The "Offset" field is used by internal hardware to verify the offset between the TDM Circular Buffer Write Pointer and the TX_SAR Read Pointer (which is stored in Circ. Buf. Pnt. in the Transmit Control Structure, once the structure becomes active). Offset should be initialized to "00h". All Transmit Control Structures must begin on 16-byte boundaries, and may not overlap 256-byte boundaries. Any Transmit Control Structure that overlaps a 256-byte boundary will cause unpredictable SAR behaviour. The "First Entry", "Current Entry", and "Last Entry" fields are pointers that must be set relative to the beginning of the particular Transmit Control Structure. The First Entry field represents the location of the first TX Circular Buffer Address within a Transmit Control Structure. This 7-bit field represents the 8 LSBs of the actual entry location divided by two (shifted right by one). When the Transmit Control Structure represents CBR-AAL0 or AAL1 type data, the lower three bits of the "First Entry" will always be "110" since the first entry is always 12 bytes away from the start of the Transmit Control Structure. When transmitting CBR-AAL5 type cells, the lower four bits of the "First Entry" will always be "1000" because the first TX Circular Buffer Address is located 16 bytes away from the start of the Transmit Control Structure. The "Current Entry" and "Last Entry" fields are programmed similarly, with "Current Entry" bearing the same address as "First Entry" when the structure is initialized by software. The programming of the First Entry and Last Entry fields for two examples can be seen below in Figure 18. Note that the Transmit Control Structure is not active until the A bit in the first byte of the structure is set HIGH. The cell header portion of the Transmit Control Structure is passed directly to the UTOPIA bus without any modifications. Typically, the PHY device will calculate the HEC and over-write the HEC field in the Transmit Control Structure. However, in the case where the PHY device does not calculate the HEC field, the HEC byte may be calculated by the CPU, and written into the HEC field of the Transmit Control Structure. The AS field indicates to the TX_SAR if the VC is a CBR-AAL0/AAL5, AAL1-SRTS, or AAL1 VC. Note that only one Transmit Control Structure can be programmed with the AAL1-SRTS flag. The SRTS only changes relative to one VC since it can only be synchronized to one VC. The "payload-size" field in the Transmit Control Structure indicates the number of TDM bytes carried in an ATM cell. For a fully-loaded cell of AAL1 or CBR-AAL0, the payload-size field must be set to a value of 2Fh (decimal 47) which represents a full payload for CBR-AAL0 (48 TDM bytes), pointerless AAL1 Structured Data Transfer (47 TDM bytes plus 1 AAL1 byte), and AAL1-SDT (47 TDM bytes plus 1 AAL1 byte, or 46 TDM bytes plus 1 AAL1 byte plus 1 pointer byte). For a fully-loaded cell of CBR-AAL5, the payload-size field must be set to a value of 27h (decimal 39) which represents a full payload for CBR-AAL5 (40 TDM bytes). For partially-filled cells, the payload-size field may be set to a value ranging from 03h to 2Eh. Note that these values represent different numbers of payload bytes, depending on the type of data structuring that is being used. For example, to represent a fill of 32 TDM bytes in each CBR-AAL0 or CBR-AAL5 cell, the user should set a payload-size of 1Fh. However, in order to ensure that each AAL1 cell (SDT or pointerless Structured Data Transfer format) contains 32 TDM bytes, the payload-size must be set to 20h. Similarly, while a payload-size of 7h indicates that the transmitted CBR-AAL0 or CBR-AAL5 cells contain 8 bytes of TDM data a payload-size of 8h is required to ensure a fill of 8 TDM bytes in each cell transmitted using AAL1-SDT or pointerless AAL1 Structured Data Transfer. In general, the payload-size field should be set to the expected number of TDM bytes when transmitting AAL1-type cells, and it should be set to one less than the expected number of TDM bytes when transmitting CBR-AAL0 and CBR-AAL5 cells. As well, it should be noted that 2Eh (decimal 46) is an illegal value for AAL1-SDT. The PSEL nibble is used to denote the cell(s) within an 8-cell sequence in which the pointer byte (P-byte) is to be sent. When using pointerless AAL1 Structured Data Transfer, no pointer cells are ever sent, and the PSEL nibble must be initialized to 0h. With SDT, pointers may be sent in cells 0, 2, 4, or 6 of a sequence. The MT90500 can support both standardized and proprietary SDT formats. In order to meet ITU-T I.363.1, a structure (i.e. a specific VC) must be composed of no more than 96 channels, and the P-byte must be sent in the first (i.e. sequence number = 0) cell of each 8-cell cycle. Thus the PSEL field must be set to 1000 (the 52 MT90500 15 20180 20182 20184 20186 First Entry HEC Current Entry Offset 87 A AS SEQ Last Entry Payload Size Circ. Buf. Pnt. PSEL 0 0 First Entry location = 2018C 1000110 First Entry field A A R S 00 VPI(7:0) GFC / 20188 VPI(11:8) 2018A 2018C V 2018E V 20190 V VCI(15:12) PTI C1 Last Entry location = 20190 VCI(11:0) TX Circular Buffer Address TX Circular Buffer Address TX Circular Buffer Address 1001000 Last Entry field 0 0 Figure 18 - a: Sample Three-Channel Transmit Control Structure (AAL1/CBR-AAL0) 15 20180 20182 20184 20186 First Entry HEC Current Entry Offset 87 A AS SEQ Last Entry Payload Size Circ. Buf. Pnt. PSEL 0 0 First Entry location = 20190 1001000 First Entry field A A R S 00 VPI(7:0) GFC / 20188 VPI(11:8) 2018A 2018C 2018E 20190 V VCI(15:12) PTI C1 Last Entry location = 20190 VCI(11:0) 0000 0000 0000 0000 0000 0000 0000 0000 1001000 Last Entry field 0 0 TX Circular Buffer Address Figure 18 - b: Sample One-Channel Transmit Control Structure (CBR-AAL5) PSEL bits are one-hot bits which represent cells with sequence numbers 0, 2, 4, and 6, respectively - see Table 10 below for an explanation of bit operation). The MT90500 also supports proprietary pointer transmissions in which a P-byte is sent every 4 cells (PSEL = A hex) or every other cell (PSEL = F hex). Using these proprietary methods, up to 122 channels can be sent on a particular VC, but this is only possible if the receiving chip can handle the extra P-bytes during a cycle. Table 10 - Effect of PSEL Field on P-byte Generation Sequence # 0 0000 Sequence # 2 Sequence # 4 Sequence #6 Applicable Standards ANSI and ITU-T - AAL0, AAL5, pointerless AAL1 Structured Data Transfer, and partiallyfilled cells Pointer sent ANSI and ITU-T - AAL1-SDT ANSI - AAL1-SDT ANSI - AAL1- SDT No pointers are sent. 1000 1010 1111 Pointer sent. Pointer sent Pointer sent Pointer sent Pointer sent Pointer sent Each "TX Circular Buffer Address" appended to the end of the structure points to a 64-byte circular buffer in external memory. 53 MT90500 C A Transmit Event Scheduler - one for each type of AAL data (3 schedulers possible) Controls scheduling of transmission of VCs within frames B External Synchronous SRAM ** TX Circular Buffers - one for each TDM channel to be transmitted Transmit Control Structures one for each VC Dictate which Circular Buffer data to be sent on each VC * ** * Directs TDM data to Circular Buffers Transmit Circular Buffer Control Structure MT90500 TX AAL1 SAR Primary Cell Queue Secondary Cell Queue TDM Bus 16 lines 1024 x 64kbps (max.) Local TDM Bus 32 x 64 kbps in/ 32 x 64 kbps out Clock Signals TDM Module TDM Bus Interface Logic TDM Clock Logic To External PHY Main UTOPIA Interface TX UTOPIA MUX Internal TDM Frame Buffer From Secondary External UTOPIA SAR Interface UTOPIA Module Figure 19 - Overview of CBR Data Transmission Process 54 MT90500 4.3.3 Non-CBR Data Cell Transmission Capability The TX_SAR also has the ability to transmit CPU-written non-CBR data cells directly from a user-defined FIFO in external memory (the Transmit Data Cell FIFO) to the UTOPIA module. Non-CBR data cells include OAM cells, other signalling cells, and AAL5 cells containing CPU data. Once the CPU writes the complete cell into the Transmit Data Cell FIFO, the UTOPIA module then treats these non-CBR data cells the same as the normal CBR cells. All 53 bytes of the non-CBR data cells are written by the microprocessor into the FIFO in 64-byte long structures located on 64-byte boundaries (see Figure 21). There are 16, 32, 64 or 128 of these structures contained in the circular FIFO, mapped in the external memory at the address determined by the Transmit Data Cell FIFO Base Address Register (register 2050h). This FIFO must not overlap an 8-Kbyte boundary. If the FIFO does overlap an 8K boundary, some or all of the non-CBR cells sent by the TX_SAR will be corrupted. There are two ways to control transmission of non-CBR data cells: by scheduler, or by AUTODATA. The scheduler method requires mapping data cell events into one of the transmission schedulers being used. This is done by writing "001" in the Entry Type section of the VC Pointer entry, as shown in Figure 20. VC Pointer 15 TX_Struct_Pnt 432 R T 0 R = Reserved (must be set to `0') T = Entry Type (000 = inactive; 001 = non-CBR data; 010 = AAL1/CBR-AAL0; 111 = CBR-AAL5; all others: Reserved) 15 XXXX XXXX XXXX 432 0 001 0 Figure 20 - VC Pointer For Scheduler-Controlled Non-CBR Data Cell In this case, when the scheduler hits the frame within which this entry is contained, it will read the next valid data cell from the Transmit Data Cell FIFO and transmit it. Because non-CBR cell transmission does not require the use of Transmit Control Structures, the TX_Struct_Pnt field in the VC Pointer is not used and thus its value is irrelevant. Note that using the scheduler(s) to control non-CBR data transmission results in regularly spaced non-CBR data cells, as specified in the scheduler entries. The other possibility for controlling transmission of non-CBR data cells is by using the AUTODATA bit in the TX_SAR Control Register at 2000h. While that bit is HIGH, once the TX_SAR has completed its assigned cells for a certain quad frame (or frame) and is waiting for its next pulse (i.e. the TX_SAR is idle), the MT90500 will automatically transmit data cells, provided that data cells are available in the Transmit Data Cell FIFO. This process will end as soon as the next pulse is detected (Note: The non-CBR cell being treated at that time will be completed before the TX_SAR returns to CBR cell assembly). Both these cases require the microprocessor to write the full non-CBR data cell into the Transmit Data Cell FIFO, and then to write the new (incremented) value of the Transmit Data Cell FIFO Write Pointer (address 2052h). Non-CBR data cells will only be sent if the Transmit Data Cell FIFO Write Pointer and the Transmit Data Cell FIFO Read Pointer (address 2054h) indicate that there are valid cells contained in the FIFO. When the pointers are not equal, the TX_SAR goes to the appropriate address indicated by the Transmit Data Cell FIFO Base Address Register (address 2050h) and reads the non-CBR data cell. Note that although the FIFO read pointer will be automatically adjusted to fit the Transmit Data Cell FIFO size (for example, if the FIFO size is 32 cells, when the read pointer is 31 and a cell is read, it will wrap around to 0), that is not true of the write pointer. Therefore, if the FIFO write pointer is set to 128, non-CBR cells will always be considered valid. 55 MT90500 15 GFC or VPI(11:8) 87 VPI(7:0) VCI(11:0) HEC Byte Reserved Data Byte #0 Data Byte #2 Data Byte #4 Data Byte #6 Data Byte #8 0 VCI(15:12) PTI, etc. Reserved Reserved Data Byte #1 Data Byte #3 Data Byte #5 Data Byte #7 Data Byte #9 +00 +02 +04 +06 +08 +0A +0C +0E +10 +32 +34 +36 +38 +3A +3C +3E Data Byte #42 Data Byte #44 Data Byte #46 Reserved Reserved Reserved Reserved Data Byte #43 Data Byte #45 Data Byte #47 Reserved Reserved Reserved Reserved Figure 21 - Transmit Non-CBR Data Cell Structure Format 56 MT90500 4.4 The RX_SAR Module Figure 30 at the end of this section gives an overview of the processes explained below. 4.4.1 RX_SAR Overview The RX_SAR block performs cell identification and reassembly functions on data moving from the Primary UTOPIA Port (refer to Section 4.5) toward the TDM interface. The RX_SAR module receives cells from the UTOPIA module, which has the capability of identifying cells as either CBR cells or non-CBR data cells. When non-CBR data cells are received by the UTOPIA module, they are stored in a multi-cell circular buffer located in external memory. When CBR cells are detected (AAL1, CBR-AAL5 or CBR-AAL0), they are processed and the payload is extracted and stored in time slot-related circular buffers, the size of which can be individually programmed by software on a per-VC basis. The RX_SAR block supports AAL1-SDT, pointerless AAL1 structured data transfer (for ITU I.363.1 voiceband signal transport) and AAL0 cell formats. CBR-AAL5 cells are treated as partially-filled AAL0. Single or multiple (up to 122) TDM channels are supported per Virtual Circuit (specific VPI/VCI). On the receive side, the MT90500 RX_SAR block has the ability to receive and process up to 1024 Virtual Circuits simultaneously (and up to 1024 TDM channels at 64 kbps), resulting in a total of about 74 Mbps of bandwidth on the receive side. If 1024 TDM channels are used for full-duplex connections such as phone calls, the bandwidth will be ~74 Mbps per direction. The amount of external memory required for the handling of receive VCs is variable and is defined by the user. The external memory requirements to support the RX_SAR are scalable and depend mainly on the number of TDM channels that need to be received on the ATM link and the size of the receive circular buffer required to compensate for latency and CDV (cell delay variation). As an example, the reception of 1024 simultaneous Virtual Circuits, each representing a 64 kbps channel, each with a 128 ms buffer, requires external memory capacity exceeding 1024 Kbytes (SRAM). The RX_SAR module has no interface to the external pins. It has internal connections to the External Memory Controller, the UTOPIA module, and the Microprocessor Interface. It also receives synchronization signals from the TDM module. No fatal errors can be generated by the RX_SAR. Most of the registers associated with it are targeted at network statistics and error monitoring. 4.4.2 RX_SAR Process As explained in Section 4.5, detailing the operation of the UTOPIA module, cells received over the ATM link that are intended for the RX_SAR are tagged and forwarded to the RX_SAR module. For the traffic tagged as CBR, the RX_SAR then uses control information in the RX_SAR Control Structures to extract the payload data from the received cell and store it into TDM channel RX Circular Buffers located in external memory. For the traffic tagged as non-CBR data, the RX_SAR simply stores the whole cell, which is considered to be a raw AAL0 cell, in a circular FIFO located at the address specified by the Receive Data Cell FIFO Base Address Register (4020h). This will be explained further in Section 4.5.4. In addition, timing reference cells (which may carry CBR traffic or non-CBR data) can also be received on the ATM side of the MT90500. As outlined more fully in Section 4.5.3, the reception of these cells results in the generation of timing pulses used in Adaptive Clock Recovery. For each VC assigned to CBR traffic in reception, an RX_SAR Control Structure has to be set up and maintained in external memory, as explained below. 57 MT90500 4.4.2.1 RX_SAR Control Structures The RX_SAR Control Structure is quite similar to the Transmit Control Structure shown in Figure 16, but it has added cell delay variation control fields (as seen in Figure 22). The "First Entry", "Current Entry", "Last Entry", "AS", "S", "Payload Size", "V", and "RX Circular Buffer Base Address" fields all have the same properties as in the TX_SAR. 15 +00 +02 +04 +06 +08 +0A S First Entry Minimum Lead Average Lead Reserved Current Entry BS 0 AS 87 0 Last Entry Maximum Lead Payload Size Reserved AAL1 Byte 0 0 First Entry: Indicates location of the first RX Circular Buffer Base Address within the RX_SAR Control Structure. Last Entry: Indicates where the last RX Circular Buffer Base Address is located within the RX_SAR Control Structure. Minimum Lead: Indicates the minimum number of bytes that must always be valid in the RX Circular Buffer (to get the number of bytes, multiply Minimum Lead by four). Usually initialized to 01h. Maximum Lead: Indicates the maximum number of bytes that may be valid in the RX Circular Buffer (to get the number of bytes, multiply Maximum Lead by four). Average Lead: Indicates the average number of bytes that are valid in the RX Circular Buffer (to get the number of bytes, multiply Average Lead by four). Equal to (Minimum Lead + Maximum Lead) / 2. AS: AAL Type. "00"= CBR-AAL0 & CBR-AAL5; "01"=Reserved; "10"=AAL1; "11"=AAL1-SRTS Payload Size: Indicates the number of payload bytes within an ATM cell. Full cell = 2Fh (48 bytes). Partially-filled cells = 03h to 2Eh. Current Entry: Indicates location of the current Receive Circular Buffer. Must be initialized to First Entry value and is incremented by hardware (or realigned with arrival of pointer byte). AAL1 Byte: Used by hardware to check for cell loss / misinsertion. Should be initialized to 00h. S: Structure Initialized. `0' = uninitialized; `1' = initialized. Must be set as `0' by S/W. BS: Circular Buffer Size. "000" = 64 bytes; "001" = 128 bytes; "010" = 256 bytes; "011" = 512 bytes; "100" = 1024 bytes; other = reserved. RX_SAR Write Pointer: When S bit is `0', uninitialized; when S bit is `1', indicates which byte in the RX Circular Buffer the hardware will write first with the data in the next cell. V: Receive Circular Buffer Valid Bit. `0' = not valid; `1' = valid (write received cell data to a circular buffer). RX Circular Buffer Base Address: This is the upper part (bits 20:6) of the address that points to a Receive Circular Buffer. Note: RX Circular Buffers must be located on boundaries corresponding to the size of the buffer (see Figure 7 on page 37 for clarification). Reserved: Set to all zeroes. RX_SAR Write Pointer +0C V +0E V +10 V +12 V +14 V +16 V RX Circular Buffer Base Address (bits<20:6>) RX Circular Buffer Base Address (bits<20:6>) RX Circular Buffer Base Address (bits<20:6>) RX Circular Buffer Base Address (bits<20:6>) RX Circular Buffer Base Address (bits<20:6>) RX Circular Buffer Base Address (bits<20:6>) Minimum Structure Size - 14 bytes Maximum Structure Size - 256 bytes +F8 V +FA V +FC V +FE V RX Circular Buffer Base Address (bits<20:6>) RX Circular Buffer Base Address (bits<20:6>) RX Circular Buffer Base Address (bits<20:6>) RX Circular Buffer Base Address (bits<20:6>) Pointer to Start of RX_SAR Control Structure 20 18 17 RXBASE (from 4000) 43 RX Structure Address (set by software) 0 0000 Pointer to First RX Circular Buffer Entry 87 20 Upper Struct Address First Entry 0 0 Note: RX_SAR Control Structures must start on 16-byte boundaries and cannot overlap 256-byte boundaries. Pointer to Current RX Circular Buffer Entry 87 20 Upper Struct Address Current Entry 0 0 Pointer to Last RX Circular Buffer Entry 87 20 Upper Struct Address Last Entry 0 0 Note: Upper Struct Address is obtained from the upper 13 bits (i.e. bits<20:8>) of the Pointer to Start of RX_SAR Control Structure. Figure 22 - RX_SAR Control Structure 58 MT90500 Three cell delay variation control fields must be initialized by the software: the "Minimum Lead", "Maximum Lead" and "Average Lead". Each of these fields is concatenated with "00" (i.e. multiplied by 4) to have a range from 0 to 1020. Before disassembling any cell, the RX_SAR verifies its write pointer's validity with respect to the Maximum and Minimum Lead fields, as discussed in Section 4.4.2.2. The AAL1 byte is used by hardware to check the cell sequence number and therefore provide cell loss / misinsertion detection. Before opening a VC, the user should write 00h into this field and then leave it for hardware control. The "S" bit (Structure un-initialized) serves to indicate that the structure has not been "run" yet. When the first cell of a VCC arrives at the MT90500, the RX_SAR control structure is called by the lookup table for the first time, and the 'S' bit is '0' as set by software. When the hardware loads the RX_SAR control structure from memory, and sees that bit-15 in the 6th word is '0' (S is 0), this first cell is written starting at the location of the Average Lead Pointer, which automatically sets up the buffer with average-lead of CDV tolerance. The "BS" field indicates the size of the Receive Circular Buffers. The valid size ranges from 64 to 1024 bytes and depends upon the amount of available memory and the cell delay variation (CDV) in the network. Note that all channels arriving on the same VC must have the same CDV and therefore their RX Circular Buffers will all be the same size. The "RX_SAR Write Pointer" is initialized to zero by software and used only by the hardware. Unlike the Transmit Control Structures, there is no difference in the configuration of the RX_SAR Control Structures for the various cell types. In fact, the only thing which differentiates the control structures for different AALs is the AS field. In particular, this field is set to "00" for CBR-AAL0 and CBR-AAL5 cells (because CBRAAL5 is really just a special case of CBR-AAL0), or "10" for AAL1. AAL1 cells which are carrying SRTS information are identified by an AS setting of "11". As with the Transmit Control Structures, all RX_SAR Control Structures must start on 16-byte boundaries and must never cross 256-byte boundaries. 4.4.2.2 RX_SAR Error Counter and Interrupt Sources The RX_SAR has three 16-bit error counters, and three error structure ID registers for error monitoring. When receiving a cell, any of the following errors can be detected: a write overrun error, a write underrun error, an AAL1 byte parity error, an AAL1 CRC error, a sequence number error, a P-byte parity error, or a P-byte out of range error. A counter and ID register are used to monitor each of the two write slip-type errors (3022h and 3020h for Underrun events; 3032h and 3030h for Overrun events). The other five types of errors share common counter (3012h) and event ID (3010h) registers. Five bits in the RX_SAR Control Register (3000h) allow the control software to choose which error events affect the count and ID registers. If more than one error count enable is active, the counter will add all occurrences of the various errors. The ID register points to the RX_SAR Control Structure which experienced the last recorded error. All of the errors should be selfexplanatory, except for the P-byte out of range error. This error occurs when the P-byte's value implies that a hyper-channel contains more channels than indicated by the RX_SAR Control Structure. NOTE that received cells with AAL1 errors (e.g. sequence numbers, AAL1-byte parity, AAL1-byte CRC, P-byte parity and P-byte CRC) are NOT discarded. The dropping of such cells is optional in the AF-VTOA-0078 CESIS V2.0 specification. The cell contents are passed to the AAL1 reassembly process on the basis that corruption of the AAL1-byte may or may not imply corruption of the TDM contents, and that TDM channels are generally relatively tolerant of noise, and that using these cells will help to maintain timing. 59 MT90500 4.4.2.3 Receive Overruns and Underruns The "First Entry" and "Last Entry" fields in the RX_SAR Control Structure point to the first and last RX Circular Buffer Base Address pointers in the RX_SAR Control Structure. The "Minimum Lead", "Maximum Lead", and "Average Lead" entries define the window within the circular buffer within which cell data can be received without generating an underrun or overrun condition. This window is defined relative to the TDM Circular Buffer Read Pointer, as described in Figure 23. Whenever data from a newly received cell is to be written to the Receive Circular Buffers, the location of the RX_SAR Write Pointer is checked against the Minimum and Maximum Lead Pointers. RECEIVE BUFFER TDM CIRC. BUFFER READ POINTER INVALID BYTE VALID BYTE VALID BYTE VALID BYTE VALID BYTE Min. Lead VALID BYTE VALID BYTE INVALID BYTE Avg. Lead INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE Max. Lead INVALID BYTE INVALID BYTE TDM CIRC. BUFFER READ POINTER RECEIVE BUFFER INVALID BYTE VALID BYTE VALID BYTE VALID BYTE VALID BYTE Min. Lead VALID BYTE VALID BYTE VALID BYTE Avg. Lead VALID BYTE VALID BYTE VALID BYTE VALID BYTE Max. Lead VALID BYTE INVALID BYTE TDM CIRC. BUFFER READ POINTER RX_SAR WRITE POINTER (OLD) RX_SAR WRITE POINTER (NEW) RECEIVE BUFFER INVALID BYTE VALID BYTE VALID BYTE VALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE INVALID BYTE Min. Lead RX_SAR WRITE POINTER RX_SAR WRITE POINTER (NEW) Max. Lead RX_SAR WRITE POINTER (OLD) Normal Overrun Underrun Figure 23 - Overrun and Underrun Situations When a new cell is received, the hardware checks for the location of the RX_SAR Write Pointer, which indicates where the new cell should be written within the associated Receive Circular Buffer(s). The VALID bytes shown in the figure above indicate bytes which have been written by the RX_SAR and have yet to be read by the External Memory to TDM Data Output Process. Consequently, INVALID bytes represent those that have already been read or, in the case of start-up, have never been written. If the pointer falls within the window defined by the Min. Lead and Max. Lead parameters, the new data is written immediately following the old data. If the RX_SAR Write Pointer falls after the Maximum Lead Pointer, an overrun condition is detected, and the new data is written starting at the location of the Average Lead Pointer. (Some addresses containing previously received, unread data bytes are overwritten.) If the RX_SAR Write Pointer falls before of the Minimum Lead Pointer, an underrun condition is detected, and the new data is written starting at the location of the Average Lead Pointer. (Some addresses containing already-read data bytes are "skipped" and left unwritten.) Figure 23 depicts the Write Pointer to Read Pointer comparison that occurs at cell receive time. The External Memory to TDM Data Output Process (Section 4.1.4) has its own TDM Read Underrun Error indication (see register 6000h) which works in parallel to the mechanism described above. The ninth bit of the external memory byte is not used for parity, but is used to indicate whether each TDM byte has been previously transferred to the TDM bus. When the External Memory to TDM Data Output Process reads a byte which has already been transferred (has the ninth bit set), an underrun condition is flagged, if enabled by that TDM channel's entry in the External Memory to Internal Memory Control Structure. Since this TDM Read Underrun Error functions as each byte is read (and not just when a cell arrives, as the RX_SAR errors do) it is useful to indicate dropped VCs (no cells), and excessive CDV (late cells). Data bytes which have been read out to the TDM bus by the External Memory to TDM Data Output Process are handled according to the programming of the External Memory to Internal Memory Control Structure. Depending on the value of the write-back disable bit for each individual TDM channel, bytes read out to the TDM bus will either be replaced by silence (FFh) or left unchanged. This has the effect that in the event of an underrun, either silence (FFh) will be read out of the "skipped" area, or the old data in the "skipped" area will be repeated on the TDM bus. 60 MT90500 Registers 3022h and 3032h are used to maintain statistics on the occurrence of RX_SAR underrun and overrun conditions. The last VC where an underrun or overrun condition was detected is also recorded in the event ID registers 3020h and 3030h. Note: Care must be taken when assigning the Maximum Lead value for small circular buffers: when the Maximum Lead is too far from the TDM Read Pointer, the reception of a cell could write new data over the data being read by the TDM module. This error can occur if {(Maximum Lead) + (# of Bytes in Cell)} > (Circular Buffer Size). 4.4.2.4 Lost Cell Handling In the event of a lost cell, the MT90500 maintains bit count integrity through buffer-fill level monitoring, rather than through sequence number processing (ITU-T Rec. I.363.1 terminology). Sequence numbers are however monitored, and errors are reported (registers 3000h and 3002h). In the event of an underflow (due to lost cells or excessive CDV) the buffers are reset to "Avg. Lead" for all TDM channels carried by a particular VC. In the event of a single cell loss: * * * * * * * RX_SAR Write Underrun will detect underrun if the CDV tolerance is depleted (3002h); TDM Read Underrun will detect underrun if Rx Circular Buffer is depleted (6002h); Sequence number error will be detected (3002h). In the event of loss of multiple consecutive cells: RX_SAR may detect Write Underrun or Write Overrun (dependent on number of cells lost, and Rx circular buffer size); TDM Read Underrun will detect underrun if Rx Circular Buffer is depleted; Sequence number error will be detected. In the event a VC gets disconnected: TDM Read Underrun will detect underrun (once Rx Circular Buffer is depleted). Note that the operation of the TDM Read Underrun Error bit requires that the TDM Read Underrun Detection Enable bit in the External to Internal Memory Control Structure be asserted (for the particular TDM channel in question) and 9-bit (parity) memory is used (36-bit rather than 32 bit external memory). In the event of a cell loss not large enough to trigger one of the underrun alarms, the TDM data is read as normal from the Rx Circular Buffer. This will "jump" the data from the lost cell, similar to a frame slip in TDM switches. In the event of a TDM Read Underrun Error, the TDM output depends on the state of the External Memory to Internal Memory Control Structure write-back disable bit, as explained in Section 4.4.2.2. If enough cells are lost on a particular VC, causing the TDM Circular Buffer Read Pointer to advance far enough to "wrap around", it is possible for the RX_SAR to mistakenly declare an overrun when a cell finally arrives. Using a larger circular buffer RAM allocation makes this less likely to occur, since the RAM is re-used at greater intervals. (The delay is not increased, as delay is controlled by Maximum Lead and Average Lead, not by the RAM allocation.) In any event, the TDM Read Underrun will correctly identify an underrun, even in situations of large numbers of lost cells. 61 MT90500 4.5 UTOPIA Module On the ATM transmit side, the MT90500 multiplexes ATM cells generated by the internal TX_SAR module with ATM cells coming from the Secondary UTOPIA Port. Cells coming from the Secondary UTOPIA Port may be generated by the optional external SAR device (e.g. AAL5 SAR) or another MT90500 device (see Figure 63, "UTOPIA Bus Interconnections for Two MT90500s and an AAL5 SAR," on page 139 for an application example). 4.5.1 UTOPIA Overview The UTOPIA module is used to daisy chain one or several SAR devices in order to use a single PHY device, as seen below in Figure 24. RX RX TX RX TX RX TX MT90500 Device ABR SAR Device TX ATM Network PHY Device MT90500 Device Figure 24 - MT90500 Daisy Chain Example In the transmit direction, the Secondary UTOPIA Port of the MT90500 emulates a PHY, receiving cells from other SAR devices on the bus. The MT90500 then forwards these cells to the actual PHY using the Primary UTOPIA bus. The transmit portion of the UTOPIA module multiplexes the cell traffic from the Secondary UTOPIA bus with the cell traffic from the MT90500's TX_SAR. A small internal FIFO is used to buffer up to four Secondary UTOPIA bus cells) and four TX_SAR cells. The TX_SAR and Secondary UTOPIA bus can have the same transmit priority, or the priority can be given to the TX_SAR (this is determined by the Round-Robin Priority bit in the UTOPIA Control Register at 4000h). No overruns are possible in the TX part of the UTOPIA interface since flow control (UTOPIA bus handshaking) is used. On the receive side, the MT90500 passively taps the Receive UTOPIA bus. Since the Receive UTOPIA bus is multi-drop, cells may be received by more than one device. This can be used for redundant transfer of data or timing. Cells can be received at the maximum transfer rate of the bus (up to 25 MHz). When a cell is received, its header is analyzed: the cell is either ignored, or stored in the Primary Receive FIFO. (Ignored cells are assumed to be destined for another device on the Receive UTOPIA bus.) The Primary Receive FIFO is internal to the MT90500, and can contain 32 cells. If the internal Primary Receive FIFO is full, the received cell is discarded, so it is important to use a master clock rate (MCLK) fast enough for the application. Further details on the cell reception process are given in Section 4.5.3. All cell transfers on both UTOPIA buses are performed using cell-level handshaking. See AF-PHY-0017 for more information regarding UTOPIA standards. For details on chaining UTOPIA devices, see Section 7, "Applications" of this datasheet. Details on configuring the PTXCLK pin are in the "Main Control Register," on page 84. 62 MT90500 . SECONDARY UTOPIA PORT DEVICE BOUNDARY FIFO FIFO PRIMARY UTOPIA PORT From TX_SAR TX MUX To/From Microprocessor I/F To RX_SAR FIFO RX FIFO & VC Search Engine To/From Memory Controller To / From TDM Module Figure 25 - Mux and Internal FIFO Sub-Module Block Diagram 4.5.2 Cell Transmission and Mux Process The general block diagram of the Mux and internal FIFO sub-module is shown above. The Mux sub-module's operation is relatively straight-forward. It multiplexes onto the Primary Transmit UTOPIA Port cells generated by the TX_SAR with cells received from the optional external SAR device. A number of register bits found at address 4000h control the operation of the sub-module: a general enable (RXENA); an external SAR interface enable (STXENA); and a mux arbitration method (RRP, which gives priority to the TX_SAR or allocates priority in round-robin fashion). 4.5.3 Receive Cell Selection Process The purpose of the Receive Cell Selection Process is to determine the routing of received ATM cells, which can include OAM cells, timing reference cells, CBR cells destined for the RX_SAR, and non-CBR data cells which will be routed to the Receive Data Cell FIFO. The steps involved in the Receive Cell Selection Process are detailed below and are outlined in the flow chart in Figure 26. The Receive Cell Selection Process is as follows: a) The most significant bit of the PTI field in the cell header is examined to determine if the cell is an OAM cell. If the received cell is an OAM cell, it is either sent to the 32-cell (2048-byte) internal Primary Receive FIFO, or discarded as determined by the OAM Routing Select bit, OAMSEL, in the UTOPIA Control Register at 4000h. OAM cells that are sent to this internal FIFO are then treated as non-CBR data cells and are eventually sent to the Receive Data Cell FIFO in external memory; see step (e). If the cell is not an OAM cell, step (b) is taken. b) Non-OAM cells are then passed through the MT90500's timing filter mechanism. The VPI and VCI values of the incoming cell are compared to the values found within the VPI Timing Register (401Ah) and the VCI Timing Register (401Ch). If the VC of the received cell matches the Timing Registers, a timing pulse is sent to the Clock Recovery Module, along with the AAL1 byte of the cell header (this process is explained in detail in Section 4.6.1, "Adaptive Clock Recovery Sub-Module"). Regardless of whether the cell matches the timing filter or not, the cell is sent to step (c) for further processing. 63 MT90500 c) The cell's VPI field (8 bits) is examined. A bit by bit comparison of the VPI is performed using the contents of both the VPI Match Register (4012h) and the VPI Mask Register (4014h). If a bit value in the VPI Mask Register is `0', no comparison is performed on the corresponding bit in the VPI Match Register (and the bit is automatically accepted). If a bit value in the VPI Mask Register is `1', the comparison result will only be true if the received VPI bit and the corresponding VPI Match Register bit are identical. The cell will only be processed further (i.e. proceed to step (d)) if each of the 8 bit comparisons produces true results. Otherwise, the cell will be discarded. d) The cell's VCI field (16 bits) is then examined. A bit by bit comparison of the VCI is performed using the contents of both the VCI Match Register (4016h) and the VCI Mask Register (4018h). If a bit value in the VCI Mask Register is `0', no comparison is performed on the corresponding bit in the VCI Match Register. If a bit value in the VCI Mask Register is `1', the comparison result will only be true if the received VCI bit and the corresponding VCI Match Register bit match. Step (e) will only be executed if each and every one of the 16 bit comparisons produces true results. Otherwise, the cell will be discarded. Note: The VPI/ VCI match and mask filter serves two important purposes. It can eliminate non-unique look-uptable entries (important as the look-up-table space is smaller than the entire VPI/VCI space of 16M addresses). It can also reduce the number of unnecessary look-up-table accesses (and unnecessary memory-access bandwidth) by eliminating cells with VPI/VCI not destined for the MT90500. The user is advised to set the VPI/ VCI match and mask filter as narrowly as practical for the application. e) Any cell which passes through both the VPI and VCI match filtering will be placed in the 32-cell FIFO of the UTOPIA module. Cells are then read out by another internal process. As mentioned in step (a) above, OAM cells which are located in the Primary Receive Queue are automatically placed into the Receive Data Cell FIFO. On the other hand, non-OAM cells are passed to the lookup engine of the UTOPIA module, as explained in step (f). (f) Within the look-up engine, the N least significant bits of the VCI and the M least significant bits of the VPI are concatenated together to form a 15-bit word. If M + N is smaller than 15, the missing most significant bits of the 15-bit word are zeroed. Two least significant zeroes are appended automatically (by H/W) to this word to form a 17-bit pointer aligned on a double-word boundary. Note: This is explained more fully in the register description for the VPI/VCI Concatenation Register at address 4010h. This pointer is added to the contents of the Look-up Table Base Address Register at address 401Eh to form a memory pointer into the VC Look-up Table, which is composed of 32-bit entries. The look-up engine then examines the "T" bits of each look-up table entry. These bits indicate the type of information being carried by a particular cell and therefore determine the final destination of the cell: * "00" indicates an undefined cell type. In this case, the cell is either discarded or treated as a nonCBR data cell which is placed in the Receive Data Cell FIFO. This final cell routing is dependent on the setting of the UKSEL (Unknown Routing Select) bit in the UTOPIA Control Register at 4000h. "01" represents a non-CBR data cell. In this case, the cell is stored in a 64-byte long structure within the Receive Data Cell FIFO (see Figure 29). "10" indicates a CBR cell. In this case, the RX Structure Address in the look-up table, (Figure 27) is used to access the RX_SAR Control Structure (see Figure 22 - RX_SAR Control Structure) to determine how to process the cell payload data. * * 64 MT90500 PHY (checks HEC) UTOPIA Interface Primary RX Port Incoming Cell YES OAM Cell? NO `0' OAMSEL `1' Timing Match VPI and VCI Timing No Timing Match Cell Discarded Send Timing Pulse and AAL1 Byte to Clock Recovery Module VPI/VCI Match VPI and VCI Match and Mask No Match 32-cell internal UTOPIA FIFO Cell Discarded YES OAM Cell? NO OAM Data Cell placed in RX Data Cell FIFO "10" (CBR traffic) Lookup Table T-Bits "01" (non-CBR data) Use RX_SAR Control Structure Address in Look-up Table "00"(undefined) Data Cell placed in RX Data Cell FIFO `0' UKSEL `1' Cell Discarded Unknown Data Cell placed in RX Data Cell FIFO Figure 26 - Receive Cell Selection Process 65 MT90500 VC Lookup Table 31 LUTBASE + "00000" RX Structure Address RX Structure Address 18 16 15 T T R R 2 0 RR RR R = Reserved (should be set to all zeroes) T = Entry Type (00 = inactive/undefined; 01 = non-CBR data; 10 = CBR; 11 = Reserved) VPI (M bits) VCI (N bits) 00 RX Structure Address T R RR (LUTBASE + "00000") + VPVCC RX_SAR Control Structure 18 17 43 20 0 RXBASE RX Structure Address 0000 (from 4000) 15 +00 +02 +04 +06 +08 +0A S First Entry Minimum Lead Average Lead Reserved Current Entry BS R 0 AS 87 0 Last Entry Maximum Lead Payload Size Reserved AAL1 Byte 0 0 RX_SAR Write Pointer RX Circular Buffer Base Address RX Circular Buffer Base Address +0C V +0E V +10 V RX Circular Buffer Base Address +FC V +FE V RX Circular Buffer Base Address RX Circular Buffer Base Address RX Circular Buffer 20 RX Circular Buffer Base Address 12 OR 20 RX Circular Buffer Write Address RX_SAR Write Pointer 0 Data Byte Data Byte 65 000000 0 0 7 Data Byte Data Byte 0 Figure 27 - MT90500 Cell Receive Process 66 MT90500 4.5.4 Non-CBR Data Cell Reception Ability As mentioned above, the MT90500 is capable of receiving non-CBR data cells as well as CBR cells. Non-CBR cells can be received on the UTOPIA bus and written into the user-defined Receive Data Cell FIFO in external memory, where they wait for the CPU to read them. There are 3 ways for cells to be identified as data cells. First of all, OAM cells may be treated as non-CBR cells if the OAM Routing Select bit in the UTOPIA Control Register (address 4000h, bit<5>) is set to 1. Secondly, unknown cells may be considered as non-CBR cells if the Unknown Routing Select bit (bit<6> of the UTOPIA Control Register) is set to 1. Finally, normal cells whose VPI and VCI values correspond to those in the VPI and VCI Match Registers located at 4012h and 4016h respectively, can be tagged as data if their entry in the lookup table is associated with a non-CBR entry. 31 (LUTBASE + "00000") + VPVCC 18 16 15 01 R 2 0 RR RX Structure Address (can be ignored) T = "01" indicates a non-CBR data cell T = Entry Type (refer to Figure 27, "MT90500 Cell Receive Process," on page 66 for details for non-data cells) R = Reserved (should be set to all zeroes) Figure 28 - Look-up Table Non-CBR Data Entry To write into the Receive Data Cell FIFO, the chip will use the Receive Data Cell FIFO Base Address Register (address 4020h) and will write into the next available entry as tagged by the Receive Data Cell FIFO Write Pointer Register (address 4022h), regardless of the value in the RX Structure Address field of the look-up table entry. Once this is done, the write pointer will be incremented. Finally, the CPU should read the data contained in the FIFO once the write pointer becomes greater than the read pointer. To do so, the CPU should access each of the 24 word entries corresponding to that cell (24 words * 2 bytes = 48 bytes, max. cell payload). Once it has completed its task, the read pointer should be incremented to ensure the hardware knows the cell has been read. 67 MT90500 15 GFC or VPI(11:8) 87 VPI(7:0) VCI(11:0) Data Byte #0 Data Byte #2 0 VCI(15:12) PTI, etc. Data Byte #1 Data Byte #3 +00 +02 +04 +06 +30 +32 +34 +36 +38 +3A +3C +3E Data Byte #44 Data Byte #46 Reserved Reserved Reserved Reserved Reserved Reserved Data Byte #45 Data Byte #47 Reserved Reserved Reserved Reserved Reserved Reserved Figure 29 - Received Non-CBR Data Cell Internal Format Should the CPU not read the appropriate data cells or should a huge concentration of non-CBR cells arrive consecutively on the Primary UTOPIA Port, a Receive Data Cell FIFO Overrun will occur. This error, indicated by bit<10> of the UTOPIA Status Register (address 4002h), indicates that the oldest data cell in the FIFO has been over-written due to lack of space for valid cells. Should this occur, the CPU will have to read the non-CBR cells faster or, conversely, the Receive Data Cell FIFO size should be increased. 68 MT90500 VC Look-up Table External Synchronous SRAM Determines which VCs are controlled by which RX_SAR Control Structures ** RX Circular Buffers - one for each TDM channel being received RX_SAR Control Structures one for each VC Dictate received data to be sent to specific RX Circular Buffers * ** * Directs data from Circular Buffers to TDM channels External Memory to Internal Memory Control Structure MT90500 UTOPIA Module RX UTOPIA BLOCK, including OAM and VPI/VCI Filtering Receive Cell Selection Process (see Figure 26 on page 65) Internal TDM Frame Buffer TDM Bus 16 lines 1024 x 64kbps (max.) Local TDM Bus 32 x 64 kbps in / 32 x 64 kbps out Clock Signals TDM Module TDM Bus Interface Logic TDM Clock Logic From External PHY Main UTOPIA Interface 32-cell Primary Receive Queue Clock Recovery Figure 30 - Overview of CBR Data Reception Process 69 MT90500 4.6 4.6.1 Clock Recovery from ATM Link Adaptive Clock Recovery Sub-Module Adaptive Clock Recovery is a flexible method for TDM clock recovery from an ATM link. There are several approaches to adaptive clock recovery, and the standards do not require a specific one, so adaptive clock recovery is termed "non-standardized." The implementation given here is similar to the general outline in ITU-T I.363.1. In the MT90500, adaptive clock recovery uses a reference 8 kHz clock to generate the TDM clock signals. The TDM clocks are controlled by adjusting the reference 8 kHz clock frequency according to the arrival rate of ATM cells on a designated VC. As seen in Figure 31, the reception rate of timing reference cells or 8 kHz markers (EX_8KA) is used as the basis for the adaptive clock recovery scheme implemented by this sub-module. This block is responsible for generating (under software control) a reference clock signal (RXVCLK) based on the rate of reception of the timing reference cells or markers. The sub-module additionally implements a state machine (seen in Figure 32) which tracks the cell arrival rate, checks the cell sequence numbers for lost or misinserted cells or cells with bad SNP fields (to a maximum of one), and adjusts for discrepancies. Cell / 8 kHz Timing Reference Cell Processing designated timing VC new_cell 0 Event Counter Event Count Register (60A2h) EX_8KA EX_8KA CLKx1 1 Temp Register CLKx1 Count Registers (60A4h and 60A6h) DIV 8 Counter CNTUPDATE MCLK DIVX Register (60A8h) RXVCLK REF8KCLK DIVX Ratio Register (60AAh) REFSEL<1:0> = 01 MT90500 CLKx1 CLKx2 External PLL 8 kHz Figure 31 - Adaptive Clock Recovery Sub-Module (Simplified Functional Block Diagram) The Adaptive Clock Recovery Block consists of: * a Timing Reference Cell Processing unit which generates an event ("new_cell") every time a timing reference cell is received. A timing reference cell is defined as an AAL1 cell whose VPI/VCI matches that specified in the VPI Timing Register (401Ah) and the VCI Timing Register (401Ch). OAM cells on the specified VPI/VCI are ignored, as they do not carry CBR data. The unit can compensate for a single lost or misinserted cell or bad sequence number protection (SNP). It will also flag an out-of-sync error when more than one cell is lost, misinserted, or received with corrupted sequence number protection. SNP-checking is enabled by setting the Seq_CRC_Ena bit in the Timing Reference Processing Control Register at 60A0h. If no timing reference cell is received within a certain period (user-definable by setting bits<9:0> in the same register), it will generate a loss of timing reference cell error. The state machine for this unit is shown in Figure 32: 70 MT90500 OUT_OF_ SYNC any consecutive error out of sequence (except 2nd next) next sequence out of sync (any consecutive error) Bad SNP BAD_SNP next sequence (good SNP) IN_SYNC 2nd next sequence LOST_CELL next sequence previous sequence next sequence - When going to In_Sync or Bad SNP state, generate one timing reference pulse for each timing cell received. ("Bad SNP" is bad Sequence Number Protection, meaning a bad CRC, or a bad parity bit.) - When going to Lost Cell state, generate two timing reference pulses. - When coming back to In_Sync state from Lost Cell state, generate one pulse if "next sequence" received. Do not generate pulse if "previous sequence" received, indicating an inverse-ordered cell condition. - When in Out_of_Sync state, do not generate timing pulses. If OUT_SYNC_IE bit is set at 6080h, and TIM_INTE is set at 0000h, an interrupt will be generated on entering Out_Of_Sync. - If no timing reference cells or markers have been received within the time-out period set in the Timing Reference Processing Control Register (60A0h), a Loss of Timing Reference Cells event will be indicated (LOSS_TIMRF in 6082h), and an interrupt will be generated if LOSSCIE is set at 6080h (and TIM_INTE is set at 0000h). Figure 32 - Timing Reference Cell Processing State Machine * * the Event Counter, which keeps a running count of the timing reference cells or 8 kHz markers received. The Cell/8 kHz bit in the Timing Reference Processing Control Register (address 60A0h) is used to select whether clock recovery is based on Timing Reference Cell arrival events, or 8 kHz marker events. The Event Count Register (60A2h) is updated every time the CNTUPDATE bit is set HIGH in the Clock Module General Control Register at 6080h. a counter which is incremented every eight cycles of CLKx1. The output of this counter is sent to the Temp Register, which is updated every time the Event Counter is incremented. Finally, the CLKx1 Count Registers (60A4h and 60A6h) are updated every time the CNTUPDATE bit is set HIGH in the Clock Module General Control Register at 6080h. The RXVCLK Clock Generation Block is composed of: * * a programmable divider (DIVX Register at address 60A8h) which divides the master IC clock (MCLK) in order to obtain RXVCLK. a division factor register (DIVX Ratio Register at address 60AAh) which controls the ratio of divide-by-X to divide-by-(X+1). Together, the Adaptive Clock Recovery Block and the RXVCLK Clock Generation Block allow the CPU to implement an adaptive algorithm which permits the locally generated TDM clock to track the remotely generated TDM clock. 71 MT90500 The adaptive clock recovery method operates on a single receive VC which is defined by the VCI Timing Register and the VPI Timing Register. The clock recovery method is, briefly, as follows: * * * Every (CLKx1 * 8) clock period, counter 1 (CLKx1 Counter) is incremented. Every time an 8 kHz marker or a cell with the Timing Recovery ID is received, counter 2 (Event Counter) is incremented. As well, the CLKx1 Counter value is latched to the Temp Register. Periodically, the processor writes the CNTUPDATE bit in Clock Module General Control Register (6080h) and reads both counters to determine if the local clock needs to be sped up or slowed down with respect to the remote clock. The local clock (RXVCLK) frequency is then adjusted by controlling the contents of the DIVX (60A8h) and DIVX Ratio (60AAh) Registers. * Please refer to the MT90500 Programmers' Manual for an example of an Adaptive Clock Recovery algorithm. 4.6.2 SRTS Clock Recovery Description The Synchronous Residual Time Stamp (SRTS) method of clock recovery is standardized in ITU-T I.363.1 and ANSI T1.630. This section outlines the operation of the MT90500 during transmit SRTS generation and receive SRTS clock recovery. Note that SRTS may be used in different applications than Adaptive Clock Recovery because SRTS produces a clock which better meets public network specifications for jitter and wander, but requires a common (synchronous) ATM physical layer reference clock at both ends. Please refer to MSAN-171 - "TDM Clock Recovery from CBR-over-ATM Links Using the MT90500" for applications of Synchronous Residual Time Stamp clocking. Please note that Mitel has entered into an agreement with Bellcore with respect to Bellcore's U.S. Patent No. 5,260,978 and Mitel's manufacture and sale of products containing the SRTS function. However the purchase of this product does not grant the purchaser any rights under U.S. Patent No. 5,260,978. Use of this product or its resale as a component of another product may require a license under the patent which is available from Bell Communications Research, Inc., 445 South Street, Morristown, New Jersey 07960. Since all of the TDM data streams on the MT90500 serial bus are synchronized to a single clock and frame pulse, the SRTS clock recovery module generates a single clock, from a single source VC. Although the MT90500 may receive several CBR VCs from various sources, the serial bus clocks can be locked only to one of the incoming VCs. Similarly, only one specific VC is selected to transmit the SRTS information from the MT90500 device. The `AS' (AAL Type) fields within the Transmit Control Structure (see Figure 16) and the RX_SAR Control Structure (refer to Figure 22) are used to designate the particular transmit and receive VCs that will carry the SRTS information. Note that only AAL1-type cells can be used to transmit SRTS data as the CSI bit in the AAL1 header byte is used to carry the information. 4.6.2.1 Transmit SRTS Operation In the transmit SRTS operation, the MT90500 compares the local service clock (derived from CLKx1) to a divided-down version of the network clock (available at the FNXI input pin). The SRTS method uses a stream of residual time stamps (RTS) to communicate the difference between a common reference clock (fnx, derived from the network) and a local service clock (fS, derived from the local TDM clock). If the same ATM physical layer reference clock is available at both the origin and destination points (e.g. two different MT90500s), the service clock can be recovered at the destination using the common reference clock, the transmitted (remote) RTS, and a locally-generated RTS. Within the MT90500 SRTS module, the RTS service clock is derived from the TDM clock signals. The CLKx1 main TDM bus clock is used to obtain a clock, fB, which represents the TDM byte frequency of the SRTS transmit VC. fB is equal to N * 8 kHz, where N is the number of TDM input channels in the VC which is selected for SRTS transmission (fB is one-eighth of the service clock, fs). To generate fB, N pulses are spaced more or less evenly within the 125 s period defined by the input signal FSYNC. The number of pulses per period and their spacing are determined by the settings within the SRTS Transmit Gapping Divider Register at address 60B0h. For instance, if there are 64 channels in the SRTS VC, N = 64, and the resulting byte rate, fB, is 512 kHz (TB = 125 s / 64). In order to implement this configuration, the register at 60B0h should be set as follows: TX_Ch_per_VC = 3Fh while the TX_Gapping field is set to 3h. (Please refer to "SRTS Transmit Gapping Divider Register," on page 109 for configuration details.) 72 MT90500 SRTS Transmit Divider Register period of the RTS (one 8-cell cycle) MULTIPLE clk LATCHES data_in RTS 4 enable TX_SAR BLOCK Transmit ATM Cells w/ CSI bits CLKx1 Gapping Control fB fB Generator Byte Counter fB = fS / 8 = service byte clock 4 ATM Physical Layer Network Clock Divide by x FNXI fnx 4-bit counter Internal to MT90500 Figure 33 - Transmit SRTS Operation A 4-bit RTS value is generated once every "period of the RTS" (TN). Since one RTS value is carried by the CSI bits in each 8-cell sequence, the "period of the RTS" is the assembly time of 8 cells on the designated SRTS VC. The SRTS Transmit Byte Counter Register at 60B2h contains the number of payload bytes within an 8-cell sequence of the SRTS VC. The value in this register is used to divide the byte frequency fB to obtain the "period of the RTS". For pointerless AAL1 Structured Data Transfer, the number of bytes necessary to fill 8 cells is 376 (8 cells @ 47 bytes per cell). In Nx64 AAL1 SDT, the number of bytes required to fill 8 cells varies depending on the number of P-bytes sent within an 8-cell sequence, but it is generally set to 375 bytes (1 cell of 46 TDM payload bytes plus 7 cells of 47 TDM payload bytes). The SRTS Transmit Divider Register shown in Figure 33 generates a latch pulse which captures the value of a free-running counter clocked by the external signal fnx (the network reference clock, input at the FNXI pin). The latched value is the four-bit residual time stamp. Multiple latches (a 5-deep FIFO) are used to synchronize this clocking block with cell transmission (controlled by the transmit event schedulers). In order for the SRTS clock recovery method to operate correctly, the divided-down network clock, FNXI, must be properly derived. As stated in I.363.1: "For SDH and non-SDH physical layers, a clock at frequency f8 = 8 kHz, synchronized to a common network clock, is available from which clocks at frequencies fnx = f8 x (19440 / 2k) kHz, where k = 0,1,2,...,12 can be derived. This set of derived frequencies can accommodate all service rates from 64 kbps up to the full capacity of the STM-1 payload. The exact value of fnx to be used is uniquely specified since the frequency ratio is constrained by 1 fnx/fs < 2." For example, to support N = 24 (fS = 1.536 MHz) or N = 32 (fS = 2.048 MHz), the derived network frequency will be 2.430 MHz (8000 * 19440 / 26). To support N = 1 (fS = 64 kbps), the derived network frequency will be 75.9375 kHz (8000 * 19440 / 211). In compliance with I.363.1, the MT90500 transmits the 4-bit RTS values in the serial bit stream provided by the CSI bits of successive odd-sequence-numbered SAR-PDU headers (the even-numbered CSI bits are available for other uses such as SDT pointers). The modulo-8 sequence count provides a frame structure over 8 bits in this serial bit stream. The MSB of the RTS is placed in the CSI bit of the SAR-PDU header with a sequence count of 1. Due to the internal hardware design of the MT90500, the frequency of FNXI must be < MCLK / 3. This places no restrictions on the SRTS VC as long as MCLK is greater than 30 MHz. Since the maximum structure size is 122 channels, the maximum value of fS = 7.808 MHz, and the maximum value of fnx is 9.72 MHz. 73 MT90500 Receive ATM Cells w/ CSI bits RX_SRTS 4 RX_SAR BLOCK Comparator enable SRTSENA SRTSDATA period of the RTS (one 8-cell cycle) SRTS Receive Divider Register CLKx1 Gapping Control fB fB Generator Byte Counter clk MULTIPLE LATCHES data_in 4 enable EXPECTED_ SRTS 4 fB = fS / 8 = service byte clock ATM Physical Layer Network Clock Divide by x FNXI fnx 4-bit counter Internal to MT90500 Figure 34 - Receive SRTS Operation 4.6.2.2 Receive SRTS Operation Note: The following specification assumes that the MT90500 will perform the SRTS function with the use of external logic as depicted in Figure 35 and Figure 36. On the receive side, the MT90500 will generate a local RTS value (EXPECTED_SRTS) as depicted in Figure 34 (and in a manner identical to that explained in detail in Section 4.6.2.1 for the transmit direction), and will compare it with the received RTS code (RX_SRTS) from the incoming ATM stream. Up to five locallygenerated RTS values can be stored in a series of internal latches (a 5-deep FIFO). The MT90500 internal comparator generates a 4-bit complement code that indicates the difference between the locally generated RTS value and the incoming RTS value (remote - local). The value of this code ranges from -8 (1000) to +7 (0111). The result of the comparison is then sent out via the SRTSDATA pin, with an associated strobe output transmitted on SRTSENA. External user logic is necessary to monitor these difference values, perform the clock adjustment and recover the original ST-BUS clock. If the difference values increase, it is due to the fact that the remote bus is running faster than the local bus and therefore the local bus frequency must be increased. Likewise, if the difference values are decreasing, it is because the remote bus is running more slowly than the local bus, and thus the local bus must be slowed down. Two 5-deep FIFOs are used to minimize the effect of cell delay variation in the transmission and reception process and to minimize slips. For both the receive SRTS and the transmit SRTS processes, the FIFOs are self-aligning: if an underrun or overrun is encountered, the FIFOs' pointers are re-centered. These errors are reported in the Clock Module General Status Register at 6082h. 74 MT90500 ATM PHY DEVICE Divide by x Network Reference Clock UTOPIA interface TDM Port (MVIP, ST-BUS, SCSA) MT90500 DEVICE PLLCLK CLKx1 FSYNC CORSIGB CORSIGD CORSIGC SRTSDATA EX_8KA FNXI REF8KCLK PLL e.g. MT9041 SRTSENA EXTERNAL LOCAL REFERENCE TIMING GENERATION CIRCUIT (Small FPGA) Note 1: In ATM receive applications, SRTSDATA corresponds to the 4-bit SRTS calculated as the difference between the locally-generated RTS code and the remotely-generated RTS code received from the incoming ATM cell stream. Note 2: The external timing generation logic generates an 8 kHz output reference clock. This signal is fed from the FPGA into the EX_8KA input of the MT90500 to be routed back to the external PLL. Note 3: The external reference timing generation logic can be implemented in a small FPGA. Figure 35 - Clock Recovery Using SRTS Method (Hardware) . 75 MT90500 ATM PHY DEVICE Divide by x Network Reference Clock UTOPIA interface TDM Port (MVIP, ST-BUS, SCSA) MT90500 DEVICE CORSIGB PLLCLK FNXI PLL e.g. MT9041 CLKx1 FSYNC REF8KCLK CORSIGD CORSIGC SRTSDATA External Data Latch/Buffer (Small FPGA) SRTSENA Modified DIVX and DIVX Ratio values CPU Running SRTS S/W Algorithm Note 1: In ATM receive applications, SRTSDATA corresponds to the 4-bit difference calculated between the locally-generated RTS code and the remotely-generated RTS code received from the incoming ATM cell stream. Note 2: The external circuit within the FPGA provides access to the SRTSDATA values in a parallel format (i.e. stored in a register). Note 3: The CPU then accesses the SRTS values stored within the FPGA. A software algorithm is used to determine if the local clock is too fast or too slow relative to the remote clock. Based on this algorithm, the DIVX and DIVX Ratio Registers are modified (as in Adaptive Clock Recovery). Using the new settings in these registers, the MT90500 generates an 8 kHz output reference clock from REF8KCLK. This signal is routed from the MT90500 to . the external PLL. Figure 36 - Clock Recovery Using SRTS Method (CPU) 76 MT90500 4.7 4.7.1 Microprocessor Interface General This interface allows an external control device (microprocessor) to configure and confirm the status of the MT90500 via access to internal control and status registers and access to the external device memories. It supports a variety of software maskable interrupt services. The CPU interface allows external microprocessors to program the MT90500 and its external memory. The interface supports word (16-bit) data accesses only. The AEM pin determines if the access is to internal registers (`0'), or to external memory (`1'). The CPU module features internal registers that are used to control and monitor the operation of the MT90500. See Main Control Register (0000h) and Main Status Register (0002h) in Section 5.2. Detailed timing diagrams for the microprocessor interface are shown in Section 6.2.3, "CPU Interface Accessing Registers and External Memory". 4.7.2 A Programming Example - How to Set Up a VC The basic sequence for initializing a connection at the MT90500 can be summarized in 5 functional steps. In outlining the basic steps, we consider the need to allocate an ATM Virtual Circuit to one or more 64 kbps channels present at the ST-BUS interface (ST[15:0]). In this particular scenario, we focus on a channel to be received from the ST-BUS interface and sent out at the ATM interface (i.e. the transmit process). A similar procedure (albeit in the reverse order) will have to be repeated for the case whereby an ATM VC is received and transferred to the associated 64 kbps channel at the ST-BUS interface (i.e. the receive process). 1 - The CPU identifies which 64 kbps time slot(s) or N x 64 kbps grouped channel(s) must be selected on the ST-BUS backplane. The identification of the selected channels is done via a command from the driver managing the device. 2 - The CPU identifies which of the Transmit Circular Buffers are available to receive the 64 kbps time slots from the ST-BUS interface. The number of circular buffers available will depend on the number of time slots and the data rate selected at the ST-BUS backplane interface (256 time slots @ 2.048 Mbps, 512 time slots @ 4.096 Mbps or 1024 time slots @ 8.192 Mbps). 3 - Once the selection of the circular buffers is made, the CPU maps the time slots to be serviced and therefore to be transferred to the external circular buffers. This is performed via programmable pointers in the Transmit Circular Buffer Control Structure, located in external memory. 4 - The CPU starts filling the Transmit Control Structure(s). This information is programmed in external memory and identifies (in summary) the ATM cell header bytes, the circular buffer address(es) from which the device will take the time slots and assemble cells, and whether or not this is a partially-filled cell. 5 - Once the ATM cell structure for a particular VC is complete, the CPU can program the scheduler, which basically tells the MT90500 how many and which tasks must be executed every 125 s. If multiple ATM Virtual Circuits have to be opened simultaneously, the CPU can execute items 1 to 4 taking into consideration all the TDM channels being treated. However, item 5 can be optimized to provide some fairness in the general TX_SAR engine so that the device can perform up to 1024 specific ATM VC cell assembly functions using minimal memory and processing time requirements. The details of that operation, as well as specific VC setup examples, are provided in the MT90500 Programmers' Manual. 77 MT90500 4.7.3 Microprocessor Access and Device Reset Upon hardware reset (using the RESET pin) of the MT90500, the microprocessor registers go to their respective reset states, as indicated in the register descriptions. Further, the SRES bit in Register 0000h is set LOW, "latching" the reset state. No registers other than the Microprocessor Interface Registers can (nor should) be accessed until the SRES bit is set HIGH. Steps to reset and restart the MT90500 are therefore: 1. Assert hardware RESET (and optionally TRISTATE), or write register 0000h to 0000h. 2. Remove hardware reset. 3. Allow at least 75 MCLK clock cycles (about 2 sec at 60 MHz). 4. Write register 0000h to 4400h (enable normal internal clocks). 5. Write register 0000h to C400h (de-assert SRES). 6. Write register 0000h to desired functional setting. 7. Write other MT90500 registers. (Note that configuration bits must generally be programmed before setting process enable bits.) 4.8 Test Interface The MT90500 contains an IEEE 1149 standard Test Access Port (TAP), which provides Boundary-Scan test access to aid board-level testing. (IEEE 1149 is often referred to by its older designation: JTAG - Joint Test Action Group.) 4.8.1 Test Access Port The test port is a standard IEEE 1149 interface, with the optional TRST pin. The Test Access Port consists of 5 pins: TCLK: Boundary-scan Test Clock. TDI: Test Data In; input pin clocked in on the rising edge of TCK. TDI should be pulled HIGH if boundary-scan is not in use. TDO: Test Data Out; output pin updated on the falling edge of TCK. The output is in high-impedance except when data is actually being shifted out. TMS: Test Mode Select; input control line clocked in on the rising edge of TCK. TMS should be pulled HIGH if boundary-scan is not in use. TRST: Test Reset; asynchronous, active-low, input which is used to reset the JTAG interface, and the TAP controller. The TRST pin has an internal pull-down, and should also be pulled LOW externally whenever boundary-scan is not in use, to ensure normal operation of the MT90500. Figure 37 below shows a typical board-level design, including how TRST can be pulled HIGH by the test connector in cases where the tester does not provide a TRST pin. 78 MT90500 Board-Under-Test JTAG Tester Signals TCLK TDI TDO TMS GND JTAG Test Connector TCLK TDI TDO TMS TRST MT90500 Figure 37 - A Typical JTAG Test Connection 4.8.2 JTAG ID Version<31:28>: Part Number<27:12>: LSB<0>: 0000 0000 0101 0000 0000 = 0500h 1 The JTAG device ID for the MT90500 is 0050014Bh: Manufacturer ID<11:1>: 0001 0100 101 4.8.3 Boundary Scan Instructions The TAP Controller of the MT90500 supports the following instructions: IDCODE, SAMPLE, BYPASS, EXTEST, HIGHZ, CLAMP, and INTEST. 4.8.4 BSDL A BSDL (Boundary Scan Description Language) file is available from Mitel Semiconductor to aid in the use of the IEEE 1149 test interface. 79 MT90500 5. 5.1 5.1.1 Register Map Register Overview General This section describes the registers contained within the MT90500. The MT90500 is mapped over 128 Kbytes of address space, which is divided into two halves by the state of the AEM input pin. The division of the addressing allows the user to access either the internal registers associated with the different internal blocks, or to access the external SSRAM containing the circular buffers and associated control structures. The first 64 Kbytes of address space are allocated for internal use, and are accessed by setting the AEM input pin low. As shown in Table 11 on page 82, the MT90500 does not implement all of the 64 Kbytes available inside the chip. The unused address space is reserved for future functionality. The internal registers are used for control and status of: * * * * * * Microprocessor Interface TX_SAR RX_SAR UTOPIA module and interface TDM Interface and clock recovery TDM time slot control. The second 64 Kbytes of address space are allocated as a window to external memory, accessed by setting the AEM input pin high. This window is used by the CPU to access up to 2048 Kbytes of external SRAM. The five latched address bits (EXTMADD[20:16] located at 0030h), provide access to 32 pages (each 64 Kbytes long) of external memory. All microprocessor accesses are 16-bit (word) accesses; byte access is not supported. Note that addresses are however expressed as byte addresses. The least-significant-bit of the address bus is the A1 pin, sufficient to distinguish between 16-bit words. All register addresses and reset values are listed in hexadecimal (Hex) format. The register types are: * * Read / Write (R/W) - can be read or written via the microprocessor interface. Read Only Latched (R/O/L) - these bits are set by an activated status point within the chip; once set, they remain set even if the status point is deactivated. The microprocessor can read this point and clear it by writing a logic `1' into it. The register is cleared if the status point is not active. Writing logic `0' has no effect on this register. Read Only (R/O) - can be read via the microprocessor interface. A write to this register is ignored by the chip. Write Only (W/O) - certain bits associated with AAL5 operation which must be written high, but which read back low. * * 80 MT90500 5.1.2 Interrupt Structure The MT90500 uses a two-level interrupt structure, as shown in Figure 38. For each of five major modules (TX_SAR, RX_SAR, UTOPIA, TDM Interface and TDM Clock) there is a Status register containing one or more status bits, and a Control register containing corresponding mask bits (interrupt enable bits). There is also a Main Status Register, and a Main Control Register. For an interrupt to be asserted at the INT pin, the following three conditions must be met: a status bit in one of the five module Status Registers must be asserted by an alarm event; the mask bit for that alarm event must be set in that modules Control Register; and the mask bit for that module must be set in the Main Control Register. Similarly, an interrupt event at the INT pin can be traced back to its source by reading the Main Status Register to identify the module which is the source of the alarm, and then reading that module's Status Register to identify the particular alarm source. The interrupt can then be cleared by writing a `1' over the status bit. One for each major module Status Register Main Status Register Status Bits . . . . . . . . . . . . . . . INT Control Register Status Mask Bits Main Control Register . . . . . . Figure 38. MT90500 Interrupt Structure 81 MT90500 5.1.3 Register Summary Table 11 - Register Summary Address Hex Label Reset Value Description Microprocessor Interface Registers 0000 0002 0010 0012 0030 0032 0034 0036 0040 MCR MSR Reserved Reserved WTEMC Reserved Reserved RDPAR MEMCNF 0000 00X0 0000 0001 0000 0000 0000 0000 0008 Main Control Register Main Status Register Reserved - DO NOT WRITE Reserved - DO NOT WRITE Window to External Memory Register - CPU Reserved - DO NOT WRITE Reserved - DO NOT WRITE Read Parity Register Memory Configuration Register TX_SAR Registers 2000 2002 2010 2012 2014 2020 2022 2024 2030 2032 2034 2040 2050 2052 2054 TXSC TXSS TESBAA TESFEA TESERA TESBAB TESFEB TESERB TESBAC TESFEC TESERC TXCSBA TXDFBA TXDFWP TXDFRP 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TX_SAR Control Register TX_SAR Status Register TX_SAR Scheduler Base Register - Scheduler A TX_SAR Frame End Register - Scheduler A TX_SAR End Ratio Register - Scheduler A TX_SAR Scheduler Base Register - Scheduler B TX_SAR Frame End Register - Scheduler B TX_SAR End Ratio Register - Scheduler B TX_SAR Scheduler Base Register - Scheduler C TX_SAR Frame End Register - Scheduler C TX_SAR End Ratio Register - Scheduler C TX_SAR Control Structure Base Address Register Transmit Data Cell FIFO Base Address Register Transmit Data Cell FIFO Write Pointer Register Transmit Data Cell FIFO Read Pointer Register RX_SAR Registers 3000 3002 3010 3012 3020 3022 3030 3032 RXSCR RXSSR RXMEID RXMECT RXUEID RXUECT RXOEID RXOECT 0000 0000 0000 0000 0000 0000 0000 0000 RX_SAR Control Register RX_SAR Status Register RX_SAR Misc. Event ID Register RX_SAR Misc. Event Counter Register RX_SAR Underrun Event ID Register RX_SAR Underrun Event Counter Register RX_SAR Overrun Event ID Register RX_SAR Overrun Event Counter Register UTOPIA Registers 4000 4002 4010 4012 4014 4016 4018 401A UCR USR VPVCC VPMT VPMS VCMT VCMS VPITIM 0000 0000 0000 0000 0000 0000 0000 0000 UTOPIA Control Register UTOPIA Status Register VPI / VCI Concatenation Register VPI Match Register VPI Mask Register VCI Match Register VCI Mask Register VPI Timing Register 82 MT90500 Table 11 - Register Summary Address Hex 401C 401E 4020 4022 4024 Label VCITIM LUTBA RXDFBA RXDFWP RXDFRP Reset Value 0000 0000 0000 0000 0000 VCI Timing Register Look-up Table Base Address Register Receive Data Cell FIFO Base Address Register Receive Data Cell FIFO Write Pointer Register Receive Data Cell FIFO Read Pointer Register Description TDM Interface and Clock Interface Registers 6000 6002 6004 6010 6020 6022 6024 6040 6042 6044 6046 6048 6080 6082 6090 6092 60A0 60A2 60A4 60A6 60A8 60AA 60B0 60B2 60B4 60B6 TDMCNT TIS CORSIG TDMTYP LBTYP TDMLOC LOCTDM TXCBCS EMIM TXCBBA RXUNDA RXUNDC CMGCR CMGSR MCGCR MCDF TRPCR EVCR C1CRL C1CRH DIVX DIVXR SRTGD SRTBC SRRGD SRRBC 0000 XX00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00C0 2000 0001 0000 0000 0000 2000 0FFF 0000 0177 0000 0177 TDM Interface Control Register TDM Interface Status Register TDM I/O Register TDM Bus Type Register Local Bus Type Register TDM Bus to Local Bus Transfer Register Local Bus to TDM Bus Transfer Register TX Circular Buffer Control Structure Base Register External to Internal Memory Control Structure Base Register TX Circular Buffer Base Address Register TDM Read Underrun Address Register TDM Read Underrun Count Register Clock Module General Control Register Clock Module General Status Register Master Clock Generation Control Register Master Clock / CLKx2 Division Factor Timing Reference Processing Control Register Event Count Register CLKx1 Count - Low Register CLKx1 Count - High Register DIVX Register DIVX Ratio Register SRTS Transmit Gapping Divider Register SRTS Transmit Byte Counter Register SRTS Receive Gapping Divider Register SRTS Receive Byte Counter Register TDM Time Slot Control 7000 + 2N OEM XXXX Output Enable Registers (N=0,1,2,....,127) 83 MT90500 5.2 5.2.1 Register Description Microprocessor Interface Registers Table 12 - Main Control Register Address: 0000 (Hex) Label: MCR Reset Value: 0000 (Hex) Label TDM_INTE TX_SAR_INTE RX_SAR_INTE MUX_INTE TIM_INTE Reserved PAGE_MODE PTXCLK_SEL CLOCKMOD Bit Position 0 1 2 3 4 10:5 11 13:12 14 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W Description TDM Module Interrupt Enable. Enables interrupts from the TDM module when `1'. See TDM_SERV in Register 0002h. TX_SAR Module Interrupt Enable. Enables interrupts from the TX_SAR module when `1'. See TX_SAR_SERV in Register 0002h. RX_SAR Module Interrupt Enable. Enables interrupts from the RX_SAR module when `1'. See RX_SAR_SERV in Register 0002h. UTOPIA MUX Sub-module Interrupt Enable. Enables interrupts from the UTOPIA module when `1'. See MUX_SERV in Register 0002h. Timing Recovery Module Interrupt Enable. Enables interrupts from the Timing Recovery module when `1'. See TIM_SERV in Register 0002h. Reserved. Must be set to "100_000". For normal operation, set this bit to `1'. PTXCLK Select. Choose how PTXCLK is generated. "00"= PTXCLK pin is tristated (external oscillator drives the pin); "01"= MCLK/2; "10"= MCLK/4; "11"=STXCLK. Clock Mode. When `0', all external clocks (except MCLK) are replaced by MCLK/4. When `1', all clocks operate normally. This feature ensures that all internal blocks in the MT90500 are reset even if some secondary clocks are absent. To prevent internal clock glitches, this bit should be set before SRES is de-asserted. Software Reset. When `0', all modules except the CPU module are maintained in a reset state. Note that the MT90500 is synchronously reset, and that MCLK should be applied during reset. Reset should last at least 2 sec when MCLK is 60 MHz (>75 clock cycles). Note: SRES should be written to `1' before any other register is accessed. SRES 15 R/W Table 13 - Main Status Register Address: 0002 (Hex) Label: MSR Reset Value: 00X0 (Hex) Label TDM_SERV Bit Position 0 Type R/O Description TDM Module Service Request. When `1', indicates the TDM module requires service (i.e. at least one TDM Interface event bit (in register 6002h) and matching enable bit (in register 6000h) are set). When this bit is `1' and the TDM_INTE interrupt enable bit is `1' in the MCR (Register 0000h), an external hardware interrupt is generated. TX_SAR Module Service Request. When `1', indicates the TX_SAR module requires service (i.e. at least one TX_SAR event bit (in register 2002h) and matching enable bit (in register 2000h) are set). When this bit is `1' and the TX_SAR_INTE interrupt enable bit is `1' in the MCR (Register 0000h), an external hardware interrupt is generated. RX_SAR Module Service Request. When `1', indicates the RX_SAR module requires service (i.e. at least one RX_SAR event bit (in register 3002h) and matching enable bit (in register 3000h) are set). When this bit is `1' and the RX_SAR_INTE interrupt enable bit is `1' in the MCR (Register 0000h), an external hardware interrupt is generated. UTOPIA MUX Sub-module Service Request. When `1', indicates the UTOPIA MUX submodule requires service (i.e. at least one UTOPIA event bit (in register 4002h) and matching enable bit (in register 4000h) are set). When this bit is `1' and the MUX_INTE interrupt enable bit is `1' in the MCR (Register 0000h), an external hardware interrupt is generated. TX_SAR_SERV 1 R/O RX_SAR_SERV 2 R/O MUX_SERV 3 R/O 84 MT90500 Table 13 - Main Status Register Address: 0002 (Hex) Label: MSR Reset Value: 00X0 (Hex) Label TIM_SERV Bit Position 4 Type R/O Description Timing Module Service Request. When `1', indicates the Timing Recovery module requires service (i.e. at least one Clock Recovery event bit (in register 6082h) and matching enable bit (in register 6080h) are set. When this bit is `1' and the TIM_INTE interrupt enable bit is `1' in the MCR (Register 0000h), an external hardware interrupt is generated. Reserved. Undefined at reset. `1' when any of bits<4:0> is set. Undefined at reset. Always read "0000_0000" Reserved SERVICE Reserved 6:5 7 15:8 R/0 R/O R/O Table 14 - Window to External Memory Register - CPU Address: 0030 (Hex) Label: WTEMC Reset Value: 0000 (Hex) Label EXTMADD16 EXTMADD17 EXTMADD18 EXTMADD19 EXTMADD20 Reserved Bit Position 0 1 2 3 4 15:5 Type R/W R/W R/W R/W R/W R/W Description This bit represents address line A[16] for external memory access (CPU byte address). This bit maps to MEM_ADD[14] (double-word address). This bit represents address line A[17] for external memory access. This bit maps to MEM_ADD[15] or bank_selection (32K addressing mode). This bit represents address line A[18] for external memory access. This bit maps to MEM_ADD[16] or bank_selection (64K addressing mode). This bit represents address line A[19] for external memory access. This bit maps to MEM_ADD[17] or bank_selection (128K addressing mode). This bit represents address line A[20] for external memory access. This bit maps to bank_selection (256K addressing mode). Reserved, must always be "0000_0000_000". This register is automatically used while a CPU access is performed. Table 15 - Read Parity Register Address: 0036 (Hex) Label: RDPAR Reset Value: 0000 (Hex) Label CPUPAR32 CPUPAR33 CPUPAR34 CPUPAR35 Reserved Reserved Bit Position 0 1 2 3 7:4 15:6 Type R/O R/O R/O R/O R/O R/O Description Bit 32 corresponds to the parity bit of the MS byte of the last odd word read from the external memory by the CPU. Bit 33 corresponds to the parity bit of the LS byte of the last odd word read from the external memory by the CPU. Bit 34 corresponds to the parity bit of the MS byte of the last even word read from the external memory by the CPU. Bit 35 corresponds to the parity bit of the LS byte of the last even word read from the external memory by the CPU. Reserved. Reserved. Always read "0000_0000". 85 MT90500 Table 16 - Memory Configuration Register Address: 0040 (Hex) Label: MEMCNF Reset Value: 0008 (Hex) Label ADDMODE Bit Position 1:0 Type R/W Description Addressing Mode. Indicates the number of address lines connected to the external memory and therefore the size of the memory chip(s). "00"=32K (MEM_ADD[14:0]); "01"=64K (MEM_ADD[15:0]); "10"=128K (MEM_ADD[16:0]); "11"=256K (MEM_ADD[17:0]). External Memory Chips per Bank. Indicates the number of external memory devices used in one memory bank. `0'=1 x 32 (36)-bit chip; `1'=2 x 16 (18)-bit chips. Read Length. Indicates the number of clock cycles between an address and its read data. "001"=1 clock cycle (used with "Synchronous Burst RAMs"); "010"=2 clock cycles (used with "Pipeline Synchronous Burst RAMs"); "100"=3 clock cycles; all other values are reserved. Writing a reserved value in this register may have adverse effects on the MT90500 and the external memories. Read/Write Turn Around Cycles. `0'=Disabled; `1'=Enabled. Read Bank1 / Read Bank2 Turn Around Cycles. `0'=Disabled; `1'=Enabled. CPBANK READLEN 2 5:3 R/W R/W RWTA RRTA 6 7 R/W R/W 8 9 10 Reserved 15:8 R/W R/W R/W R/W Reserved. These bits must always be "0000_0000" during operation. For further details on memory configuration, see Section 4.2, "External Memory Controller," on page 38. 86 MT90500 5.2.2 TX_SAR Registers Table 17 - TX_SAR Control Register Address: 2000 (Hex) Label: TXSC Reset Value: 0000 (Hex) Label SAENA Bit Position 0 Type R/W Description Scheduler A Enable. `0' = Disabled; `1' = Enabled. Before enabling this scheduler, all its configuration registers must be written and valid. These registers must not be changed while SAENA is HIGH. If an event scheduler is re-configured (i.e. changes made to 2010h, 2012h, or 2014h), all of its events and dependent structures should be re-initialized before starting the scheduler again. Scheduler B Enable. `0' = Disabled; `1' = Enabled. Before enabling this scheduler, all its configuration registers must be written and valid. These registers must not be changed while SBENA is HIGH. If an event scheduler is re-configured (i.e. changes made to 2020h, 2022h, or 2024h), all of its events and dependent structures should be re-initialized before starting the scheduler again. Scheduler C Enable. `0' = Disabled; `1' = Enabled. Before enabling this scheduler, all its configuration registers must be written and valid. These registers must not be changed while SCENA is HIGH. If an event scheduler is re-configured (i.e. changes made to 2030h, 2032h, or 2034h), all of its events and dependent structures should be re-initialized before starting the scheduler again. Transmit FIFO Enable. When this bit is LOW, the Transmit Data Cell FIFO Read Pointer (TXFFRP in TXDFRP at 2054h) is reset to 00h. When this bit is HIGH, the FIFO can operate normally. When this bit is `1', non-CBR data cells (the next cells located in the Transmit Data Cell FIFO) will be transmitted while the TX_SAR is idle. When this bit is `0', data cell transmission is controlled by the schedulers. Transmit Data Cell FIFO Overrun Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on TXFFOR in Register 2002h will force a `1' on TX_SAR_SERV in Register 0002h. Scheduler Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on SCHEDULE in Register 2002h will force a `1' on TX_SAR_SERV in Register 0002h. Increment Transmit Data Cell FIFO Read Pointer. When `1' is written to this bit, the Transmit Data Cell FIFO Read Pointer (TXFFRP) is incremented. Used for test purposes only. Test Status. When HIGH, this bit forces all the status events in TX_SAR Status Register at 2002h to occur. Used for test purposes only. Reserved. Always read as "0000_000". SBENA 1 R/W SCENA 2 R/W TXFFENA 3 R/W AUTODATA 4 R/W TXFFORIE 5 R/W SCHEDULE_IE TXFFRP+ 6 7 R/W R/W TESTS Reserved 8 15:9 R/W R/O Table 18 - TX_SAR Status Register Address: 2002 (Hex) Label: TXSS Reset Value: 0000 (Hex) Label Reserved TXFFOR Bit Position 4:0 5 Type R/O R/O/L Reserved. Always read as "0_0000". Transmit Data FIFO Overrun. When set, this bit indicates that the CPU changed the value of the Transmit Data Cell FIFO Write Pointer (2052h) to the value of the Transmit Data Cell FIFO Read Pointer (2054h). When this event occurs, the MT90500 assumes that the CPU is trying to write one more non-CBR cell than the FIFO can contain. Writing a `1' over this bit clears it. Description 87 MT90500 Table 18 - TX_SAR Status Register Address: 2002 (Hex) Label: TXSS Reset Value: 0000 (Hex) Label SCHEDULE Bit Position 6 Type R/O/L Description Scheduler Error. The TX_SAR has too heavy a work load (e.g. too many events per scheduler frame; uneven distribution of events throughout the scheduler). To recover, the schedulers must be stopped and re-balanced. The TX Control Structures must also be reinitialized. Writing a `1' over this bit clears it. Fatal error. Reserved. Always read as "000_0000_0". TX Service. This bit is set if bit<5> or bit<6> is set. Reserved TXSERV 14:7 15 R/O R/W Table 19 - TX_SAR Scheduler Base Register Address: Scheduler A: 2010 (Hex); Scheduler B: 2020 (Hex); Scheduler C: 2030 (Hex) Label: TESBAA; TESBAB; TESBAC Reset Value: 0000 (Hex) Label SBASE Bit Position 11:0 Type R/W Description Scheduler Base Address. This register contains bits<20:9> of the base address of an event scheduler. Bits<8:0> are always 000h. This register must not be changed when the scheduler is enabled. Entries per Frame. This register contains the number of entries in one frame on the scheduler. "0000" = 8 entries; "0001" = 16 entries; "0010" = 32 entries; all other values are reserved. This register must not be changed when the scheduler is enabled. ENTRY 15:12 R/W Note: All scheduler entries must be read from external SSRAM to check if they are active or inactive. Better memory-bandwidth efficiency is achieved with fewer entries-per-frame and events distributed throughout the frames of the scheduler, as opposed to having bursts of events and many inactive entries. Table 20 - TX_SAR Frame End Register Address: Scheduler A: 2012 (Hex); Scheduler B: 2022 (Hex); Scheduler C: 2032 (Hex) Label: TESFEA; TESFEB; TESFEC Reset Value: 0000 (Hex) Label SHTEND Bit Position 7:0 Type R/W Description Short End Frame. This register indicates the number of the last frame when the scheduler is executing a short turn. This register must not be changed when the scheduler is enabled. Long End Frame. This register indicates the number of the last frame when the scheduler is executing a long turn. This register must not be changed when the scheduler is enabled. LNGEND 15:8 R/W Table 21 - TX_SAR End Ratio Register Address: Scheduler A: 2014 (Hex); Scheduler B: 2024 (Hex); Scheduler C: 2034 (Hex) Label: TESERA; TESERB; TESERC Reset Value: 0000 (Hex) Label RATIO Bit Position 2:0 Type R/W Description Long/Short Ratio. This register indicates how many long turns a scheduler must execute for one short turn. In other words, the value in this register is the non-P: P-cell ratio. For pointerless cells, the value must be "000". For structured cells, the value can be "001" (1:1), "011" (3:1), or "111" (7:1). This register must not be changed when the scheduler is enabled. 88 MT90500 Table 21 - TX_SAR End Ratio Register Address: Scheduler A: 2014 (Hex); Scheduler B: 2024 (Hex); Scheduler C: 2034 (Hex) Label: TESERA; TESERB; TESERC Reset Value: 0000 (Hex) Label SINGLE Bit Position 3 Type R/W Description Single Frame Assembly. When `1', this bit indicates that cells must be assembled one frame at a time, which allows an even cell flow. When it is `0', it indicates that cells are formed 4 frames at a time, which allows better external memory efficiency. This register must not be changed when the scheduler is enabled. For full 1024 VC (or 1024 TDM time slot) operation, this bit must be `0'. Reserved. These bits must always be written as "00". Initialization bits for AAL5 operation. These two bits must be written, at initialization, in all three schedulers for AAL5 operation in any scheduler, regardless of how many schedulers are active. The INIT pattern is different in each of the three schedulers: 2014h, Scheduler A(7:6): `01' 2024h, Scheduler B(7:6): `10' 2034h, Scheduler C(7:6): `11' Reserved. These bits must always be "0000_0000". Reserved AAL5_INIT 5:4 7:6 R/W W/O Reserved 15:8 R/O Table 22 - TX_SAR Control Structure Base Address Register Address: 2040 (Hex) Label: TXCSBA Reset Value: 0000 (Hex) Label TXBASE Bit Position 4:0 Type R/W Description TX Control Structure Base Address. When accessing a Transmit Control Structure, TXBASE represents address bits<20:16>; the address in the scheduler, bits<15:4>. This register must not be changed when any scheduler is enabled. Reserved. Always read as "0000_0000_000". Reserved 15:5 R/O Table 23 - Transmit Data Cell FIFO Base Address Register Address: 2050 (Hex) Label: TXDFBA Reset Value: 0000 (Hex) Label TXFFBASE Bit Position 11:0 Type R/W Description Transmit Data Cell FIFO Base Address. Represents address bits<20:9> that point to the first structure in the Transmit Data Cell FIFO. The lower bits of this pointer are "0_0000_0000". Each non-CBR cell occupies a 64-byte buffer. The Transmit Data Cell FIFO must not overlap an 8 Kbyte boundary. When this register is changed, TXFFENA (in the TX_SAR Control Register at 2000h) must not be asserted. Transmit Data Cell FIFO Size. This field indicates the number of non-CBR data cells in the Transmit Data Cell FIFO. "00"=16 cells; "01"=32 cells; "10"=64 cells; "11"=128 cells. When this register is changed, TXFFENA (in the TX_SAR Control Register at 2000h) must not be asserted. Reserved. Always read as "00". TXFFSIZ 13:12 R/W Reserved 15:14 R/W Table 24 - Transmit Data Cell FIFO Write Pointer Register Address: 2052 (Hex) Label: TXDFWP Reset Value: 0000 (Hex) Label TXFFWP Reserved Bit Position 7:0 15:8 Type R/W R/O Description Transmit Data Cell FIFO Write Pointer. Indicates cell structure number in which the CPU is currently writing (the cell is not yet valid) within the Transmit Data Cell FIFO. Reserved. Always read as 00h. 89 MT90500 Table 25 - Transmit Data Cell FIFO Read Pointer Register Address: 2054 (Hex) Label: TXDFRP Reset Value: 0000 (Hex) Label TXFFRP Reserved Bit Position 6:0 15:7 Type R/O R/O Description Transmit Data Cell FIFO Read Pointer. Indicates the cell structure number in which the TX_SAR is currently transmitting (the cell is still valid). Reserved. Always read as "0000_0000_0". 90 MT90500 5.2.3 RX_SAR Registers Table 26 - RX_SAR Control Register Address: 3000 (Hex) Label: RXSCR Reset Value: 0000 (Hex) Label APEMS Bit Position 0 Type R/W Description AAL1-byte Parity Error Misc. Select. When this bit is set, a parity error in the AAL1-byte increments the RX_SAR Misc. Event Counter Register (3012h) and affects the RX_SAR Misc. Event ID Register (3010h). AAL1-byte CRC Error Misc. Select. When this bit is set, a CRC error in the AAL1-byte increments the RX_SAR Misc. Event Counter Register (3012h) and affects the RX_SAR Misc. Event ID Register (3010h). AAL1 Sequence Number Error Misc. Select. When this bit is set, a sequence number error in the AAL1-byte increments the RX_SAR Misc. Event Counter Register (3012h) and affects the RX_SAR Misc. Event ID Register (3010h). Pointer-byte Parity Error Misc. Select. When this bit is set, a parity error in the pointer-byte (for P-Type cells only) increments the RX_SAR Misc. Event Counter Register (3012h) and affects the RX_SAR Misc. Event ID Register (3010h). Pointer-byte Out of Range Error Misc. Select. When this bit is set, an out of range pointerbyte (for P-Type cells only) increments the RX_SAR Misc. Event Counter Register (3012h) and affects the RX_SAR Misc. Event ID Register (3010h). AAL1-byte Parity Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on APE in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h. AAL1-byte CRC Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on ACE in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h AAL1-byte Sequence Number Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on SNE in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h Pointer-byte Parity Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on PPE in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h Pointer-byte Out of Range Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on PORE in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h Write Underrun Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on WURE in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h Write Overrun Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on WORE in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h Misc. Counter Rollover Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on MCR in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h Write UnderRun Counter Rollover Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on WURCR in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h Write Overrun Counter Rollover Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on WORCR in Register 3002h will force a `1' on RX_SAR_SERV in Register 0002h Test Status. When HIGH, this bit forces all the status events in the RX_SAR Status Register at 3002h to occur. Also increments the RX_SAR Misc. Event Counter Register (3012h), the RX_SAR Underrun Event Counter (3022h), and the RX_SAR Overrun Event Counter (3032h) and affects the contents of the RX_SAR Misc. Event ID Register (3010h), the RX_SAR Underrun Event ID Register (3020h), and the RX_SAR Overrun Event ID Register (3030h). Used for test purposes only. ACEMS 1 R/W SNEMS 2 R/W PPEMS 3 R/W POREMS 4 R/W APEIE ACEIE SNEIE 5 6 7 R/W R/W R/W PPEIE POREIE 8 9 R/W R/W WUREIE WOREIE MCRIE WURCRIE 10 11 12 13 R/W R/W R/W R/W WORCRIE 14 R/W TESTS 15 R/W 91 MT90500 Table 27 - RX_SAR Status Register Address: 3002 (Hex) Label: RXSSR Reset Value: 0000 (Hex) Label Reserved APE ACE SNE PPE PORE WURE WORE MCR WURCR WORCR RXSERV Bit Position 4:0 5 6 7 8 9 10 11 12 13 14 15 Type R/O R/O/L R/O/L R/O/L R/O/L R/O/L R/O/L R/O/L R/O/L R/O/L R/O/L R/O/L Reserved. Always read as "0_0000". AAL1-byte Parity Error. `0' = Event has not occurred. `1' = Event has occurred. Writing a `1' over this bit clears it. AAL1-byte CRC Error. `0' = Event has not occurred. `1' = Event has occurred. Writing a `1' over this bit clears it. AAL1-byte Sequence Number Error. `0' = Event has not occurred. `1' = Event has occurred. Writing a `1' over this bit clears it. Pointer-byte Parity Error. `0' = Event has not occurred. `1' = Event has occurred. Writing a `1' over this bit clears it. Pointer-byte Out of Range Error. `0' = Event has not occurred. `1' = Event has occurred. Writing a `1' over this bit clears it. Write Underrun Error. `0' = Event has not occurred. `1' = Event has occurred. Writing a `1' over this bit clears it. Write Overrun Error. `0' = Event has not occurred. `1' = Event has occurred. Writing a `1' over this bit clears it. Misc. Counter Rollover. If set, the RX_SAR Misc. Event Counter Register at 3012h has rolled over. Writing a `1' over this bit clears it. Write Underrun Counter Rollover. If set, the RX_SAR Underrun Event Counter Register at 3022h has rolled over. Writing a `1' over this bit clears it. Write Overrun Counter Rollover. If set, the RX_SAR Overrun Event Counter Register at 3032h has rolled over. Writing a `1' over this bit clears it. RX Service. This bit is set if any of bits<14:5> in this register is set. Writing a `1' over this bit clears it. Description Table 28 - RX_SAR Misc. Event ID Register Address: 3010 (Hex) Label: RXMEID Reset Value: 0000 (Hex) Label MISCID Bit Position 15:0 Type R/W Description MISC. Event ID number. This 16-bit register holds bits<19:4> of the address of the RX Control Structure that caused the last miscellaneous error. This register is only affected by the miscellaneous errors that are selected via the 5 least significant bits of the RX_SAR Control Register (3000h). This register will also be updated if the TESTS bit is set in the RX_SAR Control Register. Table 29 - RX_SAR Misc. Event Counter Register Address: 3012 (Hex) Label: RXMECT Reset Value: 0000 (Hex) Label MISCC Bit Position 15:0 Type R/W Description MISC. Event Count. This 16-bit register's value is incremented each time a miscellaneous error occurs. A miscellaneous error is considered to have occurred if any of bits<9:5> in the RX_SAR Status Register at 3002h is set and the corresponding miscellaneous select bit in bits<4:0> of the RX_SAR Control Register (3000h) is also set. This register is also incremented if TESTS is set in the RX_SAR Control Register. 92 MT90500 Table 30 - RX_SAR Underrun Event ID Register Address: 3020 (Hex) Label: RXUEID Reset Value: 0000 (Hex) Label WURID Bit Position 15:0 Type R/W Description RX_SAR Write Underrun ID Number. This 16-bit register holds bits<19:4> of the address of the RX Control Structure that caused the last write underrun error. This register will also be updated if the TESTS bit is set in the RX_SAR Control Register at 3000h. Table 31 - RX_SAR Underrun Event Counter Register Address: 3022 (Hex) Label: RXUECT Reset Value: 0000 (Hex) Label WURC Bit Position 15:0 Type R/W Description RX_SAR Write Underrun Count. This 16-bit register's value is incremented each time a write underrun occurs or if the TESTS bit is set in the RX_SAR Control Register at 3000h. Table 32 - RX_SAR Overrun Event ID Register Address: 3030 (Hex) Label: RXOEID Reset Value: 0000 (Hex) Label WORID Bit Position 15:0 Type R/W Description RX_SAR Write Overrun ID Number. This 16-bit register holds bits<19:4> of the address of the RX Control Structure that caused the last write overrun error. This register will also be updated if the TESTS bit is set in the RX_SAR Control Register at 3000h. Table 33 - RX_SAR Overrun Event Counter Register Address: 3032 (Hex) Label: RXOECT Reset Value: 0000 (Hex) Label WORC Bit Position 15:0 Type R/W Description RX_SAR Write Overrun Count. This 16-bit register is incremented each time a write overrun occurs or if the TESTS bit is set in the RX_SAR Control Register at 3000h. 93 MT90500 5.2.4 UTOPIA Registers Table 34 - UTOPIA Control Register Address: 4000 (Hex) Label: UCR Reset Value: 0000 (Hex) Label RXENA STXENA Bit Position 0 1 Type R/W R/W Description RX Cell Enable. When `0', all received cells are ignored. When `1', received cells are processed normally. Secondary TX Cell Enable. When this bit is `0', no cells may be received from the secondary TX interface. When `1', the UTOPIA module receives cells from the secondary SAR normally. Round-Robin Priority. When `0', CBR traffic from the MT90500 has priority over traffic from the secondary SAR interface. When `1', both traffic types have the same priority. Receive FIFO Enable. When this bit is LOW, the Receive Data Cell FIFO Write Pointer (RXFFWP at 4022h) is reset to 00h. When this bit is HIGH, the FIFO can operate normally. Increment Receive Data Cell FIFO Write Pointer. When `1' is written on this bit, the Receive Data Cell FIFO Write Pointer (RXFFWP at 4022h) is incremented. Used for test purposes only. OAM Routing Select. `0' = discard; `1'= treat as non-CBR data cell. Unknown Routing Select. `0' = discard cells with undefined entry types (i.e. T bits = "00" in look-up table); `1'= treat cells with undefined entry types (i.e. T bits = "00" in look-up table) as non-CBR data cells. RX Control Structure Base Address. These three bits represent the three most significant address bits<20:18> of the pointer to the Receive Control Structures. Receive Data Cell FIFO Overrun Error Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on RXFFOR in Register 4002h will force a `1' on MUX_SERV in Register 0002h. RX UTOPIA Module Internal FIFO Overrun Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on RXOR in Register 4002h will force a `1' on MUX_SERV in Register 0002h. Receive Data FIFO Receive Cell Interrupt Enable. `0' = Disabled; `1' = Enabled. When enabled, a `1' on RXFFRC in Register 4002h will force a `1' on MUX_SERV in Register 0002h. Reserved. Should be written as "00". TEST Status. When HIGH, this bit forces the three status events (bits<12:10>) in the UTOPIA Status Register at 4002h to occur. Used for test purposes only. RRP RXFFENA RXFFWP+ 2 3 4 R/W R/W R/W OAMSEL UKSEL 5 6 R/W R/W RXBASE RXFFORIE 9:7 10 R/W R/W RXORIE 11 R/W RXFFRCIE 12 R/W Reserved TESTS 14:13 15 R/W R/W Table 35 - UTOPIA Status Register Address: 4002 (Hex) Label: USR Reset Value: 0000 (Hex) Label Reserved RXFFOR Bit Position 9:0 10 Type R/O R/O/L Description Reserved. Always read as "00_0000_0000". Receive Data Cell FIFO Overrun Error. When this bit is `1', the RXFFWP (register 4022h) = RXFFRP (register 4024h) and one or more non-CBR data cells were discarded because the Receive Data Cell FIFO was full. Writing a `1' over this bit clears it. Receive UTOPIA Module Internal FIFO Overrun. At least one CBR cell was lost because the RX_SAR did not process the cells fast enough. Writing a `1' over this bit clears it. Data FIFO Receive Cell. Each time a non-CBR data cell is received, this bit is set. Writing a `1' over this bit clears it. Reserved. Always read as "00". UTOPIA Service. When any of the status bits in this register are HIGH, this bit is HIGH. RXOR RXFFRC Reserved UTOSERV 11 12 14:13 15 R/O/L R/O/L R/O R/O 94 MT90500 Table 36 - VPI / VCI Concatenation Register Address: 4010 (Hex) Label: VPVCC Reset Value: 0000 (Hex) Label N M Reserved Reserved Bit Position 4:0 7:5 8 15:9 Type R/W R/W R/W R/O Description The N least significant bits of the VCI to be used as an address in the VC look-up table. The M least significant bits of the VPI to be used as an address in the VC look-up table. Reserved. Must be written as `0'. Reserved. Always read as "0000_000". The VC search mechanism uses a table that can have up to 32K double-word (32-bit) entries. The table can therefore be 128 Kbytes long. This requires a 17-bit offset pointer formed by adding two least significant zeroes to a base 15-bit pointer. The base 15-bit pointer is formed by concatenation of the N least significant bits of the VCI with the M least significant bits of the VPI. The sum of M+N must be at least 8 and a maximum of 15. If M+N < 15, the most significant bits are zeroed. Example: assume N=8, indicating that the 8 LSBs of the VCI will be used to form the least significant part of the pointer. Assume M=4, indicating that the 4 LSBs of the VPI will be used to form the most significant portion of the pointer. Since M+N = 12 < 15, bits<14:12> of the base pointer will be zeroed. Assume the receive VPI value is 23h and the receive VCI value is 5678h. The resulting base 15-bit pointer will be "0378." When two least significant `0' bits are added to form a 17-bit pointer, the result is 00DE0h. This value is added to the Look-up Table Base Address Register (401Eh) contents to form a 21-bit address than can be located anywhere in memory. Table 37 - VPI Match Register Address: 4012 (Hex) Label: VPMT Reset Value: 0000 (Hex) Label VPIMATCH Reserved Bit Position 7:0 15:8 Type R/W R/O Description VPI Match value. VPI of received cells are compared to the value in this register to see if the cells should be passed to the internal FIFO, or discarded. Reserved. Always read as 00h. Note: Set the VPI Match and Mask filter as narrowly as practical for the application. See Receive Cell Selection Process on page 63. Table 38 - VPI Mask Register Address: 4014 (Hex) Label: VPMS Reset Value: 0000 (Hex) Label VPIMASK Bit Position 7:0 Type R/W Description VPI Mask value. Each bit, when set, enables the comparison of the cell VPI and the VPIMATCH field. If a bit in this register is not set, the corresponding bit in the received cell VPI is considered valid, regardless of the setting in the VPIMATCH field. Reserved. Always read as 00h. Reserved 15:8 R/O Table 39 - VCI Match Register Address: 4016 (Hex) Label: VCMT Reset Value: 0000 (Hex) Label VCIMATCH Bit Position 15:0 Type R/W Description VCI Match value. VCI of received cells are compared to the value in this register to see if the cells are valid. Note: Set the VCI Match and Mask filter as narrowly as practical for the application. See Receive Cell Selection Process on page 63. 95 MT90500 Table 40 - VCI Mask Register Address: 4018 (Hex) Label: VCMS Reset Value: 0000 (Hex) Label VCIMASK Bit Position 15:0 Type R/W Description VCI Mask value. Each bit, when set, enables the comparison of the cell VCI and the VCIMATCH field. If a bit in this register is not set, the corresponding bit in the received cell VCI is considered valid, regardless of the setting in the VCIMATCH field. Table 41 - VPI Timing Register Address: 401A (Hex) Label: VPITIM Reset Value: 0000 (Hex) Label TIMING VPI Bit Position 7:0 Type R/W Description VPI of the timing reference VC. If the VPI_VCI of the incoming cell matches that contained within this register and the VCI Timing Register at 401Ch, a clock pulse will be sent to the clock recovery module. Reserved. Always read as 00h. Reserved 15:8 R/O Table 42 - VCI Timing Register Address: 401C (Hex) Label: VCITIM Reset Value: 0000 (Hex) Label TIMING VCI Bit Position 15:0 Type R/W Description VCI of the timing reference VC. If the VPI_VCI of the incoming cell matches that contained within this register and the VPI Timing Register at 401Ah, a clock pulse will be sent to the clock recovery module. Table 43 - Lookup Table Base Address Register Address: 401E (Hex) Label: LUTBA Reset Value: 0000 (Hex) Label LUTBASE Bit Position 15:0 Type R/W Description Look-Up Table Base Address. Represents bits<20:5> of the pointer to the look-up table (bits<4:0> are "0_0000"). It must point to a boundary larger than or equal to K * {2^(M+N+2)} bytes, where K = 0,1,2,... and M and N are those values obtained from VPI/ VCI Concatenation Register at address 4010h. In addition, the look-up table requires an external memory allocation of 2^(M+N+2) bytes to accommodate the entire look-up table. 96 MT90500 Table 44 - Receive Data Cell FIFO Base Address Register Address: 4020 (Hex) Label: RXDFBA Reset Value: 0000 (Hex) Label RXFFBASE Bit Position 11:0 Type R/W Description Receive Data Cell FIFO Base Address. Represents address bits <20:9> that point to the first structure in the Receive Data Cell FIFO. The lower address bits <8:0> of the pointer are "0_0000_0000". Each cell occupies a 64-byte buffer. Bit<0> of this field must always be `0'. The Receive Data Cell FIFO must not overlap an 8 Kbyte boundary. When this register is changed, FFENA in the UTOPIA Control Register at 4000h must not be asserted. Receive Data Cell FIFO Size. This field contains the number of non-CBR data cells in the Receive Data Cell FIFO. "00"=16 cells; "01"=32 cells; "10"=64 cells; "11"=128 cells. When this register is changed, FFENA in the UTOPIA Control Register at 4000h must not be asserted. Reserved. Always read as "00". RXFFSIZ 13:12 R/W Reserved 15:14 R/W Table 45 - Receive Data Cell FIFO Write Pointer Register Address: 4022 (Hex) Label: RXDFWP Reset Value: 0000 (Hex) Label RXFFWP Bit Position 7:0 Type R/O Description Receive Data Cell FIFO Write Pointer. Indicates cell structure number in which the UTOPIA module is currently writing (the cell is not valid yet) within the Receive Data Cell FIFO. Reserved. Always read as 00h. Reserved 15:8 R/O Table 46 - Receive Data Cell FIFO Read Pointer Register Address: 4024 (Hex) Label: RXDFRP Reset Value: 0000 (Hex) Label RXFFRP Reserved Bit Position 7:0 15:8 Type R/W R/O Description Receive Data Cell FIFO Read Pointer. Indicates the cell structure number in which the CPU is currently reading (the cell is still valid). Must be set by CPU as cells are read. Reserved. Always read as 00h. 97 MT90500 5.2.5 TDM Interface and Clock Interface Registers Table 47 - TDM Interface Control Register Address: 6000 (Hex) Label: TDMCNT Reset Value: 0000 (Hex) Label TIENA IEENA Bit Position 0 1 Type R/W R/W Description TDM to/from Internal Memory Process Enable. `0'=Disabled; `1'=Enabled. Internal to/from External Memory Process Enable. `0'=Disabled; `1'=Enabled. GENOE 2 R/W General Output Enable. Enables TDM data outputs and inputs. `0' = TDM data output pins tristated and TDM output (i.e. receive) data is looped back as TDM input (i.e. transmit) data; `1' = Normal TDM operation. In order to prevent collisions on the TDM bus, one should clear all of the Output Enable Registers (addresses 7000 + 2N) prior to setting this bit. When LOW, disables CFAIL and CABS bits in the TDM Interface Status Register (6002h). CLK_LOOPBACK 3 R/W TDM Clock Loopback. `0' = Normal operation; `1' = Loopback. In loopback the CLKx2, CLKx1, and FSYNC input signals are replaced by the internally generated clocks, but the clock pins are not driven by the MT90500. Clock Absent Interrupt Enable. `0'=Disabled; `1'=Enabled. When enabled, a `1' on CABS in Register 6002h will force a `1' on TDM_SERV in Register 0002h. Clock Fail Interrupt Enable. `0'=Disabled; `1'=Enabled. When enabled, a `1' on CFAIL in Register 6002h will force a `1' on TDM_SERV in Register 0002h. TDM Out of Bandwidth Interrupt Enable. `0'=Disabled; `1'=Enabled. When enabled, a `1' on TOB in Register 6002h will force a `1' on TDM_SERV in Register 0002h. TDM Read Underrun Error Interrupt Enable. `0'=Disabled; `1'=Enabled. When enabled, a `1' on TRUE in Register 6002h will force a `1' on TDM_SERV in Register 0002h. TDM Read Underrun Counter Rollover Interrupt Enable. `0'=Disabled; `1'=Enabled. When enabled, a `1' on TRUCR in Register 6002h will force a `1' on TDM_SERV in Register 0002h. Reserved. Always read as "000_000". TEST Status. Forces all status events in both the TDM Interface Status Register (6002h) and the Clock Module General Status Register (6082h) to occur. Also causes the TDM Read Underrun Count Register (6048h) to be incremented and the TDM Read Underrun Address Register (6046h) to be updated. Used for test purposes only. CABSIE CFAILIE TOBIE TRUEIE TRUCRIE 4 5 6 7 8 R/W R/W R/W R/W R/W Reserved TESTS 14:9 15 R/O R/W 98 MT90500 Table 48 - TDM Interface Status Register Address: 6002 (Hex) Label: TIS Reset Value: XX00 Label Reserved CABS Bit Position 3:0 4 Type R/O R/O/L Reserved. Always read as "0000". Clock Absent. This flag is raised when one or more of the three TDM clock pins (CLKX2, CLKX1, and FSYNC) has not changed state within a specified number of MCLK cycles. The signals are monitored when the pins are inputs (TDM Clock Slave or Clock Master Alternate modes), and also when the pins are outputs (TDM Clock Master mode). This flag is disabled when GENOE is LOW. Writing a `1' over this bit clears it. Note when TCLKSYN in register 6010h is set to `1' in TDM Slave mode, the CLKx1 pin is not used as an output but remains high-impedance. The CABS bit will therefore report a loss of clocks unless an external signal is present at the CLKx1 pin. CFAIL 5 R/O/L SCSA Clock Fail. This flag is used only when the MT90500 is NOT the clock master (i.e. configured as Slave or as Clock Master Alternate in SCSA mode). This flag is raised and latched when the CLKFAIL pin is sampled HIGH and the CORSIGA pin is configured as CLKFAIL input (i.e. CORSIGACNF in 6004h must be "11"). The CORSIGA bit in this register can be used to verify the current state of the CLKFAIL signal. When this bit is HIGH, and the CLK_ALT bit in 6010h is HIGH, the MT90500 will drive the TDM clock lines (switch from Master Alternate to Master) and if CORSIGACNF is "11", drive 0 out on CORSIGA/CLKFAIL. This flag is disabled when GENOE is LOW. Writing a `1' over this bit clears it. TOB 6 R/O/L TDM Out of Bandwidth. This flag is raised when the internal to/from external memory process is unable to transfer all the data in the specified time. This flag generally indicates that there is a bandwidth limitation in accesses to external memory. External memory access requirements must be reduced, or external memory speed must be increased. The IEENA bit in the TDM Interface Control Register at 6000h must be set for this error to be generated. Writing a `1' over this bit clears it. TRUE 7 R/O/L TDM Read Underrun Error. `0' = Error has not occurred. `1' = An underrun has occurred. Indicates the occurrence of an underrun on a TDM read from one of the Receive Circular Buffers. This error-indication is controlled by the TDM Read Underrun Detection Enable (U) bits in the External Memory to Internal TDM Memory Control Structure (i.e. if the U bits are LOW, no underrun errors will be noted in this register). Writing a `1' over this bit clears it. TRUCR TDMSERV Reserved CORSIGA CORSIGB CORSIGC CORSIGD CORSIGE 8 9 10 11 12 13 14 15 R/O/L R/O R/O R/O R/O R/O R/O R/O TDM Read Underrun Count Rollover. This flag is raised when the underrun counter at register 6048h returns to 0000h. Writing a `1' over this bit clears it. TDM Service Bit. This bit is set if any of the above status bits<8:4> is set. Reserved. Always read as `0'. CORSIGA pin's current logic level. Undefined at reset. CORSIGB pin's current logic level. Undefined at reset. CORSIGC pin's current logic level. Undefined at reset. CORSIGD pin's current logic level. Undefined at reset. CORSIGE pin's current logic level. Undefined at reset. Description 99 MT90500 Table 49 - TDM I/O Register Address: 6004 (Hex) Label: CORSIG Reset Value: 0000 (Hex) Label CORSIGACNF Bit Position 1:0 Type R/W Description CORSIGA Configuration. Selects operation of the CORSIGA pin. "00" General I/O pin configured as input (see CORSIGA bit in register 6002h) "01" General I/O pin configured as programmable output (see CORSIGA bit in this register) "10" Reserved "11" CLKFAIL I/O (see CFAIL at 6002h) - zero driven out when the MT90500 is clock master; CLKFAIL input from SCSA bus when in slave mode or inactive clock master alternate. CORSIGB Configuration. "00" General I/O pin configured as input "01" General I/O pin configured as programmable output (see CORSIGB bit in this register) "10" MC: I/O for SCSA message channel (RXDATA sent to CORSIGD; TXDATA read from CORSIGC "11" FNXI: SRTS FNX Network Clock Input. CORSIGC Configuration. "00" General I/O pin configured as input "01" General I/O pin configured as programmable output (see CORSIGC bit in this register) "10" HDLC MCTX: data input for SCSA message channel "11" SRTS ENA output (there is a valid SRTS bit being transmitted on CORSIGD). CORSIGD Configuration. "00" General I/O pin configured as input "01" General I/O pin configured as programmable output (see CORSIGD bit in this register) "10" HDLC MCRX: data output for SCSA message channel "11" SRTS DATA output from the clock recovery module. CORSIGE Configuration. "00" General I/O pin configured as input "01" General I/O pin configured as programmable output (see CORSIGE bit in this register) "10" HDLC MCCLK: clock output for SCSA message channel "11" Reserved. Reserved. Should be set to `0'. Value that will be driven on CORSIGA output pin (only applicable if CORSIGACNF="01"). Value that will be driven on CORSIGB output pin (only applicable if CORSIGBCNF="01"). Value that will be driven on CORSIGC output pin (only applicable if CORSIGCCNF="01"). Value that will be driven on CORSIGD output pin (only applicable if CORSIGDCNF="01"). Value that will be driven on CORSIGE output pin (only applicable if CORSIGECNF="01"). CORSIGBCNF 3:2 R/W CORSIGCCNF 5:4 R/W CORSIGDCNF 7:6 R/W CORSIGECNF 9:8 R/W Reserved CORSIGA CORSIGB CORSIGC CORSIGD CORSIGE 10 11 12 13 14 15 R/W R/W R/W R/W R/W R/W 100 MT90500 Table 50 - TDM Bus Type Register Address: 6010 (Hex) Label: TDMTYP Reset Value: 0000 (Hex) Label TDMFS Bit Position 1:0 Type R/W Description TDM Fsync type. "00" = negative polarity for half-cycle of CLKx1, straddling the frame boundary (SCSA/ MVIP/H-MVIP/ST-BUS); "01" = Reserved; "10" = Reserved; "11" = positive polarity for full-cycle of CLKx1, preceding the frame boundary (IDL). When using the positive polarity frame sync, the MT90500 must be in Master mode, or TCLKSYN (bit<6>) should be LOW, and the SC bus HDLC access will not function (pins MC, MCRX, MCTX and MCCLK). TDM Sampling. Determines the sampling point of the serial input bit. "00" = 4/4; "01" = 3/4; "10" = 2/4; "11" = Reserved. TDM Clock speed. Determines the data rate of the TDM bus (and CLKX1). "00" = 2 MHz, 32 time slots/frame; "01" = 4 MHz, 64 time slots/frame; "10" = 8 MHz, 128 time slots/frame; "11" = Reserved. Selects source for internal CLKx1. `0' = normal CLKx1 output operation as TDM Master, normal CLKx1 input operation as TDM Slave; `1' = derive CLKx1 from CLKx2 (Slave mode where no CLKx1 is provided by TDM bus) Note that in TDM Slave mode, with TCLKSYN = `1', the CLKx1 pin is not used as an output but remains high-impedance. The CABS bit in register 6002h will therefore report a loss of clocks unless an external signal is present at the CLKx1 pin. Clock Type. Selects operation of CLKx2 Input when TDM Slave mode is selected (no effect when TDM Master mode is selected). `0' = single-ended input (one input pin: CLKx2); `1' = differential input (two input pins: CLKx2PI and CLKx2NI). TDM Clock Master. `0' = MT90500 is TDM Slave, and does not drive TDM clock pins (CLKx2 is an input); `1' = MT90500 is TDM Master, and drives the TDM clock pins (MT90500 drives CLKx2, CLKx1, and FSYNC). TDM Clock Alternate. `0' = disabled; `1' = MT90500 is designated as Clock Master Alternate The Clock Master Alternate will become the Clock Master and drive the clock lines only if the clock fail status bit (CFAIL in 6002h) is HIGH. Note: This bit is only used when CORSIGACNF in 6004h is "11", indicating that the CORSIGA pin is configured as CLKFAIL input (SCSA mode). Reserved. Must always be set to `0'. BUS Hold Time. `0' = fast bus (SCSA 8 Mbps); `1' = slow bus (MVIP / SCSA2 / IDL / ST-BUS) Reserved. Always read as "0000". TDMSMPL 3:2 R/W TDMCLK 5:4 R/W TCLKSYN 6 R/W CLKTYPE 7 R/W CLKMASTER 8 R/W CLKALT 9 R/W Reserved BUSHOLD 10 11 R/W R/W Reserved 15:12 R/O 101 MT90500 Table 51 - Local Bus Type Register Address: 6020 (Hex) Label: LBTYP Reset Value: 0000 (Hex) Label LBUSFS Bit Position 1:0 Type R/W Description Local Bus Fsync type. "00" = negative polarity for half-cycle of LOCx1, straddling the frame boundary (SCSA/ MVIP/H-MVIP/ST-BUS); "01" = Reserved; "10" = Reserved; "11" = positive polarity for full-cycle of LOCx1, preceding the frame boundary (IDL). Local Bus Sampling. "00" = 4/4; "01" = 3/4; "10" = 2/4; "11" = Reserved. Reserved. Should be written as "00". Local Bus Clock Division factor. Amount that TDM backplane clock must be divided to generate 2.048 Mbps local bus. "00" = Direct; "01" = Divided by 2; "10" = Divided by 4; "11" = Reserved. Indicates which input TDM stream will be routed to LOCSTo. Indicates on which output TDM stream LOCSTi will be routed. LBUSSMPL 3:2 R/W Reserved LCLKDIV 5:4 7:6 R/W R/W STi2LOCSTo LOCSTi2STo 11:8 15:12 R/W R/W Table 52 - TDM Bus to Local Bus Transfer Register Address: 6022 (Hex) Label: TDMLOC Reset Value: 0000 (Hex) Label TDM2LOCTS Reserved LOCSToNUM Bit Position 6:0 7 14:8 Type R/W R/W R/W Description LOCSTo TDM Time Slot. Input TDM time slot which will be transmitted out on LOCSTo time slot 0. Reserved. Should be written as `0'. LOCSTo Number of Time Slots. Number of time slots that are passed from the TDM bus to the local bus. "0000000" = 1 channel; "0011111" = 32 channels. Transfer Enable. When `0', the transfer process from the TDM bus to the local bus is disabled. When `1', the transfer is enabled. Whenever the transfer of data from the TDM bus to the local bus is disabled (either because this bit is `0' or because the specified number of time slots has been transferred), LOCSTi and LOCSTo are internally connected and operate in loopback mode. Note: the TIENE bit at register 6000h must be set to `1' (TDM to/from Internal Memory transfer enabled) for the Local Bus to/from TDM Bus transfer to operate. TENA 15 R/W 102 MT90500 Table 53 - Local Bus to TDM Bus Transfer Register Address: 6024 (Hex) Label: LOCTDM Reset Value: 0000 (Hex) Label LOC2TDMTS Reserved LOCSTiNUM Bit Position 6:0 7 14:8 Type R/W R/W R/W Description LOCSTi TDM Time Slot. Output TDM time slot on which LOCSTi time slot 0 will be transmitted. Reserved. Should be written as `0'. LOCSTi Number of Time Slots. Number of time slots that are passed to the TDM bus from the local bus. "0000000" = 1 channel; "0011111" = 32 channels. Receive Enable. When '1', the transfer process is enabled and from 1 to 32 local bus time slots will replace the TDM data coming from the RX_SAR. Note: the TIENE bit at register 6000h must be set to `1' (TDM to/from Internal Memory transfer enabled) for the Local Bus to/from TDM Bus transfer to operate. Note: The Output Enable Registers must be enabled to permit these data bytes to be transferred out on the TDM bus. RENA 15 R/W Table 54 - TX Circular Buffer Control Structure Base Register Address: 6040 (Hex) Label: TXCBCS Reset Value: 0000 (Hex) Label TXCBCSL Bit Position 3:0 Type R/W Description TX Circular Buffer Control Structure Length. "0000" = 128 entries; "0001" = 256 entries; "0010" = 512 entries; "0011" = 1024 entries; "0100" = 2048 entries; other = reserved. TX Circular Buffer Control Structure Base Address. This field represents bits<20:9> of the base address of the TX Circular Buffer Control Structure. The table that this structure points to must not cross an 8 Kbyte boundary. TXCBCSBASE 15:4 R/W Refer to Figure 5 on page 34 for implementation details. Table 55 - External to Internal Memory Control Structure Base Register Address: 6042 (Hex) Label: EMIM Reset Value: 0000 (Hex) Label EIMCSL Bit Position 3:0 Type R/W Description External to Internal Memory Control Structure Length. "0000" = 128 entries; "0001" = 256 entries; "0010" = 512 entries; "0011" = 1024 entries; "0100" = 2048 entries; other = reserved. External to Internal Memory Control Structure Base Address. This field represents bits<20:9> of the base address of the External to Internal Memory Control Structure. The table that this structure points to must not cross an 8 Kbyte boundary. EIMCSBASE 15:4 R/W Refer to Figure 7 on page 37 for implementation details. 103 MT90500 Table 56 - TX Circular Buffer Base Address Register Address: 6044(Hex) Label: TXCBBA Reset Value: 0000 (Hex) Label Reserved TXCBBASE Bit Position 3:0 15:4 Type R/W R/W Description Reserved. Should be written as "0000". TX Circular Buffer Base Address. This field represents bits<20:9> of the base address of the TX Circular Buffer's base address. The pointer to the circular buffers must not overlap a 64 Kbyte boundary. Table 57 - TDM Read Underrun Address Register Address: 6046 (Hex) Label: RXUNDA Reset Value: 0000 (Hex) Label TRURTSST Reserved Bit Position 10:0 15:11 Type R/O R/O Description TDM Read Underrun Time Slot Stream. Contains the time slot (bits<10:4>) and stream (bits<3:0>) on which the last underrun was detected. Reserved, always read as "0000_0". Table 58 - TDM Read Underrun Count Register Address: 6048 (Hex) Label: RXUNDC Reset Value: 0000 (Hex) Label TRURCOUNT Bit Position 15:0 Type R/O Description TDM Read Underrun Counter. Each time a TDM read underrun occurs, this register's value is incremented. Table 59 - Clock Module General Control Register Address: 6080 (Hex) Label: CMGCR Reset Value: 0000 (Hex) Label REFFAILIE SRTSTSIE Bit Position 0 1 Type R/W R/W Description REFFAIL Interrupt Enable - Clock Generation Sub-Module. When enabled, a `1' on REFFAIL in Register 6082h will force a `1' on TIM_SERV in Register 0002h. SRTS Transmit Interrupt Enable - SRTS Sub-Module. When enabled, a `1' on SRTST_UND or SRTST_OVR in Register 6082h will force a `1' on TIM_SERV in Register 0002h. Counter Update Control - When a `1' is written to this bit, the counts in registers 0x60A2, 0x60A4, and 0x60A6 are updated. The values in those registers will remain the same until the next time a `1' is written to this bit. The static value of this bit is always ignored. SRTS Receive Interrupt Enable - SRTS Sub-Module. When enabled, a `1' on SRTSR_UND or SRTSR_OVR in Register 6082h will force a `1' on TIM_SERV in Register 0002h. Reserved. Should be written as `0'. Loss of Timing Reference Cells Interrupt Enable - Timing Reference Cell Sub-Module. When enabled, a `1' on LOSS_TIMF in Register 6082h will force a `1' on TIM_SERV in Register 0002h. CNTUPDATE 2 R/W SRTSRSIE Reserved LOSSCIE 3 4 5 R/W R/W R/W 104 MT90500 Table 59 - Clock Module General Control Register Address: 6080 (Hex) Label: CMGCR Reset Value: 0000 (Hex) Label OUT_SYNC_IE TIM_ENA Reserved Bit Position 6 7 15:8 Type R/W R/W R/O Description Out-Of-Sync Interrupt Enable - Timing Reference Cell Sub-Module. When enabled, a `1' on OUT_SYNC in Register 6082h will force a `1' on TIM_SERV in Register 0002h. Timing Enable - When `1', enables the operation of the Timing Reference Cell Sub-Module receive circuit for Adaptive Clock Recovery. Will always read 00h. Table 60 - Clock Module General Status Register Address: 6082 (Hex) Label: CMGSR Reset Value: 0000 (Hex) Label REFFAIL Bit Position 0 Type R/O/L Description Reference Clock Failure - Clock Generation Sub-Module. When `1', indicates that the REF8KCLK signal has failed. When this bit is `1' and the FREERUN bits in the Master Clock Generation Control Register (MCGCR at 6090h) are "01", the external signal FREERUN will be activated. MCLK should be at least 2048 times the REF8KCLK frequency for proper operation. Writing a `1' over this bit will clear it. SRTS Transmit Underrun - SRTS Sub-Module. When `1', indicates a slip underrun error has occurred in the SRTS transmit circuit. This means that the TX_SAR (scheduler) is sending RTSs faster than the SRTS Transmit Divider Register is generating them. Check the scheduler vs. registers 60B0h, and 60B2h. Can be ignored when SRTS transmission is not enabled. Writing a `1' over this bit will clear it. SRTS Transmit Overrun - SRTS Sub-Module. When `1', indicates a slip overrun error has occurred in the SRTS transmit circuit. This means that the SRTS Transmit Divider Register is generating RTSs faster than the TX_SAR (scheduler) is sending them. Check the scheduler vs. registers 60B0h, and 60B2h. Can be ignored when SRTS transmission is not enabled. Writing a `1' over this bit will clear it. SRTS Receive Underrun - SRTS Sub-Module. When `1', indicates a slip underrun error has occurred in the SRTS receive circuit. This means that the RX_SAR is receiving RTSs faster than the SRTS Transmit Divider Register is generating RTSs. Check registers 60B4h, and 60B6h. Can be ignored when SRTS reception is not enabled. Writing a `1' over this bit will clear it. SRTS Receive Overrun - SRTS Sub-Module. When `1', indicates a slip overrun error has occurred in the SRTS receive circuit. This means that the SRTS Transmit Divider Register is generating RTSs faster than the RX_SAR is receiving RTSs. Check registers 60B4h, and 60B6h. Can be ignored when SRTS reception is not enabled. Writing a `1' over this bit will clear it. Loss of Timing Reference Cell stream - Timing Reference Cell Sub-Module. When `1', indicates a loss of timing reference cells (or marker) event has occurred (loss period determined by Time-out field at 60A0h) while the Adaptive Clock Recovery state machine was enabled (TIM_ENA bit set in Clock Module General Control Register at 6080h). Writing a `1' over this bit will clear it. Out-Of-Sync - Timing Reference Cell Sub-Module. When `1', indicates the Timing Reference Cell state machine went out of sync. This bit is set only when the state machine initially goes out of sync - if it stays out of sync., this bit will be cleared. Writing a `1' over this bit will clear it. Will always read "000_0000_0". This bit is set if any of bits<6:0> are set. SRTST_UND 1 R/O/L SRTST_OVR 2 R/O/L SRTSR_UND 3 R/O/L SRTSR_OVR 4 R/O/L LOSS_TIMRF 5 R/O/L OUT_SYNC 6 R/O/L Reserved TIME_SERV 14:7 15 R/O R/O Note: Bits<6:0> will be set if the TESTS bit is set in the TDM Interface Control Register at 6000h. 105 MT90500 Table 61 - Master Clock Generation Control Register Address: 6090 (Hex) Label: MCGCR Reset Value: 00C0 (Hex) Label REFSEL Bit Position 1:0 Type R/W Description REF8KCLK (8 kHz Reference Clock) Selection. See Figure 3 on page 29. 00 -> MCLK/(DIVCLK + 2) or CLKx2/(DIVCLK + 2) (See register 6092h.) 01 -> RXVCLK (recovered ATM VC/SW clock. See register 60A8h.) 10 -> SEC8K input pin 11 -> EX_8KA input pin. Selects input clock for programmable divider (See register 6092h.) 0 -> MCLK 1 -> CLKx2 Select squared version of EX_8KA for output. 0 -> Pass EX_8KA signal without changes, 1 -> Convert EX_8KA input to square wave. This bit, when HIGH, selects the squared version of EX_8KA for routing to the REF8KCLK, and the SEK8K multiplexers. The squaring logic converts the EX_8KA input into a square wave (approximately 50% duty-cycle). This can convert a pulse 8 kHz signal into an 8 kHz square wave, for example. The rising edge of EX_8KA input is passed, without added jitter, to the REF8KCLK or SEC8K output as a falling edge (i.e. the signal is inverted); the rising edge at the REF8KCLK output will be 50% duty cycle with jitter equal to a cycle of MCLK. MCLK must be at least 10 times faster, and at most 16000 times faster, than EX_8KA. See Figure 3, "TDM Clock Selection and Generation Logic," on page 29. Enable SEC8K squaring logic. 0 -> Pass SEC8K signal without changes, 1 -> Convert SEC8K input to square wave. The squaring logic, when enabled, converts the SEC8K input into a square wave (approximately 50% duty-cycle) before passing it to the REF8KCLK multiplexer. This can convert a pulse 8 kHz signal into an 8 kHz square wave, for example. When REFSEL = "10" the rising edge of SEC8K input is passed, without added jitter, to the REF8KCLK output as a rising edge; the falling edge at the REF8KCLK output will be 50% duty cycle with jitter equal to a cycle of MCLK. MCLK must be at least 10 times faster, and at most 16000 times faster, than SEC8K. Clock Generator Multiplexer Selection: selects CLK16 input clock for the TDM Clock Generator. 0 -> MCLK 1 -> PLLCLK input. Clock Generator Division Factor. ("11" at reset) 00 -> 8 01 -> 1 10 -> 2 11 -> 4 Note: These bits provide the factor by which either MCLK or PLLCLK (as determined by BEPLL) is divided to provide a 16.384 MHz clock at the Main TDM Bus Clock Generation Logic. Clock Generator Phase Lock Enable. When this bit is `1', and TDMFS (in the TDM Bus Type Register at 6010h) is "00", the internal FSYNC signal generator will be slaved to the external FSYNC signal. This bit allows the MT90500 to be used as a Clock Master Alternate in SCSA mode (i.e. CLKALT = `1' and CLKMASTER = `0' in TDM Bus Type Register at 6010h). In this case, the stand-by clock master circuit (using CLK16, the local 16.384 MHz clock derived from PLLCLK or MCLK) tracks the external FSYNC signal so that when it is selected as a clock master after a clock failure, the new FSYNC will be almost in phase with the previous one. The phase-tracking is automatically disabled when the CLKFAIL input pin is asserted. When `1', the MT90500 drives the SEC8K external signal. When `0', the SEC8K pin is an input. SEC8K Clock Source Selection 0 -> EX_8KA 1 -> Internally generated 8 kHz reference (FS_INT) DIVCLK_SRC 2 R/W EX_8KA_SQ 3 R/W SEC8K_SQ 4 R/W BEPLL 5 R/W DIV1...8 7:6 R/W PHLEN 8 R/W SEC8KEN SEC8KSEL 9 10 R/W R/W 106 MT90500 Table 61 - Master Clock Generation Control Register Address: 6090 (Hex) Label: MCGCR Reset Value: 00C0 (Hex) Label FREERUN Bit Position 12:11 Type R/W Description Clock Failure Detection - FREERUN Signal Control 00 -> FREERUN is always activated (FREERUN pin is HIGH) 01 -> FREERUN is activated when status bit REFFAIL (in the Clock Module General Status Register at 6082h) is `1'. In the event of REF8KCLK clock failure, it is the software's responsibility to change the programming from "01" to "00" before clearing the REFFAIL status bit. 1X -> FREERUN is always deactivated (FREERUN pin is LOW) Reserved. Should be written as "000". Reserved 15:13 R/W Refer to Figure 3, "TDM Clock Selection and Generation Logic," on page 29 for more detailed information regarding the implementation of the selection bits. Table 62 - Master Clock / CLKx2 Division Factor Address: 6092 (Hex) Label: MCDF Reset Value: 2000 (Hex) Label DIVCLK Bit Position 13:0 Type R/W Description This value plus two is used to divide MCLK or CLKx2 to get an 8 kHz reference. Value 0000h means divide-by-two, 0001h means divide-by-three, ..., 3FFEh means divide-by16,384. Reserved. Should be written as "00". Reserved 15:14 R/W Table 63 - Timing Reference Processing Control Register Address: 60A0 (Hex) Label: TRPCR Reset Value: 0001 (Hex) Label Time-out Bit Position 9:0 Type R/W Description This value is used to indicate a time-out period, after which if no timing reference cells or markers have been received, a Loss of Timing Reference Cells (LOSS_TIMRF in 6082h) event will be indicated. The time-out period is calculated in multiples of 65536 MCLK periods. "00_0000_0000" is an illegal value (i.e. time-out is a minimum of 65536 cycles of MCLK). When `0', indicates that clock recovery is based on Timing Reference Cell arrival events. When `1', indicates that clock recovery is based on 8 kHz marker arrival events. When `1', enable CRC and parity checking on AAL1 sequence number field in state machine. See Figure 31 on page 70. Reserved. Should be written as "0000". Cell / 8 kHz Seq_CRC_Ena Reserved 10 11 15:12 R/W R/W R/W 107 MT90500 Table 64 - Event Count Register Address: 60A2 (Hex) Label: EVCR Reset Value: 0000 (Hex) Label Event_Cnt Bit Position 15:0 Type R/O Description This register keeps a running count of the reception of timing reference cells or 8 kHz markers (as determined by setting of Cell / 8 kHz bit in register 60A0h). The contents of this register are locked when a `1' is written to the CNTUPDATE bit in the Clock Module General Control Register (6080h). Thus CNTUPDATE should be set just prior to reading this register. See Figure 31, "Adaptive Clock Recovery Sub-Module (Simplified Functional Block Diagram)," on page 70 for more details. Table 65 - CLKx1 Count - Low Register Address: 60A4 (Hex) Label: C1CRL Reset Value: 0000 (Hex) Label CLKx1_Cnt_L Bit Position 15:0 Type R/O Description This register represents the low portion of a 24-bit counter which keeps a running count of CLKx1 * 8 periods (i.e. every 8 cycles of CLKx1, a counter is incremented). The counter is updated at the same time the Event Count Register (60A2h) is incremented. The contents of this register are locked when a `1' is written to the CNTUPDATE bit in the Clock Module General Control Register (6080h). This should be done just prior to reading this register. See Figure 31, "Adaptive Clock Recovery Sub-Module (Simplified Functional Block Diagram)," on page 70 for more details. Table 66 - CLKx1 Count - High Register Address: 60A6 (Hex) Label: C1CRH Reset Value: 0000 (Hex) Label CLKx1_Cnt_H Bit Position 7:0 Type R/O Description This register represents the high portion of a 24-bit counter which keeps a running count of CLKx1 * 8 periods (i.e. every 8 cycles of CLKx1, a counter is incremented). The counter is updated at the same time the Event Count Register (60A2h) is incremented. The contents of this register are locked when a `1' is written to the CNTUPDATE bit in the Clock Module General Control Register (6080h). This should be done just prior to reading this register. See Figure 31, "Adaptive Clock Recovery Sub-Module (Simplified Functional Block Diagram)," on page 70 for more details. Unused. Always read 00h. Reserved 15:8 R/O 108 MT90500 Table 67 - DIVX Register Address: 60A8 (Hex) Label: DIVX Reset Value: 2000 (Hex) Label DIVX Bit Position 13:0 Type R/W Description This value is used (along with DIVXN, in the next register) to divide MCLK to obtain an RXVCLK reference. The average frequency of RXVCLK is obtained as follows: 1 ---------RXVCLKavg = MCLK x ------------------------------------------------------------------------------------------------------------------------------- ( DIVX + 2 ) ( DIVXN ) + ( DIVX + 3 ) x ( 4096 - DIVXN ) ------------------------------------------------------------------------------------------------------------------------------- ---------4096 Note that when a new RXVCLK setting requires a change to this register and to the DIVX Ratio Register, these two writes should be performed as closely together as possible. This is required to prevent drifting of the REF8KCLK output frequency during the period that one register has been updated but the other hasn't. Reserved 15:14 R/W Reserved. Should be written as "00". Table 68 - DIVX Ratio Register Address: 60AA (Hex) Label: DIVXR Reset Value: 0FFF (Hex) Label DIVXN Bit Position 11:0 Type R/W Description This value defines how many times MCLK will be divided by (DIVX + 2) and how many times it will be divided by (DIVX + 3), as per the formula shown in 60A8h above. When 001h, MCLK is divided by (DIVX + 2) once, then divided 4095 times by (DIVX + 3). Note: 0 is an illegal value for DIVXN (same ratio as 1) Reserved. Should be written as "0000". Reserved 15:12 R/W Table 69 - SRTS Transmit Gapping Divider Register Address: 60B0(Hex) Label: SRTGD Reset Value: 0000 (Hex) Label TX_Gapping Bit Position 7:0 Type R/W Description This field provides the separation between consecutive pulses of the fB clock. This field should be set according to the following formula: (256 / number of channels per VC) - 1. The result must be rounded down. 1 channel -> 255 2 channels -> 127 3 channels -> 84 ... Number of channels in the VC that is selected for transmitting the SRTS. 0h -> 1 channel 1h -> 2 channels ... 79h -> 122 channels Note: Since maximum number of channels per VC is 122, values 7A:7F are reserved. Reserved. Should be written as `0'. TX_Ch_per_VC 14:8 R/W Reserved 15 R/W 109 MT90500 Table 70 - SRTS Transmit Byte Counter Register Address: 60B2(Hex) Label: SRTBC Reset Value: 0177 (Hex) Label Byte Number Bit Position 8:0 Type R/W Description Number of TDM payload bytes in eight (8) consecutive cells. For pointerless AAL1 Structured Data Transfer (i.e. n=1 SDT), this value is 376. For AAL1 SDT (n not equal to 1), this value is normally 375 (although it may be 374, or 372, depending on the number of P-bytes sent in each 8-cell sequence). Always read "0000_000" Reserved 15:9 R/O Table 71 - SRTS Receive Gapping Divider Register Address: 60B4(Hex) Label: SRRGD Reset Value: 0000 (Hex) Label RX_Gapping Bit Position 7:0 Type R/W Description This field provides the separation between consecutive pulses of the fB clock. This field should be set according to the following formula: (256 / number of channels per VC) - 1. The result must be rounded down. 1 channel -> 255 2 channels -> 127 3 channels -> 84 ... Number of channels in the VC that is selected for receiving the SRTS. 0 -> 1 channel 1 -> 2 channels ... Note: Since maximum number of channels per VC is 122, values 7A:7F are reserved. Reserved. Should be written as `0'. RX_Ch_per_VC 14:8 R/W Reserved 15 R/W Table 72 - SRTS Receive Byte Counter Register Address: 60B6(Hex) Label: SRRBC Reset Value: 0177 (Hex) Label Byte Number Bit Position 8:0 Type R/W Description Number of TDM payload bytes in eight (8) consecutive cells. For pointerless AAL1Structured Data Transfer (i.e. n=1 SDT), this value is 376. For AAL1 SDT (n not equal to 1), this value is normally 375 (although it may be 374, or 372, depending on the number of P-bytes sent in each 8-cell sequence). Always read "0000_000" Reserved 15:9 R/O 110 MT90500 5.2.6 TDM Time Slot Control Table 73 - Output Enable Registers Address: 7000 + 2N (Hex) - N=0,1,2,...,127 Label: OEM Reset Value: XXXX (Hex) Label OE Bit Position 15:0 Type R/W Description Output Enable for 16 time slots - When HIGH, these bits enable the corresponding time slots to be driven onto the TDM bus. <0> OE for stream 0 <1> OE for stream 1 <2> OE for stream 2 ........ <14> OE for stream 14 <15> OE for stream 15 Each register represents a particular time slot (e.g. 7000h => time slot 0; 70FEh => time slot 127). Within each register, the individual bits correspond to the ST-BUS streams, as listed above. 111 MT90500 6. 6.1 Electrical Specification DC Characteristics Table 74 - Absolute Maximum Ratings Parameter Symbol VDD5 VDD3 VI/O VI/O3 IIN IO TS PD - 40 Min - 0.3 - 0.3 VSS - 0.5 VSS - 0.5 Max 6.5 3.9 VDD5 + 0.3 VDD3 + 0.3 10 24 + 125 4 Units V V V V mA mA C W 1 2 3 4 5 6 7 8 Supply Voltage - 5 Volt Rail Supply Voltage - 3.3 Volt Rail Voltage on any I/O pin (except TRISTATE) Voltage on TRISTATE pin Continuous current at digital inputs Continuous current at digital outputs Storage Temperature Package power dissipation (PQFP) * Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage measurements are with respect to ground (VSS) unless otherwise stated. Table 75 - Recommended Operating Conditions Characteristics 1 2 3 4 5 6 Operating Temperature Supply Voltage, 5 Volt Rail Supply Voltage, 3.3 Volt Rail Input Voltage Low - all inputs Input Voltage High - TTL & 3V CMOS inputs Input Voltage High - TRISTATE input Sym TOP VDD5 VDD3 Min - 40 4.75 3.13 VSS 2.4 2.4 5.0 3.3 Typa Max + 85 5.25 3.46 0.4 VDD5 3.6 Units C V V V V V VDD3 = 3.3 V Test Conditions a. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Voltage measurements are with respect to ground (VSS) unless otherwise stated. Table 76 - DC Characteristics Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 Supply Current - 3.3 V supply Supply Current - 5 V supply Input High Voltage (3V CMOS) Input Low Voltage (3V CMOS) Switching Threshold (3V CMOS) Input High Voltage (TTL) Input Low Voltage (TTL) Switching Threshold (TTL) Schmitt Trigger Positive Threshold Schmitt Threshold Trigger Negative Sym IDD3 IDD5 Min Typa 400 1 0.7 x VDD3 2.3 0.7 0.5 x VDD3 2.0 VSS - 0.5 1.4 1.7 0.8 0.6 1.0 0.7 + 0.5 5.5 0.8 2.0 2.0 0.2 x VDD3 Max 500 Units mA mA V V V V V V V V V V CLKx2PI - CLKx2NI Test Conditions b 60 MHz, Outputs unloaded Outputs unloaded VIHC VILC VTC VIH VIL VTT Vt+ VtVtH VIHD Schmitt Trigger Hysteresis Differential Input High Voltage 112 MT90500 Table 76 - DC Characteristics Characteristics 13 14 Differential Input Low Voltage Input Leakage Current Inputs with pull-down resistors Inputs with pull-up resistors 15 16 17 18 19 Input Pin Capacitance Output HIGH Voltage Output LOW Voltage High Impedance Leakage Output Pin Capacitance Sym VILD IIL / IIH IIH IIL CI 69 - 70 Min Typa - 0.5 1 124 - 142 10 190 - 225 10 2.4 3.3 0.2 -10 1.0 VDDX 0.4 +10 10 Max Units V A A A pF V V A pF IOH = rated current (4 or 12 mA) IOL = rated current (4 or 12 mA) VO = VSS or VDD Test Conditions b CLKx2PI - CLKx2NI VIN = VDDx or Vss VIN = VDD5 VIN = Vss VOH VOL IOZ CO a. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. b. TOP = -40C to 85C; VDD5 = 5V 5%; VDD3 = 3.3V 5% Voltage measurements are with respect to ground (VSS) unless otherwise stated. Precautions During Power Sequencing Latch-up is not a concern during power sequencing. There is no requirement for sequencing 3.3 V and 5 V supplies during power up. However, to minimize over-voltage stress during system start-up, the 3.3 V supply applied to the MT90500 should be brought to a level of at least VDD = 3.0 V before a signal line is driven to a level greater than or equal to 3.3 V. This practice can be implemented either by ensuring that the 3.3 V power turns on simultaneously with or before the system 5 V supply turns on, or by ensuring that all 5 V signals are held to a logic LOW state during the time that VDD < 3.0 V. Regardless of the method chosen to limit overvoltage stress during power up, exposure must be limited to no more than + 6.5 V input voltage (VIN). The TRISTATE pin of the MT90500 can be asserted low on power-up to prevent bus contention. Precautions During Power Failure Latch-up is not a concern in power failure mode. Although extended exposure of the MT90500 to 5 V signals during 3.3 V supply power failure is not recommended, there are no restrictions as long as VIN does not exceed the absolute maximum rating of 6.5 V. To minimize over-voltage stress during a 3.3 V power supply failure, the designer should either link the power supplies to prevent this condition or ensure that all 5 V signals connected to the MT90500 are held in a logic LOW state until the 5 V supply is deactivated. Pull-ups Pull-ups from the 5V rail to 3.3V (5V tolerant) outputs of the MT90500 can cause reverse leakage currents into those 3.3V outputs when they are active HIGH. (No significant reverse current is present during the high impedance state.) If the application can put the MT90500 in a state where MCLK is stopped, and a large number of 3.3V output buffers are held in a static HIGH state, current can flow from the 5V rail to the 3.3V rail. If this MCLK-stopped state can not be avoided, the user should determine if the total MT90500 reverse current will have a negative impact on the system 3.3V power supply. Alternatively, the TRISTATE pin of the MT90500 can be asserted low to put all outputs in the high impedance state. 113 MT90500 6.2 6.2.1 AC Characteristics Main TDM Bus CLKx2PO VTT CLKx1 VTT FSYNC (neg.) VTT FSYNC (pos.) VTT STi/o Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 VTT Figure 39 - Nominal TDM Bus Timing Table 77 - Main TDM Bus Output Clock Parameters Characteristic Clock Skew - CLKx2PO falling to CLKx1 change Sym tSK Min Typ Max 10 20 CLKx2PO - Output Clock Period 2.048 Mbps bus (4.096 MHz clock) 4.096 Mbps bus (8.192 MHz clock) 8.192 Mbps bus (16.384 MHz clock) CLKx2PO Pulse Width (HIGH / LOW) 2.048 Mbps bus (4.096 MHz clock) 4.096 Mbps bus (8.192 MHz clock) 8.192 Mbps bus (16.384 MHz clock) CLKx1 - Output Clock Period 2.048 Mbps 4.096 Mbps 8.192 Mbps CLKx1 Pulse Width (HIGH / LOW) 2.048 Mbps 4.096 Mbps 8.192 Mbps Frame Pulse Width Positive Frame Pulse - 2.048 Mbps Negative Frame Pulse - 2.048 Mbps Positive Frame Pulse - 4.096 Mbps Negative Frame Pulse - 4.096 Mbps Positive Frame Pulse - 8.192 Mbps Negative Frame Pulse - 8.192 Mbps Frame Pulse Delay Positive: CLKx2PO falling to FSYNC rising Negative: CLKx2PO rising to FSYNC falling tCx2P 244 122 61 tCx2H/L 118 57 26.5 tCx1P 488 244 122 tCx1H/L 240 118 57 tFPW 488 244 244 122 122 61 tFPD 0 -2 0 -2 10 20 10 20 ns ns ns ns CL = 50 pF CL = 200 pF CL = 50 pF CL = 200 pF ns ns ns ns ns ns 244 122 61 248 126 65 ns ns ns ns ns ns 16.39 MHz (61 ns) input clock. 122 61 30.5 126 65 34.5 ns ns ns ns ns ns 16.39 MHz (61 ns) input clock with 50/50 duty cycle. Units ns ns Test Conditions CL = 50 pF CL = 200 pF 16.39 MHz (61 ns) input clock. 114 MT90500 tFPW FSYNC tFPD CLKx2PO tSK CLKx1 tCx1P tCx1H tCx1L VTT tCx2P tCx2H tCx2L VTT VTT tSODD STo Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT Figure 40 - Main TDM Bus Output Clocking Parameters - Positive Frame Pulse tFPW FSYNC tCx2P tCx2H tCx2L VTT tSK CLKx1 tSODD STo Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT tFPD CLKx2PO tCx1P tCx1L tCx1H VTT VTT Figure 41 - Main TDM Bus Output Clocking Parameters - Negative Frame Pulse NOTE: Some SCSA devices may require a wider frame pulse at 4 Mbps and at 8 Mbps than the MT90500 provides. Also, H-MVIP uses a 488 ns wide frame pulse at 8 Mbps. 115 MT90500 Table 78 - Main TDM Bus Data Output Parameters Characteristic STo Delay - Data to Data Change CLKx1 rising and (STo HIGH or STo LOW) to STo change Fast Bus Slow Bus STo Delay - Data to Data Valid CLKx1 rising and (STo HIGH or STo LOW) to (STo LOW or STo HIGH) Fast Bus Slow Bus Drive to High-Z CLKx1 rising and STo VALID to STo HIGH-Z Fast Bus Slow Bus High-Z to Drive CLKx1 rising and STo HIGH-Z to STo change Fast Bus Slow Bus High-Z to Data Valid CLKx1 rising and STo HIGH-Z to STo VALID Fast Bus Slow Bus tSODZ tSODD Sym tSODX Min Typ Max Units Test Conditions 5 10 5 15 ns ns ns ns CL = 50 pF CL = 200 pF CL = 50 pF CL = 200 pF 31 41 52 62 ns ns ns ns CL = 50 pF CL = 200 pF CL = 50 pF CL = 200 pF CL = 200 pF 20 20 tSOZX ns ns CL = 200 pF 5 10 tSOZD ns ns CL = 200 pF 41 62 ns ns CLKx1 tSODX STo1 Valid Data VTT tSODD Valid Data Valid Data Valid Data VTT tSOZX tSODZ STo2 Valid Data High-Z High-Z Valid Data VTT tSOZD Figure 42 - Main TDM Bus - Serial Output Timing 116 MT90500 Table 79 - Main TDM Bus Input Clock Parameters Characteristic Clock Skew - CLKx2 falling to CLKx1 change CLKx2 - Input Clock Period 2.048 Mbps bus (4.096 MHz clock) 4.096 Mbps bus (8.192 MHz clock) 8.192 Mbps bus (16.384 MHz clock) CLKx2 Input Pulse Width (HIGH / LOW) 2.048 Mbps bus (4.096 MHz clock) 4.096 Mbps bus (8.192 MHz clock) 8.192 Mbps bus (16.384 MHz clock) CLKx1 - Input Clock Period 2.048 Mbps 4.096 Mbps 8.192 Mbps CLKx1 Pulse Width (HIGH / LOW) 2.048 Mbps 4.096 Mbps 8.192 Mbps PLLCLK - Input Clock Period 16.384 MHz PLLCLK Pulse Width (HIGH / LOW) 16.384 MHz Frame Pulse Setup Time FSYNC valid to CLKx2 falling (TCLKSYN = 1) FSYNC valid to CLKx1 rising (negative FSYNC) FSYNC valid to CLKx1 falling (positive FSYNC) Frame Pulse Hold Time CLKx2 falling to FSYNC invalid (TCLKSYN = 1) CLKx1 rising to FSYNC invalid (negative FSYNC) CLKx1 falling to FSYNC invalid (positive FSYNC) Sym tFSK tCx2P 244 122 61 tCx2H/L 97.6 48.8 26.2 tCx1P 488 244 122 tCx1H/L 195.2 97.6 48.8 tPLL 61 tPLLH/L 26.2 tFIS 5 5 5 tFIH 10 10 10 ns ns 30.5 34.8 ns MT90500 is TDM Timing Bus Slave. ns 244 122 61 292.8 146.4 73.2 ns ns ns ns ns ns 16.39 MHz (61 ns) input clock. 122 61 30.5 146.4 73.2 34.8 ns ns ns ns ns ns 16.39 MHz (61 ns) input clock with 50/50 duty cycle. Min Typ Max 10 Units ns Test Conditions MT90500 is TDM Timing Bus Slave. Table 80 - Main TDM Bus Input Data Parameters Characteristic STi Setup Time - STi VALID to CLKx1 falling 2/4 Sampling STi Hold Time - CLKx1 falling to STi INVALID 2/4 Sampling STi Setup Time - STi VALID to CLKx2 rising 3/4 Sampling STi Hold Time - CLKx2 rising to STi INVALID 3/4 Sampling STi Setup Time - STi VALID to CLKx1 rising 4/4 Sampling STi Hold Time - CLKx1 rising to STi INVALID 4/4 Sampling Sym tSIS 5 tSIH 10 tSIS 5 tSIH 10 tSIS 5 tSIH 10 ns ns ns ns ns ns Min Typ Max Units Test Conditions 117 MT90500 tFIS FSYNC tFIH VTT CLKx2 VTT CLKx1 tSIS tSIH STi Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT VTT STo Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT Figure 43 - Main TDM Bus - 2/4 Sampling tFIS FSYNC tFIH VTT CLKx2 VTT CLKx1 tSIS tSIH STi Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT VTT STo Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT Figure 44 - Main TDM Bus - 3/4 Sampling 118 MT90500 tFIS FSYNC tFIH VTT CLKx2 VTT CLKx1 tSIS STi Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 VTT tSIH Bit 6, Channel 0 VTT STo Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT Figure 45 - Main TDM Bus - 4/4 Sampling 119 MT90500 6.2.2 Local TDM Bus Table 81 - Local TDM Bus Clock Parameters Characteristic Clock Skew - LOCx2 falling to LOCx1 change LOCx2 Period LOCx2 Pulse Width (HIGH / LOW) LOCx1 Period LOCx1 Pulse Width (HIGH / LOW) Frame Pulse Width Positive Frame Pulse Negative Frame Pulse Frame Pulse Delay Positive: LOCx2 falling to LSYNC rising Negative: LOCx2 rising to LSYNC falling Frame Pulse Guaranteed Setup Positive: LSYNC rising to LOCx2 falling Negative: LSYNC falling to LOCx2 falling Frame Pulse Guaranteed Hold Positive: LOCx2 falling to LSYNC falling Negative: LOCx2 falling to LSYNC rising Sym tLSK tLx2P tLx2H/L tLx1P tLx1H/L tLSW 488 244 tLSD 0 0 tLSS 220 98 tLSH 230 108 ns ns ns ns 10 10 ns ns Input clock = 16.39 MHz (61 ns) CL = 50 pF Input clock = 16.39 MHz (61 ns) CL = 50 pF ns ns CL = 50 pF 241 119 244 122 488 244 247 125 Min Typ Max 10 Units ns ns ns ns ns Input clock = 16.39 MHz (61 ns) Test Conditions CL = 50 pF Note: The local bus operates at 2.048 Mbps only. Table 82 - Local TDM Bus Data Output Parameters Characteristic LOCSTo Delay - Data to Data Change LOCx1 rising and ((LOCSTo HIGH to LOCSTo LOW) or (LOCSTo LOW to LOCSTo HIGH)) LOCSTo Delay - Data to Data Valid LOCx1 rising and ((LOCSTo HIGH to LOCSTo LOW) or (LOCSTo LOW to LOCSTo HIGH)) Sym tLODX Min 5 Typ Max Units ns Test Conditions CL = 50 pF tLODD 60 ns CL = 50 pF Note 1: The local bus output is never high impedance, as data is always driven out on LOCSTo. Note 2: There is no differentiation between fast bus and slow bus on the local bus. 120 MT90500 tLSW LSYNC tLSS tLSD LOCx2 tLSK LOCx1 tLx1P tLx1H tLx1L VTT tLSH tLx2P tLx2H tLx2L VTT VTT tLODD LOCSTo Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 tLODX Bit 6, Channel 0 Bit 5, Channel 0 VTT Figure 46 - Local TDM Bus Output Parameters - Positive Frame Pulse tLSW LSYNC tLSS tLSD LOCx2 tLSK LOCx1 tLODD LOCSTo Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT tLSH tLx2P tLx2H tLx2L VTT tLx1P tLx1L tLx1H VTT tLODX VTT Figure 47 - Local TDM Bus Output Parameters - Negative Frame Pulse 121 MT90500 Table 83 - Local TDM Bus Data Input Parameters Characteristic LOCSTi Setup Time - LOCSTi VALID to LOCx1 falling 2/4 Sampling LOCSTi Hold Time - LOCx1 falling to LOCSTi INVALID 2/4 Sampling LOCSTi Setup Time - LOCSTi VALID to LOCx2 rising 3/4 Sampling LOCSTi Hold Time - LOCx2 rising to LOCSTi INVALID 3/4 Sampling LOCSTi Setup Time - LOCSTi VALID to LOCx1 rising 4/4 Sampling LOCSTi Hold Time - LOCx1 rising to LOCSTi INVALID 4/4 Sampling Sym tLIS 10 tLIH 10 tLIS 10 tLIH 5 tLIS 10 tLIH 5 ns ns ns ns ns ns Min Typ Max Units Test Conditions LSYNC VTT LOCx2 VTT LOCx1 tLIS tLIH LOCSTi Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT VTT LOCSTo Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT Figure 48 - Local TDM Bus - Positive Frame Pulse, 2/4 Sampling 122 MT90500 LSYNC VTT LOCx2 VTT LOCx1 tLIS LOCSTi Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 VTT tLIH Bit 6, Channel 0 Bit 5, Channel 0 VTT LOCSTo Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT Figure 49 - Local TDM Bus - Negative Frame Pulse, 3/4 Sampling LSYNC VTT LOCx2 VTT LOCx1 tLIS LOCSTi Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 VTT tLIH Bit 6, Channel 0 VTT LOCSTo Bit 1, Last Channel Bit 0, Last Channel Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 VTT Figure 50 - Local TDM Bus - Negative Frame Pulse, 4/4 Sampling 123 MT90500 6.2.3 CPU Interface - Accessing Registers and External Memory Table 84 - Intel Microprocessor Interface Timing - Read Cycle Parameters Characteristic Address Setup - (AEM and A[15:1] VALID) to (CS and RD asserted) Address Hold - (CS or RD deasserted) to (AEM and A[15:1] INVALID) RDY De-asserted - (CS and RD asserted) to RDY de-asserted RDY Delay - (CS and RD asserted) to RDY asserted Data Output Setup - D[15:0] VALID to RDY asserted Data Output Hold - (CS or RD deasserted) to D[15:0] INVALID Sym tADDS 0 tADDH 0 tRDY 21 tRDYD 100 tDS 15 tDH 3 15 ns ns 360 1000 ns ns ns 1) ~ 1 MCLK cycle + 4 ns 2) CL = 50 pF 1) 6 MCLK < tRDYD < 60 MCLK 2) CL = 50 pF 1) ~ 1 MCLK cycle - 1 ns 2) CL = 50 pF 1) Min. measurement is to D[15:0] INVALID; max. measurement is to D[15:0] high-impedance 2) CL = 50 pF ns Min Typ Max Units Test Conditions Note 1: MCLK = 60 MHz (16.6 ns). Note 2: Both CS and RD must be asserted for a read cycle to occur. A read cycle is completed when either CS or RD is de-asserted. Note 3: There should be a minimum of 4 MCLK periods between CPU accesses, to allow the MT90500 to recognize the accesses as separate. RD VTT CS VTT WR tADDH ADDRESS VALID VTT tADDS A[15:1] AEM tRDY RDY tRDYD VTT VTT tDS tDH DATA VALID VTT D[15:0] Figure 51 - Intel CPU Interface Timing - Read Access 124 MT90500 Table 85 - Intel Microprocessor Interface Timing - Write Cycle Parameters Characteristic Address Setup - (AEM and A[15:1] VALID) to (CS and WR asserted) Address Hold - (CS or WR deasserted) to (AEM and A[15:1] INVALID) RDY De-asserted - (CS and WR asserted) to RDY de-asserted RDY Delay - (CS and WR asserted) to RDY asserted Write Cycle Hold Time - RDY asserted to (CS or WR de-asserted) Data Input Setup - D[15:0] VALID to (CS and WR asserted) Data Input Hold - (CS or WR deasserted) to D[15:0] INVALID Sym tADDS 0 tADDH 0 tRDY 21 tRDYD 100 tWRH 0 tDS 0 tDH 0 ns ns ns 415 1000 ns ns ns 1) ~ 1 MCLK cycle + 4 ns 2) CL = 50 pF 1) 6 MCLK < tRDYD < 60 MCLK 2) CL = 50 pF ns Min Typ Max Units Test Conditions Note 1: MCLK = 60 MHz (16.6 ns). Note 2: Both CS and WR must be asserted for a write cycle to occur. A write cycle is completed when either CS or WR is de-asserted. Note 3: There should be a minimum of 4 MCLK periods between CPU accesses, to allow the MT90500 to recognize the accesses as separate. tRDYD tWRH WR VTT CS VTT RD tADDH ADDRESS VALID VTT tADDS A[15:1] AEM tRDY RDY VTT VTT tDH DATA VALID VTT tDS D[15:0] Figure 52 - Intel CPU Interface Timing - Write Access 125 MT90500 Table 86 - Motorola Microprocessor Interface Timing - Read Cycle Parameters Characteristic Address Setup - (R/W, AEM and A[15:1] VALID) to (CS and DS asserted) Address Hold - (CS or DS deasserted) to (AEM, A[15:1] and R/W INVALID) DTACK High - (CS and DS asserted) to DTACK driving one DTACK Delay - (CS and DS asserted) to DTACK asserted Data to DTACK Delay - D[15:0] VALID to DTACK asserted DTACK Hold - (CS or DS de-asserted) to DTACK driving high DTACK High-Impedance - (CS or DS de-asserted) to DTACK highimpedance Data Output Hold - (CS or DS deasserted) to D[15:0] INVALID Sym tADDS 0 tADDH 0 tDTK1 34 tDTKD 100 tDDTK 14 tDTKH 5 tDTKZ 6 tDH 3 15 ns 20 ns 1) Min. measurement is to D[15:0] INVALID; max. measurement is to D[15:0] high-impedance 2) CL = 50 pF 15 ns CL = 50 pF ns 375 1000 ns ns ns 1) ~ 2 MCLK cycles 2) CL = 50 pF 1) 6 MCLK < tRDYD < 60 MCLK 2) CL = 50 pF 1) ~ 1 MCLK cycle - 2 ns 2) CL = 50 pF CL = 50 pF ns Min Typ Max Units Test Conditions Note 1: MCLK = 60 MHz (16.6 ns). Note 2: Both CS and DS must be asserted for a read cycle to occur. A read cycle is completed when either CS or DS is de-asserted. Note 3: There should be a minimum of 4 MCLK periods between CPU accesses, to allow the MT90500 to recognize the accesses as separate. tDTKD DS VTT CS tDTKZ tDTKH DTACK tDTK1 tADDS A[15:1] AEM ADDRESS VALID tADDH R/W tDDTK D[15:0] DATA VALID tADDH VTT VTT VTT VTT tDH VTT Figure 53 - Motorola CPU Interface Timing - Read Access 126 MT90500 Table 87 - Motorola Microprocessor Interface Timing - Write Cycle Parameters Characteristic Address Setup - (R/W, AEM and A[15:1] VALID) to (CS and DS asserted) Address Hold - (CS or DS de-asserted) to (AEM, A[15:1] and R/W INVALID) DTACK High - (CS and DS asserted) to DTACK driving one DTACK Delay - (CS and DS asserted) to DTACK asserted DTACK Hold - (CS or DS de-asserted) to DTACK driving high DTACK High-Impedance - (CS or DS de-asserted) to DTACK high-impedance Data Input Setup - D[15:0] VALID to (CS and DS asserted) Data Input Hold - (CS or DS deasserted) to D[15:0] INVALID Sym tADDS 0 tADDH 0 tDTK1 34 tDTKD 100 tDTKH 5 tDTKZ 6 tDS 0 tDH 0 ns ns CL = 50 pF 20 ns CL = 50 pF 15 ns CL = 50 pF 420 1000 ns ns ns 1) ~ 2 MCLK cycles 2) CL = 50 pF 1) 6 MCLK < tRDYD < 60 MCLK 2) CL = 50 pF CL = 50 pF ns Min Typ Max Units Test Conditions Note 1: MCLK = 60 MHz (16.6 ns). Note 2: Both CS and DS must be asserted for a write cycle to occur. A write cycle is completed when either CS or DS is de-asserted. Note 3: There should be a minimum of 4 MCLK periods between CPU accesses, to allow the MT90500 to recognize the accesses as separate. tDTKD DS VTT CS tDTKZ tDTKH DTACK tDTK1 tADDS A[15:1] AEM ADDRESS VALID tADDH R/W tADDH VTT VTT VTT VTT tDS D[15:0] DATA VALID tDH VTT Figure 54 - Motorola CPU Interface Timing - Write Access 127 MT90500 6.2.4 Interface with External Memory Table 88 - MCLK - Master Clock Input Parameters Characteristic MCLK Frequency MCLK Period MCLK Pulse Width (HIGH / LOW) Sym tMF tMP tMH/L 7.5 Min Typ 60 16.7 8.33 Max 60.006 Units MHz ns ns Test Conditions Table 89 - External Memory Interface Timing - Clock Parameters Characteristic MEMCLK Period MEMCLK Pulse Width (HIGH / LOW) Sym tMEMP tMEMH/ L Min Typ 16.7 Max Units ns Test Conditions MEMCLK = MCLK = 60 MHz MCLK = 16.7 ns period, 50/50 duty cycle MCLK = 16.7 ns period, 45/55 duty cycle 7.6 6.7 8.33 8.33 9.1 10.0 ns ns Table 90 - External Memory Interface Timing - Read Cycle Parameters Characteristic Data Input Setup - (MEM_DAT[31:0] and MEM_PAR[3:0] VALID) to MEMCLK rising Data Input Hold Time - MEMCLK rising to (MEM_DAT[31:0] and MEM_PAR[3:0] INVALID) Output Delay - MEMCLK rising to (MEM_ADD[17:0] VALID and MEM_CS[1:0][H/ L] and MEM_WR[3:0] asserted) Output Hold Time - MEMCLK rising to (MEM_ADD[17:0] INVALID and MEM_CS[1:0][H/L] and MEM_WR[3:0] deasserted) Sym tDIS tDIH Min 5 1 Typ Max Units ns ns Test Conditions tOD 10 ns CL = 50 pF tOH 1.5 ns CL = 50 pF Note: MEM_OE is continuously asserted low after reset. Table 91 - External Memory Interface Timing - Write Cycle Parameters Characteristic Output Delay - MEMCLK rising to (MEM_ADD[17:0], MEM_DAT[31:0] and MEM_PAR[3:0] VALID) and (MEM_CS[1:0][H/ L] and MEM_WR[3:0] asserted) Output Hold Time - MEMCLK rising to (MEM_ADD[17:0], MEM_DAT[31:0] and MEM_PAR[3:0] INVALID) and (MEM_CS[1:0][H/L] and MEM_WR[3:0] deasserted) High-Z to Drive Time - MEMCLK rising to (MEM_DAT[31:0] and MEM_PAR[3:0] change) Drive to High-Z Time - MEMCLK rising to (MEM_DAT[31:0] and MEM_PAR[3:0] High-Z) Sym tOD Min Typ Max 11 Units ns Test Conditions CL = 50 pF tOH 1.5 ns CL = 50 pF tZD tOZ 1 5 ns ns CL = 50 pF Minimum hold in High-Z Note: MEM_OE is continuously asserted low after reset. 128 MT90500 MCLK tMEMP MEMCLK tMEMH tMEML VTT VTT MEM_ADD [17:0] ADDRESS1 VALID tOD ADDRESS2 VALID tOH VTT MEM_CS0H/L MEM_CS1H/L tOD VTT tOH MEM_WR[3:0] tDIS MEM_DAT[31:0] MEM_PAR[3:0] tDIH VTT DATA1 VALID DATA2 VALID VTT MEM_OE VTT Figure 55 - External Memory Interface Timing - Read Cycle 129 MT90500 MCLK tMEMP MEMCLK tMEMH tMEML VTT VTT MEM_ADD [17:0] tOD ADDRESS VALID tOH VTT MEM_CS0H/L MEM_CS1H/L tOD tOH VTT MEM_WR[3:0] tOD tOH VTT MEM_DAT[31:0] MEM_PAR[3:0] tZD tOD DATA VALID VTT tOH MEM_OE VTT Figure 56 - External Memory Interface Timing - Write Cycle 130 MT90500 6.2.5 6.2.5.1 UTOPIA Interfaces Primary UTOPIA Interface Table 92 - Primary UTOPIA Interface Parameters - Transmit Characteristic PTXCLK Period PTXCLK Pulse Width (HIGH / LOW) Input Setup Time - PTXCLAV VALID to PTXCLK rising Input Hold Time - PTXCLK rising to PTXCLAV de-asserted Output Delay - PTXCLK rising to (PTXDATA[7:0] VALID and PTXEN and PTXSOC asserted) Output Hold Time - PTXCLK rising to (PTXDATA[7:0] INVALID and PTXEN and PTXSOC de-asserted) Sym tPTXP tPTXH/L tPTXIS tPTXIH tPTXD 16 10 1 20 Min Typ 40 20 24 Max Units ns ns ns ns ns CL = 50 pF Test Conditions PTXCLK = 25 MHz tPTXH 1 ns CL = 50 pF Note 1: The MT90500 operates with the UTOPIA cell-level handshake. Note 2: The MT90500 always inserts 1-4 idle cycles between cells on the TX UTOPIA port. tPTXP PTXCLK tPTXIH tPTXLtPTXH VTT tPTXIS PTXCLAV at least 4 cycles before the next cell VTT tPTXH VTT tPTXD PTXEN tPTXH PTXSOC VTT tPTXH PTXDATA[7:0] X H1 H2 H3 P45 P46 P47 P48 X VTT Figure 57 - Primary UTOPIA Bus - Transmit Timing 131 MT90500 Table 93 - Primary UTOPIA Interface Parameters - Receive Characteristic PRXCLK Period PRXCLK Pulse Width (HIGH / LOW) Input Setup Time - (PRXCLAV, PRXEN, PRXSOC asserted and PRXDATA[7:0] VALID) to PRXCLK rising Input Hold Time - PRXCLK rising to (PRXDATA[7:0] INVALID and PRXSOC, PRXCLAV, and PRXEN deasserted) Sym tPRXP tPRXH/L tPRXIS 16 10 Min Typ 40 20 24 Max Units ns ns ns Test Conditions PRXCLK = 25 MHz tPRXIH 1 ns Note 1: The MT90500 operates with the UTOPIA cell-level handshake. Note 2: The relative timing of PRXCLAV, PRXEN and PRSOC must be as shown, or as given in UTOPIA Level 1 Version 2.01 Figure 6. The timing shown is also valid for applications where PRXEN is permanently asserted. tPRXP PRXCLK tPRXLtPRXH VTT tPRXIH PRXCLAV tPRXIS PRXEN tPRXIH PRXSOC tPRXIH PRXDATA[7:0] VTT VTT VTT X X H1 H2 P47 X P48 H1 VTT Figure 58 - Primary UTOPIA Bus - Receive Timing 132 MT90500 6.2.5.2 Secondary UTOPIA Interface Table 94 - Secondary UTOPIA Parameters Timing Characteristic STXCLK Period STXCLK Pulse Width (HIGH / LOW) Input Setup Time - (STXDATA[7:0] VALID; STXSOC and STXEN asserted) to STXCLK rising Input Hold Time - STXCLK rising to (STXDATA[7:0] INVALID and STXSOC and STXEN de-asserted) Output Delay - STXCLK rising to STXCLAV asserted Output Hold Time - STXCLK rising to STXCLAV de-asserted Sym tSTXP tSTXH/L tSTXIS 16 10 Min Typ 40 20 24 Max Units ns ns ns Test Conditions STXCLK = 25 MHz tSTXIH 1 ns tSTXD tSTXH 1 20 ns CL = 50 pF CL = 50 pF NOTE: The MT90500 requires at least one idle cycle between cells driven into the Secondary UTOPIA interface. tSTXP STXCLK tSTXIS STXEN tSTXIH STXSOC tSTXIH STXDATA[7:0] tSTXLtSTXH VTT tSTXIH VTT VTT X H1 H2 H3 P45 P46 P47 tSTXD P48 X H1 VTT at least 4 cycles before the next cell STXCLAV VTT NOTE: STXEN must be de-asserted for at least one cycle between cells, as shown here. Figure 59 - Secondary UTOPIA Interface 133 MT90500 6.2.6 SRTS User Interface Table 95 - SRTS Interface Parameters Characteristic SRTS ENA Delay - LOCx1 falling to CORSIGC asserted SRTS DATA Delay - LOCx1 falling to CORSIGD VALID SRTS ENA Hold Time - LOCx1 falling to CORSIGC de-asserted SRTS DATA Hold Time - LOCx1 falling to CORSIGD INVALID Sym tENAD tDD tENAH 0 Min Typ Max 20 20 Units ns ns ns Test Conditions 1) LOCx1 = 2.048 MHz (488 ns). 2) CL = 50 pF 1) LOCx1 = 2.048 MHz (488 ns). 2) CL = 50 pF CL = 50 pF Note: SRTS is assumed sampled on LOCx1 rising. CL = 50 pF Note: SRTS is assumed sampled on LOCx1 rising. to be tDH 0 ns to be LOCx1 (SRTS CLOCK) tENAD CORSIGC (SRTSENA) tDD CORSIGD (SRTSDATA) tDH SRTS Bit 1 SRTS Bit 0 VTT tENAH VTT SRTS Bit 3 SRTS Bit 2 VTT Figure 60 - SRTS User Interface Timing 6.2.7 Message Channel Interface Table 96 - Message Channel Parameters Characteristic Sym tMCCP tMCCH/L tMCCD tMCTDL tMCTDZ tMCRD 4 3 15 14 ns CL = 50 pF 237 5 4 3 Min Typ 488 244 252 22 16 13 Max Units ns ns ns ns CLKX2 period 244 ns, 122 ns or 61 ns. CL = 50 pF CL = 50 pF Test Conditions MCCLK Period MCCLK Pulse Width (HIGH / LOW) Skew - CLKx2 falling to MCCLK change Transmit Delay - MCTX to MC MCTX falling to MC falling MCTX rising to MC High-Z Receive Delay - MC to MCRX MC falling to MCRX falling MC rising to MCRX rising 134 MT90500 VTT CLKx1 (8 MHz) VTT CLKx1 (4 MHz) CLKx1 (2 MHz) VTT FSYNC (FSYNC not to scale) tMCCD tMCCD tMCCH tMCCP tMCCL VTT VTT MCCLK (2 MHz) ~ ~ tMCTDZ MCTX (Data In) ~ ~ tMCTDL VTT CLKx2 ~ ~ VTT MC (Data) tMCRD MCRX (Data Out) tMCRD VTT Figure 61 - Message Channel Timing 135 MT90500 6.2.8 Boundary-Scan Test Access Interface Table 97 - Boundary-Scan Test Access Port Timing Parameter TCK period width TCK period width LOW TCK period width HIGH TDI setup time to TCK rising TDI hold time after TCK rising TMS setup time to TCK rising TMS hold time after TCK rising TDO output delay from TCK falling TRST pulse width Symbol ttclk ttclkl ttclkh tdisu tdih tmssu tmsh tdod ttrst Min 100 40 40 10 20 10 20 0 100 30 Typ Max Units ns ns ns ns ns ns ns ns ns CL = 30 pF Test Conditions tmssu tmsh TMS tdih tdisu TDI ttclk ttclkh ttclkl TCK tdod TDO ttrst TRST 136 MT90500 7. 7.1 Applications Board Level Applications Figure 62 shows a general board level application for the MT90500. This shows a high-level view of the device connection to external memory, a CPU, an ATM Physical Layer device, an ATM AAL5 SAR device, and the TDM backplane.This is a general application diagram; the most frequent variations would be: the number and size of the SSRAM chips, the type of CPU or PHY, the mode of the TDM backplane and TDM local bus (several possibilities are listed in the figure), and the presence or absence of a secondary SAR. The size of external memory is selected to suit the application, and is tied to the number of TDM 64 kbps channels to be used, the number of VCs to be used, and the Cell Delay Variation tolerance of the receive channels. Similarly the CPU and PHY are chosen to suit the application. The TDM backplane mode (positive or negative frame-pulse; fast or slow hold time; and 2.048, 4.096, or 8.192 Mbps) is application selectable, and the local TDM bus can be enabled for applications which require it (e.g. when it is desirable to have a local HDLC, or DSP, which is not tied to the backplane). The secondary SAR may be used in applications which require ATM signalling, though it is possible to do a moderate amount of signalling using the TX and RX Data FIFOs in the MT90500, provided that the CPU can perform the rest of the SAR functions in software. Off-the-shelf ATM PHY Device Primary UTOPIA Port Local Memory External Synchronous SRAM 16-bit CPU port for internal register and external memory programming CPU MT90500 240-PQFP Secondary UTOPIA Port Off-the-shelf SAR Device (AAL5) TDM Data, Clock and Sync Lines MVIP-90 H-MVIP ST-BUS SCSA IDL Figure 62 - MT90500 Device Application Block Diagram 137 MT90500 The MT90500 will work with a variety of standard Synchronous SRAM parts. The burst feature of the Synchronous SRAM is not used by the MT90500, and since the SSRAM is not connected to a cache controller, some of the control pins of most SSRAMS are not used by the MT90500. The common control pin names for the SSRAM, and their connections when used with the MT90500, are listed in Table 98, and Table 99. Table 98 - MT90500 Connections to 18-bit Synchronous SRAM Pin Function Address Data Underrun Flag Lower Byte Write Enable Upper Byte Write Enable Memory Clock Chip Enable Output Enable Burst Address Advance Processor Address Status Controller Address Status SSRAM A0-A14 DQ[0:7, 9:16] DQ[8, 17] LW* UW* K E* G* ADV* ADSP* ADSC* MT90500 MEM_ADD[14:0] MEM_DAT[15:0], or MEM_DAT[31:16] MEM_PAR[1:0], or MEM_PAR[3:2] MEM_WR[0], or MEM_WR[2] MEM_WR[1], or MEM_WR[3] MEMCLK MEM_CS0L, or MEM_CS0H, or MEM_CS1L, or MEM_CS1H MEM_OE Never enabled - pull to VDD to disable Never enabled - pull to VDD to disable Always enabled - tie to GND to enable MEM_CS0H used for second SSRAM chip. MEM_CS1x used for second bank of SSRAM chips. MEM_DAT[31:16] used for second SSRAM chip. MEM_PAR[3:2] used for second SSRAM chip. MEM_WR[2] used for second SSRAM chip. MEM_WR[3] used for second SSRAM chip. Notes Note: The pin names in this table correspond to those for the Motorola 32K x 18-bit BurstRAM Synchronous Fast Static RAM (MCM67H518). Table 99 - MT90500 Connections to 32/36-bit Synchronous SRAM Pin Function Address Data Underrun Flag Byte Write Global Write Byte Write Enable Clock Chip Enable 1 Chip Enable 2 Chip Enable 3 Output Enable Burst Address Advance Processor Address Status Controller Address Status Sleep Burst Mode no connect MCM69F536A SA DQ DQ8[d:a] SB*[d:a] SGW* SW* K SE1* SE2 SE3* G* ADV* ADSP* ADSC* LBO* CY7C1329 A DQ[31:0] (pull-up) BW*[3:0] GW* BWE* CLK CE1* CE2 CE3* OE* ADV* ADSP* ADSC* ZZ MODE MT90500 MEM_ADD MEM_DAT[31:0] MEM_PAR[3:0] MEM_WR[3:0] MEMCLK MEM_CS0L MEM_OE MEM_CSxH Tie high (disable) Tie high (disable) Tie low (enable) Tie low Tie low or tie high MEM_CSxH not used with 32/36 bit memory Tie low (enable) Tie high (enable) MEM_CS1L used for second bank/ chip. Tie high (disable global writes) Tie low (enable byte-writes) If TDM Underrun Error indication not used, pullup MEM_PAR[3:0] to VDD3. Notes The Secondary UTOPIA bus of the MT90500, and the Transmit UTOPIA multiplexer, allow application flexibility in working with a variety of off-the-shelf data SARs. This feature also allows two MT90500s to be combined for a full 2048 full-duplex TDM channel application (allowing full connection to a 4096 channel backplane). Note that each MT90500 carries 1024 channels in each direction, not 2048 transmitted by one MT90500, and 2048 received by the other MT90500. The capabilities of the TX SAR and RX SAR internal blocks are balanced at 1024 channels. 138 MT90500 SECONDARY AAL5 SAR DEVICE STXDATA[7:0] Note: If no secondary SAR device is used, ground PRXEN and tie PRXCLK to MT90500 PTXCLK. STXDATA[7:0] PTXDATA[7:0] PTXCLK PTXCLAV PTXEN PTXSOC PTXPAR PRXDATA[7:0] PTXDATA[7:0] PRXCLAV PRXSOC PRXCLK PRXEN 155Mbps Figure 63 - UTOPIA Bus Interconnections for Two MT90500s and an AAL5 SAR Figure 63 shows in greater detail an example of the UTOPIA bus connections when two MT90500 devices and a secondary AAL5 SAR are used. Note that the receive UTOPIA bus is controlled by RXEN of the secondary AAL5 SAR. If the secondary SAR is too slow, or configured badly, it will throttle-back the cells output by the PHY device, and cause lost cells or increased CDV. (RXEN may also be tied low to allow full speed cell reception.) The MT90500 allows the primary UTOPIA port transmit clock (PTXCLK) to be one of: the transmit clock of the secondary SAR (STXCLK), the master clock (MCLK) divided by 2 or 4, or an external source. The primary UTOPIA port receive clock (PRXCLK) is driven by the secondary SAR, or it is tied to PTXCLK if a secondary SAR is not present. PRXCLK should not be too slow, or CDV may be increased. PHY DEVICE PTXCLAV PTXSOC PTXPAR PTXCLK PTXEN Round Robin Arbitration: leaves half+ bandwidth (~78 Mbps) to upstream devices (MT90500 and AAL5 SAR) PRIMARY RECEIVE MT90500 TX_SAR PRIMARY TRANSMIT M U X SECONDARY UTOPIA STXCLAV STXSOC STXCLK STXEN Priority Arbitration: leaves remaining bandwidth to upstream device (AAL5 SAR) PRIMARY RECEIVE MT90500 TX_SAR PRIMARY TRANSMIT M U X SECONDARY UTOPIA STXCLAV STXSOC STXCLK STXEN 139 MT90500 In order to support the multiple SAR configuration shown in Figure 63, while remaining UTOPIA Level 1 compatible, some UTOPIA pin functions in the MT90500 are expanded. Table 100 gives a comparison of the MT90500 to the UTOPIA Level 1 standard. Also see Table 1, "Primary UTOPIA Bus Pins," on page 19. Table 100 - MT90500 UTOPIA Signal Directions MT90500 Signal Name PTXDATA[7:0] PTXSOC PTXEN PTXCLAV PTXCLK Standard UTOPIA Signal Name TxData[7:0] TxSOC TxEnb* TxCLAV TxClk MT90500 Signal Direction O O O I I/O Standard UTOPIA Signal Direction ATM to PHY (ATM O) ATM to PHY (ATM O) ATM to PHY (ATM O) PHY to ATM (ATM I) ATM to PHY (ATM O) Exception (bidirectional pin allows for external UTOPIA clock source if desired). See Main Control Register on page 84. Notes MT90500 acts as ATM. PTXPAR PRXDATA[7:0] PRXSOC PRXEN TxPrty RxData[7:0] RxSOC RxEnb* O I I I ATM to PHY (ATM O) PHY to ATM (ATM I) PHY to ATM (ATM I) ATM to PHY (ATM O) Exception (input allows Secondary ATM device to control PHY). UTOPIA Level 1 allows RxEnb* to be permanently asserted. MT90500 acts as ATM. PRXCLAV PRXCLK STXDATA[7:0] STXSOC STXEN STXCLAV STXCLK RxCLAV RxClk TxData[7:0] TxSOC TxEnb* TxCLAV TxClk I I I I I O I PHY to ATM (ATM I) ATM to PHY (ATM O) ATM to PHY (PHY I) ATM to PHY (PHY I) ATM to PHY (PHY I) PHY to ATM (PHY O) ATM to PHY (PHY I) Exception (input allows Secondary ATM device to drive PHY and MT90500). MT90500 emulates PHY. 140 MT90500 7.2 System Level Applications Figure 64 depicts an ATM adapter card within a work-group hub, switching non-CBR data and CBR voice traffic with 2 internal switching backplanes (a TDM bus, and a packet bus). The MT90500 device interfaces to the bus transporting CBR traffic such as voice or video conferencing and the external AAL5 SAR device interfaces to either a management bus or user data bus such as PCI. Figure 65 shows a block diagram of the card. Switch ASIC Data Access Module Data Access Module Ethernet T.R., ATM Switch ASIC Analog or Digital Set Trunk Card n x 64 kbps Digital Trunk Card Ethernet T.R., ATM PSTN ATM ATM Cells MT90500 ATM PHY Transceiver Specialized Work Group AAL5 SAR ATM Switch TDM Bus Packet Bus Figure 64 - The MT90500 within a LAN Hub Figure 66 shows a networking product such as an access concentrator using the MT90500 to perform conversion from TDM links coming out of T1/E1 trunks and the user's internal ATM backplane. An external converter might be used to change the MT90500's UTOPIA interface to the user's ATM bus. Figure 67 shows an application where TDM traffic must be transported across a proprietary cell bus. The interface chips transform the standard UTOPIA format cells of the MT90500 into the proprietary cell format. Figure 68 and Figure 69 show how the MT90500 device can be used within a Computer Telephony Integration (CTI) system to transport CBR traffic from multi-stream MVIP or SCSA buses across an ATM link. 141 MT90500 MT90500 ATM Cells on Primary UTOPIA Port Off-the-shelf ATM PHY Transceiver ATM 25, 51 and 155 Mbps ATM Cells on Secondary UTOPIA Port ST-BUS Off-the-shelf AAL3/4, AAL5 SAR 16 bidirectional TDM streams + clock + 8 kHz Management or User Data Figure 65 - Using the MT90500 with External SAR and ATM Links in a LAN Mitel T1/E1 Framers TDM - ATM Conversion UTOPIA Bus ST-BUS I/F Legacy Trunks at 1.5 or 2 Mbps MT90500 Mitel T1/E1 Framers ST-BUS I/F Legacy Trunks at 1.5 or 2 Mbps UTOPIA to Proprietary Bus Conversion PCM Clocks Mitel PLL Cell Bus on the Backplane Figure 66 - Access Product using Internal High Speed Cell Bus on the Backplane 142 MT90500 Cell Bus TDM Backplane ATM Bus performing cell transport function in a shelf TDM Backplane 16 x serial TDM streams MT90500 MT90500 Bus I/F Chip C E L L B U S Bus I/F Chip MT90500 MT90500 16 x serial TDM streams Line Card Asynchronous Cell Bus with no timing transfer Line Card Figure 67 - TDM Traffic Transport Over a Cell Bus MVIP/ SCSA MITEL MT90210 Voice Compression Circuit Memory e.g. SCSI PSTN Compressed Voice Storage T1/E1 MT90500 UTOPIA ATM Bus PHY & OPTICS MT90820 Conferencing Applications DSP ATM 25 or 155 Mbps ATM LAN SCSI Processor MT90810 DSP e.g. SCSI Compressed Video Storage PBX PC CHASSIS Figure 68 - Connecting CTI Platforms to ATM LANs 143 MT90500 PC-ATM BUS ATM SWITCH FABRIC VIDEO COMPRESSION CIRCUIT ATM SWITCH FABRIC UTOPIA ATM Bus PHY & OPTICS ATM 25 or 155 Mbps ATM LAN ATM SWITCH FABRIC TELECOM I/F ATM SWITCH FABRIC PC CHASSIS MT90500 UTOPIA T1/E1 MVIP PSTN Figure 69 - The GO-MVIP, PC-ATM Bus Standard Architecture 144 MT90500 7.3 7.3.1 TDM Clock Recovery Applications General By the nature of its function - carrying isochronous traffic over Asynchronous Transfer Mode networks - the MT90500 is used in applications which require some level of synchronization of the TDM clocks at the two ends of the link. Further, these applications often require the transfer, or recovery, of the isochronous TDM timing using the ATM link. There are several approaches to TDM clock synchronization, both standardized and notstandardized. These clock synchronization methods include: * plesiochronous - where the ATM link is not required to carry timing information, as the timing at both ends is obtained from plesiochronous trunks (perhaps separate public TDM network trunks); * synchronous, or physical layer - where the timing for both ends is derived from the ATM physical link clock; * adaptive - where timing is carried end-to-end via the ATM cell stream; * SRTS - a standardized method where timing is carried via time stamps in the ATM cell stream, against the ATM physical link clock; * freerun - where no clock synchronization is used at all. The choice of clock synchronization method is dependent upon the application. Most standards documents which deal with this issue specify that the recovered clock should be synchronized to the most accurate clock available. The ITU-T Recommendation I.363.1 provides some guidance on these issues; see the "Convergence Sublayer" section, especially "Source clock frequency recovery method," and Appendix II. The reader is also directed to the Mitel Semiconductor Application Note in this topic. 7.3.2 SRTS Clock Recovery Considerations The SRTS (Synchronous Residual Time Stamp) method uses the CSI bit in the AAL1 byte to carry time stamp information over the ATM data link. Figure 70 shows a generic SRTS application. At the source end, the RTS (Residual Time Stamp) is generated by comparing a divided-down ATM network clock fnx to a TDM service clock fs. (The TDM service clock fs is generated internally to the MT90500.) The RTS is transmitted, once every 8-cell sequence, to the far end. Using the common ATM network clock (synchronous fnx) and the RTS, the far end can recover the TDM clock. Implementation details are given in Section 4.6.2, "SRTS Clock Recovery Description," on page 72. Note that in order to implement SRTS clock recovery properly, both the timing source and the far end node must share a common reference ATM network clock. If a different ATM network clock is present at either end, the recovered TDM clocks will be inaccurate in proportion to the difference in the two ATM network clocks. Where the ATM network clocks are not synchronous, or where it is not known if the ATM network clocks are synchronous, adaptive clock recovery can often be used. Since the MT90500 is a backplane device, it must work with a fixed clock rate of 2.048 MHz, 4.096 MHz or 8.192 MHz, rather than the Service Clock rate carried by the SRTS link, as given in ITU-T Recommendation I.363.1. The SRTS Transmit Divider (see Figure 33) constructs the Service Clock from the TDM bus clocks. Due to internal sampling in the MT90500, there are certain values of TDM-channels-per-VC that are not recommended for the VC carrying the SRTS information. These are listed in Table 101. If a clock slower than 60 MHz is being used for MCLK, the designer should note that FNXI must be less than one-third the rate of MCLK. Table 101 - Recommended TDM Channel Numbers for SRTS VCs Number of TDM Channels Carried by the SRTS VC Recommended Reduced Accuracy Not Recommended 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 25, 30, 32, 40, 45, 48, 50, 60, 64, 75, 80, 90, 96 7, 9, 11, 13, 14, 17, 18, 21, 23, 28, 36, 51, 85 19, 22, 26, 27, 29, 31, 33, 34, 35, 37, 38, 39, 41, 42, 43, 44, 46, 47, 49, 52, 53, 54, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 76, 77, 78, 79, 81, 82, 83, 84, 86, 87, 88, 89, 91, 92, 93, 94, 95 145 MT90500 ATM Switch Port 1 2. Network up-link carries ATM network clock in one direction, and SRTS information in the other direction. Port 2 3. The two physical ports must have synchronous physical ATM network clocks. 4. Network down-link carries ATM network clock, and SRTS information. 8 kHz TDM Reference fnx PHY MCA1 TDM Bus TDM Timing Slave PHY fnx REF8KCLK PLL 16.384 MHz UTOPIA Bus UTOPIA Bus MCA1 TDM Timing Master TDM Bus TDM Clocks SRTS Difference CPU or FPGA 5. MCA1 generates local SRTS from fnx and local TDM clocks, and calculates SRTS difference. 1. MCA1 compares fnx to TDM clocks, and generates SRTS. Clock control 6. CPU or FPGA runs clock recovery algorithm, based on SRTS difference. Figure 70 - SRTS Clocking Application Another consideration in the application of SRTS clock recovery using the MT90500 is the 5 RTS buffer in the Receive SRTS circuitry. This puts an upper limit on the CDV (Cell Delay Variation) of the receive VC carrying SRTS. Each RTS in the 5 RTS buffer is carried by one 8 cell sequence, and thus represents a fixed amount of time dependent on the number of TDM channels being carried. Table 102 summarizes the maximum CDV supported by the Receive SRTS circuitry at various numbers of TDM channels. Table 102 - Limits on CDV on Receive SRTS VC Channels per VC carrying SRTS 1 2 16 24 32 64 96 N (General) Time represented by 5 RTS (msec) 234 117 14.7 9.87 7.32 3.66 2.44 125 sec X 375 / N X 5 = (234 / N) msec Maximum CDV (msec) 117 58.6 7.32 4.84 3.66 1.83 1.22 125 sec X 375 / N X 5 / 2 = (117 / N) msec 7.3.3 Free-running Clocks It is usually possible to provide intelligible voice connections using a free-running clock, provided that the crystal accuracy is constrained to a few parts per million. Free-running clocks are not recommended however, as relatively frequent frame slips (and accompanying data errors) are inevitable, and this is generally not acceptable for TDM data going to the public network. 146 MT90500 7.4 7.4.1 External Memory Space and Bandwidth Calculations External Memory Space Requirements This section provides a list of the control and data structures used by the MT90500 which are located in external memory. An estimation of the structure size is provided, assuming various scenarios: 256, 512, and 1024 TDM channels in both directions and from 16 to 1024 VCs. (In line with accepted usage for memory, here 1 Kbyte = 1024 bytes.) Transmit Memory Requirements Refer to Figure 19, "Overview of CBR Data Transmission Process," on page 54. A. TX Circular Buffer Control Structure Two bytes of RAM are required for every TDM channel transmitted. * 256 TDM channels * 512 TDM channels * 1024 TDM channels B. Transmit Circular Buffers 0.5 Kbyte 1 Kbyte 2 Kbytes 64 bytes of RAM are required for every TDM channel transmitted. * 256 TDM channels * 512 TDM channels * 1024 TDM channels C. Transmit Event Scheduler 16 Kbytes 32 Kbytes 64 Kbytes Assume either 1 scheduler, or all 3 schedulers in service. Assume the schedulers are composed of 47 frames (AAL1-SDT) and each frame contains 16 two-byte VC Pointer entries. * 1 scheduler * 3 schedulers D. Transmit Control Structure ~ 1.5 Kbytes ~ 4.4 Kbytes Each control structure begins with 12 bytes of control data, followed by 2 bytes of information for each TDM channel. All transmit control structures occupy an integer number of 16-byte blocks. * 16 VCs (16 TDM channels per VC) * 128 VCs (4 TDM channels per VC) * 1024 VCs (1 TDM channel per VC) * 64 data cell structures at 64 bytes each 0.75 Kbyte (16 * ROUNDUP(12 + 16 * 2) = 768 bytes) 4 Kbytes (128 * ROUNDUP(12 + 4 * 2) = 4096 bytes) 16 Kbytes (1024 * ROUNDUP(12 + 1 * 2) = 16384 bytes) E. Transmit Data Cell FIFO holding 64 cells (Refer to Section 4.3.3.) 4 Kbytes Sub-total external memory space requirements to support the TDM to ATM transmit process: Minimum requirements (256 channels, 1 scheduler): Maximum requirements (1024 channels, 3 schedulers): 22.7 Kbytes 90.4 Kbytes Receive Memory Requirements See Figure 30, "Overview of CBR Data Reception Process," on page 69. A. VC Look-up Table Note: These numbers assume one-to-one mapping of look-up table entries to VCs. Larger "sparse" tables may be used in some applications, up to 128 Kbytes. 147 MT90500 * 16 possible VCs * 128 possible VCs * 1024 possible VCs B. RX_SAR Control Structures Each control structure begins with 12 bytes of control data, and is then followed by 2 bytes of information for each TDM channel. For the purposes of these calculations, all RX_SAR control structures are designed to occupy an integer number of 16-byte blocks. 0.0625 Kbyte 0.5 Kbytes 4 Kbytes * 16 VCs (16 TDM channels per VC) * 128 VCs (4 TDM channels per VC) * 1024 VCs (1 TDM channel per VC) C. Receive Circular Buffers 0.75 Kbyte (16 * ROUNDUP(12 + 16 * 2) = 768 bytes) 4 Kbytes (128 * ROUNDUP(12 + 4 * 2) = 4096 bytes) 16 Kbytes (1024 * ROUNDUP(12 + 1 * 2) = 16384 bytes) A 64-byte buffer provides 8 ms of buffering capability (1 byte = 125 s) while a 1024-byte buffer provides up to 128 ms of buffering. In this example, we give sizes for a 64-byte and a 1024-byte (64 / 1024) buffer for each channel. * 256 TDM channels * 512 TDM channels * 1024 TDM channels 16 / 256 Kbytes 32 / 512 Kbytes 64 / 1024 Kbytes D. External Memory to Internal TDM Memory Structure Four bytes of RAM are required for every TDM channel transmitted. * 256 TDM channels * 512 TDM channels * 1024 TDM channels * 64 at 64 bytes each 1 Kbyte 2 Kbytes 4 Kbytes E. Receive Data Cell FIFO holding 64 cells (Refer to Section 4.5.4.) 4 Kbytes Sub-total external memory space requirements to support the ATM to TDM receive process: Minimum requirements (256 channels, 64-byte buffers): Maximum requirements (1024 channels, 1024-byte buffers): ~22 Kbytes 1052 Kbytes Total Memory Requirements Total external memory size requirements to support both the TDM to ATM transmit process and the ATM to TDM receive process: Minimum requirements: Maximum requirements: 44.7 Kbytes (256 X 64 kbps bidirectional channels with 16 VCs) 1142.4 Kbytes (1024 X 64 kbps bidirectional channels with 1024 VCs) Where the memory requirements are close to the physical size of the provisioned memory, the designer should pay special attention to what memory address boundaries some structures may not cross. (See Section 7.4.2.) 148 MT90500 7.4.2 Memory Structure Summary Table 103 - Summary of External Memory Structures External Memory Structure TX Circular Buffer Control Structure SIze (in bytes) Min: 256 Max: 4096 Start on Boundary Control structure must start on 512-byte boundary: x0 0000 0000 Register 6040h: TXCBCSBASE = bits<20:9> of TX Circular Buffer Control Structure Base Address. Do not cross boundary Control structures cannot cross an 8192-byte (8K) boundary x0 0000 0000 0000 Therefore, to ensure that structure never crosses this boundary, start structure on a boundary equal to the structure size. Notes Structure size = # of entries * 2 bytes/entry. TX Circular Buffers 64 (per TDM channel transmitted) First buffer must start on a 512-byte boundary: x0 0000 0000 Register 6044h: TXCBBASE = bits<20:9> of TX Circular Buffer Base Address. Each subsequent buffer automatically starts on next 64-byte boundary. Transmit Control Structures Min: 14 Max: 256 (per VC) Each control structure must start on a 16-byte boundary: x 0000 Register 2040h: TXBASE = bits<20:16> of Transmit Control Structure Base Address. The address in the scheduler provides bits<15:4> of address. Control structures cannot cross a 256-byte boundary x 0000 0000 Transmit Event Schedulers Min: 16 Max: 16K (per scheduler - up to 3 can be configured) Each scheduler must start on a 512-byte boundary: x0 0000 0000 Register 2010h/2020h/ 2030h: SBASE = bits<20:9> of Scheduler Base Address. The look-up table must start on a boundary equal to the table size = 2^(M+N+2) = #-of-entries * 4 bytes Register 401Eh: LUTBASE = bits<20:5> of pointer to start of look-up table. Register 4010h: M and N = number of LSBs from VPI and VCI, respectively, to be used in address. Min. Size = 1 frame * 8 entries/frame * 2 bytes/ entry. Typ. Size = 47 frames * 16 entries/frame * 2 bytes/entry. Max. Size = 256 frames * 32 entries/frame * 2 bytes/entry. Min. Size = 2^(8 + 2) = 1024. Max. Size = 2^(15 + 2) = 131072 = 128K. Requires external memory allocation of 2^(M + N + 2) bytes. Look-UpTable Min: 1024 Max: 128K 149 MT90500 Table 103 - Summary of External Memory Structures External Memory Structure External Memory to Internal Memory Control Structure SIze (in bytes) Min: 512 Max: 8192 Start on Boundary Control structure must start on 512-byte boundary: x0 0000 0000 Register 6042h: EIMCSBASE = bits<20:9> of External to Internal Memory Control Structure Base Address. Do not cross boundary Control structures cannot cross an 8192-byte (8K) boundary x0 0000 0000 0000 Therefore, to ensure that structure never crosses this boundary, start structure on a boundary equal to the structure size. Notes Structure size = # of entries * 4 bytes/entry. RX Circular Buffers Min: 64 Max: 1024 (one buffer per received TDM channel) Buffers must start on boundary equal to buffer size: 64 - x00 0000 128 - x000 0000 256 - x 0000 0000 512- x0 0000 0000 1024 - x00 0000 0000 Number of unique bits provided differs in External to Internal Memory Control Structure: 64 bytes - bits<20:6> 128 bytes - bits<20:7> 256 bytes - bits<20:8> 512 bytes - bits<20:9> 1024 bytes - bits<20:10> Buffer size is controlled by the External to Internal Memory Control Structure and the RX_SAR Control Structure. RX_SAR Control Structures Min: 14 Max: 256 (per VC) Each control structure must start on a 16-byte boundary: x 0000 Register 4000h: RXBASE = bits<20:18> of RX_SAR Control Structure Base Addresses. Look-up Table entry provides bits<17:4> of address. Control structures cannot cross a 256-byte boundary x 0000 0000 Transmit Data Cell FIFO Min: 1024 Max: 8192 FIFO must start on a 512byte boundary: x0 0000 0000 Register 2050h: TXFFBASE = bits<20:9> of Transmit Data Cell FIFO Base Address. FIFOs cannot cross an 8192-byte (8K) boundary x0 0000 0000 0000 Therefore, to ensure that FIFO never crosses this boundary, start FIFO on a boundary equal to the FIFO's size. FIFOs cannot cross an 8192-byte (8K) boundary x0 0000 0000 0000 Therefore, to ensure that FIFO never crosses this boundary, start FIFO on a boundary equal to the FIFO's size. Each non-CBR cell occupies a 64-byte buffer within the FIFO. Min. Size = 16 cells * 64 bytes/cell. Max. Size = 128 cells * 64 bytes/cell. May be omitted. Each non-CBR cell occupies a 64-byte buffer within the FIFO. Min. Size = 16 cells * 64 bytes/cell. Max. Size = 128 cells * 64 bytes/cell. May be omitted. Receive Data Cell FIFO Min: 1024 Max: 8192 FIFO must start on a 512byte boundary: x0 0000 0000 Register 4020h: RXFFBASE = bits<20:9> of Receive Data Cell FIFO Base Address. 150 MT90500 7.4.3 External Memory Bandwidth Requirements The following section provides estimated external memory bandwidth requirements to support the functionality of the MT90500, excluding negligible non-CBR traffic (i.e. data cells or OAM cells). The following scenarios are examined: 256, 512, and 1024 bidirectional TDM channels. The memory clock MEMCLK is tied to the input MCLK, which also clocks all internal processes, and also controls CPU access speed. ATM Transmit Process Bandwidth A. Access to TX Circular Buffer Control Structure. One word read access is required per TDM channel every 4 frames. Thus, one double-word access can retrieve 2 TDM channels every 4 frames (500 s): (1 double-word read access / (2 channels * 500 s)) * `N' TDM channels = 1000 * `N' accesses/s. * 256 TDM channels * 512 TDM channels * 1024 TDM channels B. Access to the Transmit Circular Buffers. 0.256 M accesses / s 0.512 M accesses / s 1.024 M accesses / s One double word (32-bit) write access is required to transfer a TDM channel into a circular buffer every four frames (500 s). As well, four additional read accesses are required to retrieve the data byte by byte: ((1 double-word write access + 4 half-word read accesses) / 500 s) * `N' TDM channels = 10000 * `N' accesses/s. * 256 TDM channels * 512 TDM channels * 1024 TDM channels C. Access to Transmit Event Schedulers. 2.56 M accesses / s 5.12 M accesses / s 10.24 M accesses / s Assuming that we have selected 16 VC Pointers (one word each) per frame, we require eight double-word read accesses per scheduler per frame (125 s): (8 double-word read accesses / 125 s) * `N' event schedulers = 64000 * `N' accesses/s. * 1 scheduler * 3 schedulers D. Transmit Control Structure Accesses. 0.064 M accesses / s 0.192 M accesses / s Each cell transmitted requires three control double-word read accesses (for the twelve bytes of control data at the start of each Transmit Control Structure), one control double-word write access (to update the Current Entry, Sequence Number, and Circular Buffer Pointer fields of the Transmit Control Structure), as well as up to 24 double-word read accesses (to select up to 48 TDM Circular Buffer addresses per cell) to know which data to transfer, for a total of up to 28 memory accesses per cell transmitted. 256 TDM channels represent a rate of ~ 5.5 cells / 125 s; 512 TDM channels represent a rate of ~11 cells / 125 s; etc. (28 double-word memory accesses * estimated cell arrival rate (per 125 s) = 224000 * cell arrival rate. * The case of one TDM channel per cell has been optimized to outperform the standards stated herein. The case of VCs having odd numbers of TDM channels is slightly worse than the number given. * 256 TDM channels * 512 TDM channels * 1024 TDM channels 1.232 M accesses / s 2.464 M accesses / s 4.928 M accesses / s Sub-total external memory access bandwidth requirements to support the TDM to ATM transmit process: Minimum requirements: Maximum requirements: ~ 4.11 M accesses / sec ~ 16.4 M accesses / sec 151 MT90500 ATM Receive Process Bandwidth A. Access to VC Look-up Table. Assuming an overall inbound traffic rate of 25.6 Mbps, the External Memory to Internal TDM Memory Structure encounters a maximum of ~60,000 cells per second (i.e. (3.2 Mbytes/s) / (53 bytes/cell) = 60377.36 cells / s). Assuming an overall inbound traffic of 155.52 Mbps (again, 1M = 1 000 000), the External Memory to Internal TDM Memory Structure encounters ~400,000 cells per second (i.e. (19.44 Mbytes/s) / (53 bytes/cell) = 366792.45 cells / s). There is one double-word read access per cell. * 25.6 Mbps * 155.52 Mbps B. RX_SAR Control Structure Accesses. ~ 0.06 M accesses / s ~ 0.4 M accesses / s Each received cell requires three control double-word read accesses (for the twelve bytes of control data at the start of each RX_SAR Control Structure), one control double-word write access (to update the Current Entry and TDM Write Pointer fields of the RX_SAR Control Structure), as well as up to 24 double-word read accesses (to select up to 48 RX Circular Buffer Base Addresses per cell) to know which data to transfer, for a total of up to 28 memory accesses per cell transmitted. 256 TDM channels represent a rate of ~ 5.5 cells / 125 s; 512 TDM channels represent a rate of ~11 cells / 125 s; etc. 28 double-word read accesses * estimated cell arrival rate (per 125 s) = 224000 * cell arrival rate. * 256 TDM channels * 512 TDM channels * 1024 TDM channels C. Access to the Receive Circular Buffers. 1.232 M accesses / s 2.464 M accesses / s 4.928 M accesses / s One double-word (32-bit) read access followed by a double-word write access (to clear the underrun bit after the byte has been read) per TDM channel every four frames (500 s). Four times as many accesses are required to transfer the data from the received cell to the circular buffer, byte per byte. ((1 double-word read access + 1 double-word write access + 4 half-word write accesses) / 500 s * `N' TDM channels = 12000 * `N' accesses/s. * 256 TDM channels * 512 TDM channels * 1024 TDM channels 3.07 M accesses / s (5.63 M accesses / s) 6.14 M accesses / s (11.3 M accesses / s) 12. 3 M accesses / s (22.5 M accesses / s) D. Access to the External Memory to Internal TDM Memory Structure. One double-word read access is required per TDM channel every 4 frames (500 s): (1 double-word read access / 500 s) * `N' TDM channels = 2000 * `N' accesses/s. * 256 TDM channels * 512 TDM channels * 1024 TDM channels 0.512 M accesses / s 1.024 M accesses / s 2.048 M accesses / s Sub-total of external memory access bandwidth requirements to support the ATM to TDM receive process: Minimum requirements: Maximum requirements: ~ 7.76 M accesses / s ~ 29.9 M accesses /s Total Bandwidth Requirements Total of external memory access bandwidth requirements to support both the TDM to ATM transmit and the ATM to TDM receive process: Minimum requirements: Maximum requirements: 152 ~ 11.9 M accesses / s ~ 46.3 M accesses /s MT90500 The above maximum requirement defines the theoretical minimum clock frequency the design must achieve to support 1024 X 64 kbps bidirectional channels with 1024 VCs. Assuming a 29% margin for CPU accesses, AAL0 cell processing, and random lost memory access efficiency, the MT90500 should be supplied with a master clock (MCLK) of 60 MHz to support 1024 X 64 kbps bidirectional channels with 1024 VCs. It is also recommended to select SSRAM to minimize turnaround cycles, for the greatest memory efficiency. 7.5 CBR Throughput Delay Delay through the MT90500, from TDM bus to TDM bus, depends on a number of variables, not all of which are under the control of the designer. The following discussion omits ATM network delay (transmission delay), TDM switching delay (caused by moving a TDM channel from time slot 0 to time slot 32, for instance) and CDV buffer delay (Avg. Lead of the RX Circular Buffer). An example of large delay would use AAL1, N=1, fully-filled cells, the delay for which can be typically 66 frames (8.25 msec). This is due to the following factors: 4 3 47 8 4 ---66 frames frames frames frames frames frames TX TDM Input Frame Buffer average TX offset (TDM Write Pointer to TX_SAR Read Pointer) cell assembly (47 byte payload) RX Circular Buffer delay (Avg. Lead = 02h, = 8 frames) RX TDM Output Frame Buffer. Minimum delay is achieved using larger trunking numbers (N > 47) or using partially filled cells with N = partialfill- level. Delay in this case will be 3 msec to 5 msec, with CDV buffers set to the minimum. To these numbers, the designer may wish to add the application-specific delays: ATM network transmission delay, ATM switching delay, CDV buffer delay, and TDM switching delay. 153 MT90500 7.6 7.6.1 Other Applications Payload Switching Figure 71 indicates how the MT90500 can be used as a payload switch. In such an application, TDM data received in the cell payload of one ATM VC can be transmitted from the MT90500 as the cell payload of a different ATM VC. Note that this constrains the Receive Circular Buffers to 64 bytes (the same size as the Transmit Circular Buffer), which limits the CDV tolerance. A major consideration in this application is delay tolerance of the transported channels, as the reassembly delay and segmentation delay of this payload switch are added to the end points/ reassembly delay and segmentation delay. k Circular Buffers (Serve as Receive AND Transmit) Circular Buffer (64 bytes) RX SAR Arriving ATM Cells N Arriving VCs, k TDM Channels Circular Buffer (64 bytes) TX SAR Transmitted ATM Cells M Transmitted VCs, k TDM Channels Circular Buffer (64 bytes) Figure 71 - TDM Payload Switching 7.6.2 TDM Switching and Loopback Figure 72 indicates how the MT90500 can be used to switch one or more TDM channels. In such an application, TDM data input on a specific time slot and stream can be output from the MT90500 on a different TDM time slot and stream. (When an input TDM channel from a specific trunk is output back to that trunk, this switching can be termed a "loopback".) Note that for this application the Receive Circular Buffers for the TDM channels involved must be 64 bytes (the same size as the Transmit Circular Buffer). To perform loopback or switching of a specific TDM input channel to a specific TDM output channel, the Transmit Circular Buffer Control Structure is first programmed to have the desired input TDM channel written to a particular TX Circular Buffer. The External Memory to Internal Memory Control Structure is then programmed to set up an RX Circular Buffer 64 bytes long, at the same address as the TX Circular Buffer just enabled. At the same time, the desired output TDM channel is set up to read from this RX Circular Buffer (shared buffer). No further CPU involvement is required. 154 MT90500 The input channel is now automatically written to the shared buffer, and the output channel is automatically read from the shared buffer, resulting in the input channel being written to the output channel. The throughput delay in this setup is 1 msec. This is due to the 4-frame TDM Input Frame Buffer followed by the 4-frame TDM Output Frame Buffer. Circular Buffers (Receive AND Transmit programmed into same addresses) Circular Buffer (64 bytes) TDM Input Frame Buffer Input TDM Channels Circular Buffer (64 bytes) TDM Output Frame Buffer Output TDM Channels Circular Buffer (64 bytes) Figure 72 - TDM-to-TDM Loopback/Switching 7.6.3 DS0 Trunking, or Dynamic TDM channel re-mapping The MT90500 can be used in trunking applications. In trunking applications it is often desirable to maintain an ATM VC of constant bandwidth (constant Nx64) but to re-map the TDM channels within the ATM VC to different TDM channels on the backplane or TDM trunks. Given an established VC, and the need to shut down a TDM channel and re-use the bandwidth within the VC, re-mapping a TDM channel can be done on the MT90500 as follows: 1) Tristate the output TDM channel at the reassembly device (receive TDM end), using the OE Registers, to end the old TDM channel connection. 2) Re-write the TDM-channel-to-TX-Circular-Buffer mapping in the Transmit Circular Buffer Control Structure at the segmentation device (transmit end). This is done by writing a new time slot and/or stream into the word-entry associated with the particular TX circular buffer. 3) Re-write the RX-Circular-Buffer-to-TDM-channel mapping in the External Memory to Internal Memory Control Structure at the reassembly device (receive TDM end). This is done by writing a new TDM Channel # into the first word of the two-word-entry associated with the particular RX circular buffer. 4) Turn on the output TDM channel at the reassembly device (receive TDM end), using the OE Registers, to start the new connection. 155 MT90500 7.6.4 SCSA Message Channel Figure 73 shows how the CORSIG/MC pins are used in an SCSA Message Channel application. +5V Typical Message Bus Controller MCTX MC MCRX MC CT Bus or SCbus TXDA RXDA CXDA DCLK MCCLK MT90500 CLKx2 Figure 73 - SCSA Message Bus Application 156 Package Outlines L1 A A2 L b A1 e D D1 E1 Index E Notes: 1) Not to scale 2) Top dimensions in inches 3) The governing controlling dimensions are in millimeters for design purposes ( ) WARNING: This package diagram does not apply to the MT90810AK 100 Pin Package. Please refer to the data sheet for exact dimensions. Pin 1 Metric Quad Flat Pack - L Suffix 44-Pin Dim 64-Pin Max 0.096 (2.45) 0.083 (2.10) 0.018 (0.45) 100-Pin Max 0.134 (3.40) 0.12 (3.05) 0.02 (0.50) 128-Pin Max 0.134 (3.40) 0.12 (3.05) 0.015 (0.38) Min A A1 A2 b D D1 E E1 e L L1 0.01 (0.25) 0.077 (1.95) 0.01 (0.30) Min 0.01 (0.25) 0.1 (2.55) 0.013 (0.35) Min 0.01 (0.25) 0.1 (2.55) 0.009 (0.22) Min 0.00 0.125 (3.17) 0.019 (0.30) Max 0.154 (3.85) 0.01 (0.25) 0.144 (3.60) 0.018 (0.45) 0.547 BSC (13.90 BSC) 0.394 BSC (10.00 BSC) 0.547 BSC (13.90 BSC) 0.394 BSC (10.00 BSC) 0.031 BSC (0.80 BSC) 0.029 (0.73) 0.04 (1.03) 0.941 BSC (23.90 BSC) 0.787 BSC (20.00 BSC) 0.705 BSC (17.90 BSC) 0.551 BSC (14.00 BSC) 0.039 BSC (1.0 BSC) 0.029 (0.73) 0.04 (1.03) 0.941 BSC (23.90 BSC) 0.787 BSC (20.00 BSC) 0.705 BSC (17.90 BSC) 0.551 BSC (14.00 BSC) 0.256 BSC (0.65 BSC) 0.029 (0.73) 0.04 (1.03) 1.23 BSC (31.2 BSC) 1.102 BSC (28.00 BSC) 1.23 BSC (31.2 BSC) 1.102 BSC (28.00 BSC) 0.031 BSC (0.80 BSC) 0.029 (0.73) 0.04 (1.03) 0.077 REF (1.95 REF) 0.077 REF (1.95 REF) 0.077 REF (1.95 REF) 0.063 REF (1.60 REF) NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters. Package Outlines 160-Pin Dim 208-Pin Max 0.154 (3.92) 0.01 (0.25) 0.01 (0.25) .126 (3.20) .007 (0.17) 1.204 (30.6) 1.102 (28.00) 1.204 BSC (30.6 BSC) 1.102 BSC (28.00 BSC) 0.020 BSC (0.50 BSC) 0.04 (1.03) 0.018 (0.45) 0.051 REF (1.30 REF) 0.029 (0.75) 0.018 (0.45) 240-Pin Max .161 (4.10) 0.02 (0.50) .142 (3.60) .011 (0.27) Min A A1 A2 b D D1 E E1 e L L1 0.029 (0.73) 0.063 REF (1.60 REF) 0.125 (3.17) 0.009 (0.22) 1.23 BSC (31.2 BSC) 1.102 BSC (28.00 BSC) 1.23 BSC (31.2 BSC) 1.102 BSC (28.00 BSC) 0.025 BSC (0.65 BSC) - Min Min 0.01 (0.25) 0.126 (3.2) 0.007 (0.17) 1.360 BSC (34.6 BSC) 1.26 BSC (32.00 BSC) 1.360 BSC (34.6 BSC) 1.26 BSC (32.00 BSC) 0.0197 BSC (0.50 BSC) Max 0.161 (4.10) 0.02 (0.50) 0.142 (3.60) 0.010 (0.27) 0.144 (3.67) 0.015 (0.38) 0.029 (0.75) 0.051 REF (1.30 REF) NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters. http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively "Mitel") is believed to be reliable. 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This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel's conditions of sale which are available on request. M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation Mitel Semiconductor is an ISO 9001 Registered Company Copyright 1999 MITEL Corporation All Rights Reserved Printed in CANADA TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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