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Z86C95 DSP CPS DC-4067-13
CUSTOMER PROCUREMENT SPECIFICATION
Z86C95
CMOS Z8(R) DIGITAL SIGNAL PROCESSOR (DSP)
GENERAL DESCRIPTION
The Z86C95 MCU (Microcontroller Unit ) introduces a new level of sophistication to SuperintegrationTM ICs. The Z86C95 is a member of the Z8(R) single-chip microcontroller family incorporating a CMOS ROMless Z8 microcontroller with an embedded DSP processor for digital servo control. The DSP slave processor can perform 16-bit x 16-bit multiplicates and accumulates in one clock cycle. Additionally, the Z86C95 is further enhanced with a hardwired 16-bitx16-bit multiplier and a 32-bit/16-bit divider, three 16-bit counter timers with capture and compare registers, a half flash 8-channel 8-bit A/D converter with a 2 sec conversion time, an 8-bit DAC with 1/4 programmable gain stage, UART, serial peripheral interface, and a PWM output channel (Functional Block Diagram). It is fabricated using CMOS technology and offered in an 80-pin QFP, 84pin PLCC, or 100-pin VQFP package. The Z86C95 provides up to 16 output address lines thus permitting an address space of up to 64 Kbytes of data and program memory each. Eight address outputs (AD7-AD0) are provided by a multiplexed, 8-bit, Address/Data bus. The remaining 8 bits are provided via output address bits A15-A8. There are 256 registers located on chip and organized as 236 general-purpose registers, 16 control and status registers, and four I/O port registers. The register file can be divided into sixteen groups of 16 working registers each. Configuration of the registers in this manner allows the use of short format instructions; in addition, any of the individual registers can be accessed directly. Also, the Z86C95 contains 512 bytes of DSP Program RAM and 128 words of DSP data RAM.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
OPERATING ERRATA
This notice only applies to devices top marked "Z86C9524 ASC/FSC/VSC" with a date code of 9237 or later. 1. A DSP load to the DAC Register fails below approximately VCC = 4.7V. 2. Clipping occurs in the linearity of the DAC with a 100K load at about 3.3V output (VDHI = 3.5V). 3. ICC1 at HALT Mode will show a current of 17-18 mA, then will jump to 40-70 mA, and will settle between 1724 mA. Settling time is about 10-15 seconds. 4. ICC2 at STOP Mode and DSP Pause will show a current of 1-2 mA, then will jump to 5-7 mA, and will settle at 34 mA. Settling time is about 10-15 seconds. The following operating errata only applies to devices topmarked with "Z86C95 ASC/FSC/VSC." 1. ICC1 at HALT Mode will show a current of 17-18 mA, then will jump to 40-70 mA, and will settle between 1724 mA. Settling time is about 10-15 seconds. 2. ICC2 at STOP Mode and DSP Pause will show a current of 1-2 mA, then will jump to 5-7 mA, and will settle at 3-4 mA. Settling time is about 10-15 seconds. The following operating errata only applies to devices topmarked with "Z86C9540 ASC/FSC/VSC or SL 1636." 1. ICC1 at HALT Mode will show a current of 17-18 mA, then will jump to 40-70 mA, and will settle between 1724 mA. Settling time is about 10-15 seconds.
DC-4067-13
(5-17-94)
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Z86C95 DSP CPS DC-4067-13
GENERAL DESCRIPTION (Continued)
2. ICC2 at STOP Mode and DSP Pause will show a current of 1-2 mA, then will jump to 5-7 mA, and will settle at 3-4 mA. Settling time is about 10-15 seconds. 3. The zero error for the ADC at 25C is about 180 mV.
Output Input
Vcc
GND
XTAL /AS /DS R//W /RESET /WAIT
Port 3
Machine Timing and Instruction Control
SPI UART Three 16-Bit Counter/ Timers 32 / 16 Divider 16 x 16 Multiplier Interrupt Control
ALU
Flags
Register Pointer Register File 256 x 8-Bit
Program Counter
Digital Signal Processor
DSP RAM Bank 1
DSP RAM Bank 2
Program RAM
Port 2
Address A15-A0*
* In multiplexed mode, A7-A0 reflects the DSP address bus for emulation.
AD7-AD0 8 Address/Data
ADC
DAC
PWM
I/O (Bit Programmable)
8 Channel Analog In
Analog Out
PWM
Functional Block Diagram
2
Z86C95 DSP CPS DC-4067-13
PIN DESCRIPTION
DSP_SYNC DSP_SSN SLAVESEL DSP_RW
/WAIT
VDD
C01
C02
VSS
A15
A14
A13
A12
A11
A10
DO
A9
A8
A7
A6
A5
P2(0) P2(1) P2(2) P2(3) P2(4) P2(5) P2(6) P2(7) VSS ANGND AVCC VAHI VALO ANA(0) ANA(1) ANA(2)
64 65
A4
41 40
SK
DI
A3 A2 A1 A0 AD0 VSS AD1
Z86C95 80-Lead QFP
AD2 AD3 AD4 AD5 AD6 AD7 R/W /DS
80 1
25 24
/AS
XTAL2
VDLO
ANA(3)
ANA(4)
ANA(5)
ANA(6)
ANA(7)
SYNC
P3(7)
P3(6)
P3(5)
P3(3)
P3(2)
P3(1)
P3(0)
PWM
IACK
DAC
VDD
80-Lead QFP Pin Assignments
/RESET
XTAL1
SCLK
P3(4)
VDHI
3
Z86C95 DSP CPS DC-4067-13
PIN DESCRIPTION (Continued)
DSP_SSN
75 74
ANGND
/WAIT
VALO
AVCC
ANA3
ANA2
ANA1
ANA0
VAHI
VSS
P27
P26
P25
P24
P23
P22
P21
P20
N/C
11 ANA4 ANA5 ANA6 ANA7 VDLO DAC VDHI VDD P37 P36 P35 P33 P32 P31 P30 XTAL1 XTAL2 PWM /RESET SCLK SYNC 32 33 12
1
84
N/C
C01 C02 DSP_SYNC DSP_RW SLAVESEL SK D1 D0 VDD VSS
Z86C95 84-Lead PLCC
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6
42 43
54 53
A5
IACK
R//W
AD7
AD6
AD5
AD4
AD3
AD2
AD1
VSS
N/C
/AS
/DS
AD0
A0
A1
A2
A3
P34
84-Lead PLCC Pin Assignments
4
DSP-A8
A4
Z86C95 DSP CPS DC-4067-13
PIN DESCRIPTION (Continued)
NC NC NC DSP_A8 A3 A2 A1 A0 AD0 VSS AD1 AD2 AD3 AD4 AD5 AD6 AD7 R//W /DS /AS P34 IACK NC NC NC
45 40 35 30 25
A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS VDD NC D0 D1 SK SLAVESEL DSP_RW DSP_SYNC C02 C01 DSP_SSN /WAIT
50
55
20
60
15
Z86C95 100-Lead VQFP 65 10
70
5
75
80
85
90
95
1
NC SYNC SCLK NC RESET PWM XTAL2 XTAL1 P30 P31 P32 P33 P35 P36 P37 VDD VDHI DAC VDLO ANA7 ANA6 ANA5 ANA4 NC NC
NC NC P20 P21 P22 P23 P24 P25 P26 P27 VSS NC NC NC ANGND
100-Pin VQFP Pin Assignments
AVCC AVHI AVLO ANA0 ANA1 ANA2 ANA3 NC NC NC
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Z86C95 DSP CPS DC-4067-13
PIN FUNCTIONS
DSP Single Step DSP Read Write DSP Sync
Clock
Emulation Pins
Timing and Control
Analog Power
+5V GND
DSP_SSN
DSP_SYNC
XTAL1
SCLK IACK
/SYNC DSP-A8
XTAL2
DSP_RW
/RESET
R//W
/DS
/AS
Address A15-A0
A7-A0 (DSP Emulator Support)
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
ANGND
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VDLO VDHI
ANVCC
Analog Inputs To A/D
D/A Ref Voltage DAC Output PWM Output Compare Outputs SPI Slave Select SPI Clock SPI Data Asynchronous WAIT States
Z86C95
DAC PWM C01 C02 SLAVESEL SK DI DO /WAIT
Port 2 (Bit Programmable I/O)
Port 3
A/D Ref Voltage
6
VALO
VAHI
P22
P23 P24
P26
P21
P27
P31
P32
P33
P34
P35
P36
P20
P25
P30
P37
Z86C95 DSP CPS DC-4067-13
ABSOLUTE MAXIMUM RATINGS
Symbol VDD TSTG TA Description Supply Voltage* Storage Temp Oper Ambient Temp Min -0.3 -65 Max +7.0 +150 Unit V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Notes: * Voltages on all pins with respect to GND. See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted (Test Load Diagram).
DUT Device Under T est V Commutation I OL
50 pf
I OH
Test Load Diagram
7
Z86C95 DSP CPS DC-4067-13
DC ELECTRICAL CHARACTERISTICS VCC = 3.3V 10%
Sym Parameter VCH VCL VIH VIL VOH VOH VOL VRH VRl IIL IOL IIR ICC ICC1 ICC2 IALL Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltge Output High Voltge Output Low Voltage Reset Input High Voltage Reset Input Low Voltage Input Leakage Output Leakage Reset Input Current Supply Current HALT STOP and Pause Mode Auto Latch Low Current TA = 0C to +70C Min Max 0.8 VCC -0.03 0.6xVCC -0.3 2.0 VCC - 100 mV 0.8xVCC -0.03 -2 -2 0.4 VCC 0.2xVCC 2 2 -180 50 15 20 10 7 VCC 0.1xVCC VCC 0.2xVCC Typical at 25C Units V V V V V V V V V V A A A mA mA A A Conditions IIN 250 A Driven by External Clock Generator Driven by External Clock Generator
IOH = -1.0 mA IOH = -100 A IOL = +1.0 mA
40 10 6 5
Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 24 MHz [1] HALT Mode VIN=OV, VCC @ 24 MHz [1] STOP Mode VIN=OV, VCC [1]
-10
Note: [1] All inputs driven to 0V, VCC and outputs floating.
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Z86C95 DSP CPS DC-4067-13
DC ELECTRICAL CHARACTERISTICS VCC = 5.0V 10%
Sym Parameter VCH VCL VIH VIL VOH VOH VOL VRH VRl IIL IOL IIR ICC Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltge Output High Voltge Output Low Voltage Reset Input High Voltage Reset Input Low Voltage Input Leakage Output Leakage Reset Input Current Supply Current TA = 0C to +70C Min Max 3.8 -0.03 2.0 -0.3 2.4 VCC - 100mV 3.8 -0.03 -2 -2 0.4 VCC 0.8 2 2 -180 82 120 150 20 30 45 -20 20 20 7 VCC 0.8 VCC 0.8 Typical at 25C Units V V V V V V V V V V A A A mA mA mA mA mA mA A A Conditions IIN 250 A Driven by External Clock Generator Driven by External Clock Generator
IOH = -2.0 mA IOH = -100 A IOH = +2.0 mA
50 70 85 13 20 30 6 5
Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 24 MHz [1] @ 33 MHz [1] @ 40 MHz [1], [2] HALT Mode VIN=OV, VCC @ 24 MHz [1] HALT Mode VIN=OV, VCC @ 33 MHz [1] HALT Mode VIN=OV, VCC @ 40 MHz [1], [2] STOP Mode VIN=OV, VCC [1]
ICC1
HALT
ICC2 IALL
STOP and Pause Mode Auto Latch Low Current
Note: [1] All inputs driven to 0V, VCC and outputs floating. [2] Preliminary values, to be characterized.
9
Z86C95 DSP CPS DC-4067-13
AC CHARACTERISTICS External I/O or Memory Read/Write Timing Diagram
R/W, /DM
19 12
20 13
Port 0
A8 - A15
16 21
Port 1
A0 - A7
2 3
D0 - D7 IN
9 10
A0 - A7
/AS
8 4 5 6 11
/DS (Read)
1
17
Port1
A0 - A7
14
D0 - D7 OUT
15 7
A0-A7
/DS (Write)
External I/O or Memory Read/Write Timing
10
Z86C95 DSP CPS DC-4067-13
AC CHARACTERISTICS External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table
TA = 0C to +70C 33 MHz Min Max 15 20 75 10 0 60 35 40 0 20 16 10 12 12 12 90 20 10 15 15 30 30 40 30 40 30 5 15 20 5 15 20 20 10 15 15 35 35 45 35 45 35 5 15 25 0 25 16 12 12 12 12 115 40 22 35 30 40 40 50 45 50 45 15 0 65 40 45 0 40 30 26 30 34 34 160 96 28 0 100 65 80
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 30
Sym TdA(AS) TdAS(A) TdAS(DI) TwAS TdAZ(DSR) TwDSR TwDSW TdDSR(DI) ThDSR(DI) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDO(DSW) ThDSW(DO) TdA(DI) TdAS(DSR) TdDM(AS) TdDS(DM) ThDS(A) TdXT(SCR) TdXT(SCF) TdXT(DSRF) TdXT(DSRR) TdXT(DSWF) TdXT(DSWF) TsW(XT) ThW(XT) TwW
Parameter Address Valid To /AS Rise Delay /AS Rise To Address Hold Time /AS Rise Data In Req'd Valid Delay /AS Low Width Address Float To /DS Fall (Read) /DS (Read) Low Width /DS (Write) Low Width /DS Fall (Read) To Data Req'd Valid Delay /DS Rise (Read) to Data In Hold Time /DS Rise To Address Active Delay /DS Rise To /AS Delay R/W To Valid /AS Rise Delay /DS Rise To R/W Not Valid Delay Data Out To /DS Fall (Write) Delay /DS Rise (Write) To Data Out Hold Time Address Valid To Data Req'd Valid Delay /AS Rise To /DS Fall (Read) Delay /DM Valid To /AS Rise Delay /DS Rise To /DM Valid Delay /DS Rise To Address Valid Hold Time XTAL Falling to SCLK Rising XTAL Falling to SCLK Falling XTAL Falling to/DS Read Falling XTAL Falling to /DS Read Rising XTAL Falling to /DS Write Falling XTAL Falling to /DS Write Rising Wait Set-up Time Wait Hold Time Wait Width (One Wait Time)
40 MHz** Min Max 8 15
Min 22 25
24 MHz Max
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
130
Notes: When using extended memory timing add 2 TpC. Timing numbers given are for minimum TpC. ** Preliminary values, to be characterized.
11
Z86C95 DSP CPS DC-4067-13
AC CHARACTERISTICS (Continued) Timing Diagrams
XTAL1 (External Clock Drive) 22 23
SCLK 24 /DS (Read) 25
26 /DS (Write)
27
XTAL/SCLK To DSR and DSW Timing
T1
T2
TW
TW
TW
T3
T1
XTAL1
SCLK
/AS
/DS
30
/WAIT
28
29
XTAL/SCLK To WAIT Timing 12
Z86C95 DSP CPS DC-4067-13
1 3
Clock
2 7 7 2 3
T IN
4 6 5
IRQ N
8 9
Additional Timing
AC CHARACTERISTICS Additional Timing Table
TA = 0C to +70C 24 MHz 33 MHz Min Max Min Max 42 11 75 3 TpC 8 TpC 100 70 5 TpC 3 TpC 70 5 TpC 3 TpC 100 70 5 TpC 3 TpC 1000 10 30 10 75 3 TpC 8 TpC 100 ns ns 1000 5
No 1 2 3 4 5 6 7 8a 8b 9
Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH
Parameter Input Clock Period Clock Imput Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Times Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times
40 MHz Min Max 25 8 75 3 TpC 8 TpC 1000 5
Units ns ns ns ns
Notes [1] [1] [1] [2] [2] [2] [2] [2,4] [2,5] [2,3]
Notes: [1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request via Port 3. [4] Interrupt request via Port 3 (P33-P31). [5] Interrupt request via Port 30.
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Z86C95 DSP CPS DC-4067-13
AC CHARACTERISTICS Handshake Timing Diagrams
Data In Data In Valid Next Data In Valid
1
3
2
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Output Handshake Timing
14
Z86C95 DSP CPS DC-4067-13
AC CHARACTERISTICS Handshake Timing Table
TA = 0C to +70C Min Max 0 0 40 70 40 0 TpC 0 70 40 40 Data Direction In In In In In In Out Out Out Out Out
No 1 2 3 4 5 6 7 8 9 10 11
Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVIf(RDYf) TdDAVIr(RDYr) TdRDYOr(DAVIf) TdD0(DAV) TdDAV0f(RDYIf) TdRDYIf(DAVOr) TwRDY TdRDYIr(DAVOf)
Parameter Data In Setup Time to /DAV RDY to Data In Hold Time /DAV Width /DAV to RDY Delay DAV Rise to RDY Wait Time RDY Rise to DAV Delay Data Out to DAV Delay /DAV to RDY Delay RDY to /DAV Rise Delay RDY Width RDY Rise to DAV Wait Time
Units ns ns ns ns ns ns ns ns ns ns ns
15
Z86C95 DSP CPS DC-4067-13
AC CHARACTERISTICS (Continued)
A/D Converter Electrical Characteristics VCC = 3.3V 10% Parameter Resolution Integral non-linearity Differential non-linearity Zero Error at 25C Supply Range Power dissapation, no load Clock frequency Input voltage range Conversion time Input capacitance on ANA VAHI range VALO range VAHI --VALO
Notes: Voltage 2.7V - 3.3V Temp 0-70C
Minimum
Typical 8 0.5 0.5
Maximum 1 1 5.0 3.3 40 24 VAHI 2 40 AVCC AVCC-2.5 AVCC
Units Bits LSB LSB mV Volts mW MHz Volts sec pF Volts Volts Volts
2.7
3.0 20
VALO 25 VALO +2.5 ANGND 2.5
D/A Converter Electrical Characteristics VCC = 3.3V 10% Parameter Resolution Integral non-linearity Differential non-linearity Setting time, 1/2 LSB Zero Error at 25C Full Scale error at 25C Supply Range Power dissapation, no load Ref Input resistance Output noise voltage VDHI range at 3 volts VDLO range at 3 volts VDHI-VDLO, at 3 volts Capacitive output load, CL Resistive output load, RL Output slew rate
Notes: Voltage 2.7V - 3.3V Temp 0-70C
Minimum
Typical 8 0.25 0.25 1.5 10
Maximum 1 0.5 3.0 20 0.5 3.3 10K 2.1 0.8 1.9 20
Units Bits LSB LSB sec mV LSB Volts mW Ohms Vp-p Volts Volts Volts pF Ohms V/sec
2.7 2K 1.5 0.2 1.3 50K 1.0
0.25 3.0 10 4K 50 1.8 0.5 1.6
3.0
16
Z86C95 DSP CPS DC-4067-13
A/D Converter Electrical Characteristics VCC = 5.0V 10% Parameter Resolution Integral non-linearity Differential non-linearity Zero Error at 25C Supply Range Power dissapation, no load Clock frequency Input voltage range Conversion time Input capacitance on ANA VAHI range VALO range VAHI --VALO
Notes: Voltage 4.5V -5.5V Temp 0-70C
Minimum
Typical 8 0.5 0.5
Maximum 1 1 45 5.5 85 33 VAHI 2 40 AVCC AVCC-2.5 AVCC
Units Bits LSB LSB mV Volts mW MHz Volts sec pF Volts Volts Volts
4.5
5.0 50
VALO 25 VALO +2.5 ANGND 2.5
D/A Converter Electrical Characteristics VCC = 5.0V 10% Parameter Resolution Integral non-linearity Differential non-linearity Setting time, 1/2 LSB Zero Error at 25C Full Scale error at 25C Supply Range Power dissapation, no load Ref Input resistance Output noise voltage VDHI range at 3 volts VDLO range at 5V volts VDHI-VDLO, at 5V volts Capacitive output load, CL Resistive output load, RL Output slew rate
Notes: Voltage 4.5V - 5.5V Temp 0-70C * 100K for 24 MHz device.
Minimum
Typical 8 0.25 0.25 1.5 10
Maximum 1 0.5 3.0 20 2 5.5 85 10K 3.5 1.7 2.7 30
Units Bits LSB LSB sec mV % FSR Volts mW Ohms Vp-p Volts Volts Volts pF Ohms V/sec
4.5 2K 2.6 0.8 0.9 20K* 1.0
1 5.0 50 4K 50
3.0
17
Z86C95 DSP CPS DC-4067-13
(c) 1994 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056
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