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FAN8037 (KA3037)
7-CH Motor Driver
Features
* * * * * * * * 4-CH balanced transformerless (BTL) driver 3-CH (forward - reverse) control DC motor driver Operating supply voltage (4.5 V ~ 13.2 V) Built-in thermal shut down circuit (TSD) Built-in all channel mute circuit Built-in power save mode circuit Built-in stand by mode circuit Built-in variable regulator
Description
The FAN8037 is a monolithic integrated circuit suitable for a 7-ch motor driver which drives the tracking actuator, focus actuator, sled motor, tray motor, changer motor, panel motor and, spindle motor of the CDP/CAR-CD systems.
48-QFPH-1414
Target Application
* * * * Compact disk player (Tray, Changer) Video compact disk player (Tray, Changer) Car compact disk player (Tray, Changer) Mixing with compact disk player and mini disk player (Tray, Changer, Panel)
Ordering Information
Device FAN8037 Package 48-QFPH-1414 Operating Temp. -35C ~ +85C
Rev. .1.0.2 May. 2000.
(c)2000 Fairchild Semiconductor International
1
FAN8037 (KA3037)
Pin Assignments
REGOX
PVCC1
REGX
SVCC
RESX
VREF
DO1+
OUT1
48
47
IN1.2
46
45
44
43
42
41
40
39
38
37
IN2.1
DO2+
DO1-
IN1.1
1
36
DO2-
IN2.2 OUT2
2 3
35
PGND1 DO3+
34
IN3.1
4
33
DO3-
IN3.2 OUT3
5
32 31
DO4+ DO4-
6
FAN8037
IN4.1 7 30 DO5+
IN4.2 OUT4
8
29
DO5- PGND2
9
28
CTL1
10 11
27
DO6+
FWD1 REV1
26
DO6- DO7+
12
25
13 CTL2
14 FWD2
15 REV2
16 SGND
17 FWD3
18 REV3
19 CTL3
20 SB
21 PS
22 MUTE
23 PVCC2
24 DO7-
2
FAN8037 (KA3037)
Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name IN2.1 IN2.2 OUT2 IN3.1 IN3.2 OUT3 IN4.1 IN4.2 OUT4 CTL1 FWD1 REV1 CTL2 FWD2 REV2 SGND FWD3 REV3 CTL3 SB PS MUTE PVCC2 DO7- DO7+ DO6- DO6+ PGND2 DO5- DO5+ DO4- DO4+ I/O I I O I I O I I O I I I I I I I I I I I I O O O O O O O O CH2 op-amp input (+) CH2 op-amp input (-) CH2 op-amp output CH3 op-amp input (+) CH3 op-amp input (-) CH3 op-amp output CH4 op-amp input (+) CH4 op-amp input (-) CH4 op-amp output CH5 motor speed control CH5 forward input CH5 reverse input CH6 motor speed control CH6 forward input CH6 reverse input Signal groung CH7 forward input CH7 reverse input CH7 motor speed control Stand by Power save All mute Power supply voltage (For CH5, CH6, CH7) CH7 drive ouptut (-) CH7 drive output (+) CH6 drive output (-) CH6 drive output (+) Power ground2 (FOR CH5, CH6, CH7) CH5 drive output (-) CH5 drive output (+) CH4 drive output (-) CH4 drive output (+) Pin Function Descrition
3
FAN8037 (KA3037)
Pin Definitions (Continued)
Pin Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name DO3- DO3+ PGND1 DO2- DO2+ DO1- DO1+ PVCC1 REGOX REGX RESX VREF SVCC IN1.1 IN1.2 OUT1 I/O O O O O O O I O I I I I O CH3 drive output (-) CH3 drive output (+) Power ground 1 (FOR CH1, CH2, CH3, CH4) CH2 drive output (-) CH2 drive output (+) CH1 drive output (-) CH1 drive output (+) Power supply voltage (FOR CH1, CH2, CH3, CH4) Regulator feedback input Regulator output Regulator reset input Bias voltage input Signal supply voltage CH1 op-amp input (+) CH1 op-amp input (-) CH1 op-amp output Pin Function Descrition
4
FAN8037 (KA3037)
Internal Block Diagram
OUT1 48
IN1.2 47
IN1.1 46
SVCC 45
VREF 44
RESX 43
REGX REGOX PVCC1 DO1+ 42 + 41 40 39
DO1- 38
DO2+ 37
IN2.1
1
-+
-
36
DO2-
IN2.2
2 + - 3 + -
- +
- +
35
PGND1
OUT2
34 + - + -
DO3+
IN3.1
4
33
DO3-
IN3.2
5 + -
- +
- +
32
DO4+
OUT3
6 + + - - + -
31
DO4-
IN4.1
7 S W 8 M S C + - + - + - T.S.D D D D D
30
DO5+
IN4.2
29
DO5-
OUT4
9
S W
M S C
28
PGND2
CTL1 10 S W M S C D
27
DO6+
FWD1 11
26 D
STAND BY
DO6-
REV1 12
ALL MUTE POWER SAVE
25
DO7+
13 CTL2
14 FWD2
15
16
17 FWD3
18 REV3
19 CTL3
20 SB
21 PS
22
23
24
REV2 SGND
MUTE PVCC2 DO7-
Notes: 1. SW = Logic switch 2. MSC = Motor speed control 3. D = Output driver
5
FAN8037 (KA3037)
Equivalent Circuits
Description Input OPIN (+) OPIN (-) Pin No. 46,47,1,2 4,5,7,8 Internal circuit
SVCC
SVCC
SVCC
46 1 47
0.05k
0.05k
47 2 58
Input opout
48,3,6,9
SVCC SVCC
48 3 69
CTL
10,13,19
SVCC
SVCC
0.05k 10 13 19
1k
Logic drive FWD input REV input
11,12, 14,15, 17,18
11 12 14 15 17 18 0.05k
SVCC
30k
30k
6
FAN8037 (KA3037)
Equivalent Circuits (Continued)
Description Power save Standby Pin No. 20,21
SVCC SVCC
Internal circuit
20 21
0.05k
50k
50k
Mute
22
SVCC SVCC
0.05k 22
50k
50k
Logic drive output
24, 25 26, 27 29,30
SVCC PVCC2
24 25 26 27 29 30
30k 1k
25k
4-CH drive output
31, 32 33, 34 36, 37 38, 39
31 32 33 34 36 37 38 39
SVCC PVCC1
20k 20k
25k
7
FAN8037 (KA3037)
Equivalent Circuits (Continued)
Description Ref Pin No. 44
SVCC
Internal circuit
SVCC
20k
20k 1k
0.05k 44
1k
RESX
43
SVCC SVCC
0.05k 43
50k
50k
REG0X
41
SVCC SVCC
0.05k 41 1k
REGX
42
SVCC SVCC 0.5k
42
0.05k
60k
25k
8
FAN8037 (KA3037)
Absolute Maximum Ratings ( Ta=25C)
Parameter Maximum Supply Voltage Symbol SVCCMAX PVCC1 PVCC2 Power Dissipation Operating Temperature Storge Temperature Maximum Output Current PD TOPR TSTG IOMAX Value 18 18 18 3note -35 ~ +85 -55 ~ +150 1 Unit V V V W C C A
Notes: 1. When mounted on 70mm x 70mm x 1.6mm PCB 2. Power dissipation reduces 24mW/C for using above TA = 25C 3. Do not exceed PD and SOA (Safe Operating Area)
Pd (mW) 3,000 2,000
1,000 0 0 25 50 75 100 125 150 175 Ambient temperature, Ta [C]
Recommended Operating Conditions ( Ta=25C)
Parameter Operating Supply Voltage Symbol SVCC PVCC1 PVCC2 Min. 4.5 4.5 4.5 Typ. Max. 13.2 SVCC SVCC Unit V V V
9
FAN8037 (KA3037)
Electrical Characteristics
(SVCC = PVCC1 = PVCC2 = 8V, TA = 25C, unless otherwise specified) Parameter Quiescent circuit current Power save on current Stand by on voltage Stand by off voltage Power save on voltage Power save off voltage All mute on voltage All mute off voltage DRIVER CIRCUIT (RL=12) Output offset voltage Maximum output voltage 1 Maximum output voltage 2 Closed-loop voltage gain Slew rate INPUT OPAMP CIRCUIT Input offset voltage Input bias current High level output voltage Low level output voltage Output sink current Output source current Open loop voltage gain Slew rate VOF IB VOH VOL ISINK ISOURCE GVO SR RL=Open RL=Open RL=50 RL=50 VIN=-75dB Square, Vout=2Vp-p, f=120kHz -30 7.2 2 2 7.7 0.2 4 4 70 2.5 +30 300 0.5 mV nA V V mA mA dB V/s VOO VOM1 VOM2 AVF SR VIN=2.5V VCC=PVCC1=PVCC2=8V, RL=12 VCC=PVCC1=PVCC2=13V, RL=24 VIN=0.1Vrms,f=1kHz Square, Vout=4Vp-p,f=120kHz -80 5.5 10.5 10.5 6.5 11.5 12 2 +80 13.5 mV V V dB V/s Symbol ICC IPS VSBON VSBOFF VPSON VPSOFF VMON VMOFF Conditions Under no-load Pin21=GND Pin20=Variation Pin20=Variation Pin21=Variation Pin21=Variation Pin22=Variation Pin22=Variation Min. 15 2 2 2 Typ. 25 1 Max. 35 2 0.5 0.5 0.5 Units mA mA V V V V V V
10
FAN8037 (KA3037)
Electrical Characteristics (Continued)
(SVCC = PVCC1 = PVCC2 = 8V, TA = 25C, unless otherwise specified) Parameter Input high level voltage Input low level voltage Output voltage 1 Output voltage 2 Output voltage 3 Output load regulation Output offset voltage 1 Output offset voltage 2 Load regulation Line regulation Regulator output voltage 1 Regulator output voltage 2 Regulator reset on voltage Regulator reset off voltage Symbol VIH VIL VO1 VO2 VO3 VRL VOO1 VOO2 VRL VCC VREG1 VREG2 Reson Resoff Conditions VCC=8V, VCTL=2.5V, RL=12 VCC=8V, VCTL=3V, RL=45 VCC=13V, VCTL=4.5V, RL=45 VCTL=3V, IL=100mA 400mA VIN=5V, 5V VIN=0V, 0V IL=0 200mA IL=200mA, VCC=6V 9V IL=100mA IL=100mA Pin43=Varivation Pin43=Varivation Min. 2 -40 -40 -40 -20 4.75 3.135 2 Typ. 5 6 9 300 0 0 5.0 3.3 Max. 0.5 700 +40 +40 +10 +30 5.25 3.465 0.5 Units V V V V V mV mV mV V mV V V V V
TRAY, CHANGER,PANEL DRIVE CIRCUIT (RL=45)
VARIABLE REGULATOR CIRCUIT
11
FAN8037 (KA3037)
Application Information
1. THERMAL SHUTDOWN
SVCC
* When the chip temperature reaches to 175C, then the TSD circuit is activated. * This shuts down the bias current of the output drivers, and all the output drivers are in cut-off state. Thus the chip temperature begins to decrease. * when the chip temperature falls to 150C, the TSD circuit is deactivated and the output drivers are normally operated. * The TSD circuit has the hysteresis temperature of 25C.
IREF R1 Q0 R2 Hysteresis Ihys R3
Output driver bias
2. ALL MUTE FUNCTION * When the pin22 is high, the TR Q1 is turned on and Q2 is off, so the bias circuit is enabled. On the other hand, when the pin22 is Low (GND) , the TR Q1 is turned off and Q2 is on, so the bias circuit is disabled. * This function will cause all the output drivers to be in mute state. * Truth table is as follows; Pin#22 HIGH LOW FAN8037 MUTE-OFF MUTE-ON
SVCC
Bias blocks (4-Ch BTL and 3-Ch logic loading) Q2
22 Q1
3. POWER SAVE FUNCTION * When the pin21 is high, the TR Q3 is turned on and Q4 is off, so the bias circuit is enabled. On the other hand, when the pin21 is Low (GND) , the TR Q3 is turned off and Q4 is on, so the bias circuit is disabled. * That is, this function will cause all the circuit blocks of the chip except for the variable regulator to be in the off state. thus the low power quiescent state is established * Truth table is as follows; Pin#21 HIGH LOW FAN8037 POWER SAVE OFF POWER SAVE ON
SVCC
Main Bias (except for variable reg.) Q4
21 Q3
12
FAN8037 (KA3037)
4. STANDBY FUNCTION * When the pin20 is high, the TR Q5 is turned on and Q6 is off, and the bias circuit is enabled. On the other hand, when the pin20 is Low (GND) , the TR Q5 is turned off and Q6 is on, and the bias circuit is disabled. * This function will cause the output drivers of the 4-CH BTL circuit (Focus, Tracking, Spindle, Sled) to be in off state. * Truth table is as follows Pin20 HIGH LOW KA3037 STANDBY OFF STANDBY ON
SVCC
Bias block (4-CH BTL output driver) Q6
20 Q5
5. REGULATOR & RESET FUNCTION The regulator and reset circuits are illustrated in the figure 1. * The external circuit is composed of the PNP transistor(KSB772), capacitor(about 33F) and 2 feedback resistors. * The capacitor is used as a ripple filter and should have good temperature characteristics. * The regulator output voltage is determined as follows. VREG = (1+R1/R2) x 2.5 * When the voltage of the pin 43 (Vreset) is high, the regulator circuit operates normally. If the voltage of pin 43 is low, the regulator circuit is disabled .
SVCC
KSB772
Vreset R1 R2 43 42 41
VREG 33F
40
2.5V
- +
FAN8037
Figure 1. Regulator circuit
13
FAN8037 (KA3037)
6. FOCUS, TRACKING ACTUATOR, SPINDLE, SLED MOTOR DRIVE PART
R2 R1 OPin+ OPin46 47 48 1 2 3 Vref 4 5 6 7 8 9 44 + - Vin R1 Vp R2 R1 - + R2 R2 + - R2 M DON 38 36 33 31 DOP 39 37 34 32
PVCC1 Dp 60k + 62k Qp - Vp
* Vref is given by the external bias voltage of the pin 44. * The input signal (Vin) through pins 46,1,4 and 7 is amplified one time and then fed to the output stage. (assume that input opamp was used as a buffer) * The total closed loop voltage gain is as follows
Vin = Vref + V DOP = Vp + 2 V DON = Vp - 2 V Vout = DOP - DON = 4 V Vout Gain = 20 log ------------ = 20 log 4 = 12dB V
* To change the total closed loop voltage gain, use the input opamp as an amplifier * The output stage is the balanced transformerless (BTL) driver. * The bias voltage Vp is expressed as ;
62k Vp = ( PVCC1 - VDp - VcesatQp ) x ------------------------- + VcesatQp 60k + 62k PVCC1 - VDp + VcesatQp = -------------------------------------------------------------------------- + VcesatQp 1.97
----------
(1)
14
FAN8037 (KA3037)
7. TRAY, CHANGER,PANEL MOTOR DRIVE PART
out 1 24 26 29
M
out 2 25 27 30
D
D
LEVEL SHIFT 6.5V CTL1,2,3 10 13 19 S.W 0 3.25V VCTL M.S.C V(out1,out2)
IN
IN
FWD 11 14 17 12
REV 15 18
* Rotational direction control The forward and reverse rotational direction is controlled by FWD (pin 11,14, 17) and REV (pin 12,15,18) and the input conditions are as follows. INPUT FWD H H L L REV H L H L OUT 1 Vp H L OUTPUT OUT 2 Vp L H State Brake Forward Reverse Hign impedance
* Where Vp(Power reference voltage) is approximately about 3.75V at PVCC2=8V ) according to equation (1). * Where out1 pins are pins24,26,29 and out2 pins are pins25,27,30 * Motor speed control (When SVCC=PVCC2=8V) - Maximum torque is obtained when the pins (10,13 and 19 (CTL1, 2, 3)) are open. - If the voltages of the pins (10,13 and 19 (CTL1, 2, 3)) are 0V, the motor will not operate. - When the control voltage of the pins 10,13 and 19 (CTL1, 2, 3) are between 0 and 3.25V, the differential output voltage(V(out1,out2)) is about two times of control voltage. Hence, the control to the differential output gain is two. - When the control voltage is greater than 3.25V, the output voltage is saturated at the 6.5V due to the output swing limitation.
15
FAN8037 (KA3037)
8. BOOTSTRAPPED OPERATION * IC has two kinds of power supplies, the power supply , SVCC is for predrivers and the other circuit blocks(SVCC). PVCC1 and PVCC2 are for the power transistors. * When SVCC=PVCCn (n=1,2), no bootstrapped operation occurs. Thus the single-ended maximum output voltage is
SVCC - ( VcesatQ3 + Vbe1 ) SVCC - 1V
Q1
SVCC
PVCC
Q3
* If larger output swing is requied, use the bootstrap function. When the bootsrap function is operated. SVCC > PVCCn + 1V * In this mode, the single-ended maximum output voltage is PVCCn - VcesatQ1 PVCCn - 0.5 ; Thus wide output dynamic range can be obtained.
Q2
Vout
PreDriver (PD)
Power TRs
16
FAN8037 (KA3037)
Typical Performance Characteristics
ICC (mA)
40 35 30 25 20 15 10 5 0 4 6 8 10 12 14 16 18
VCC & ICC
40 35 30 25 20 15 10 5 0
ICC (mA)
TEMP & ICC
VCC=4.5V VCC=13.2 V VCC=8V
-50
-30
-10
10
30
50
70
90
110
VCC (V)
TEMP (C)
VOM1 (V)
14 12
VCC & VOM1
14 12
VCC & VOM2 VOM2 (V)
10 8 6 4 2 0 4 6 8 10 12
VOM1_CH1 VOM1_CH2 VOM1_CH3 VOM1_CH4
10 8 6 4 2 0 4 6 8 10 12 14
VO M2_C H1 VO M2_C H2 VO M2_C H3 VO M2_C H4
14
VCC (V)
VCC (V)
8 7 6 5 4 3 2 1 0
VOUT (V)
IOM & VOUT
13
AVF (dB)
VCC & AVF
CH 1_UPP CH 1_LOW CH 2_UPP CH 2_LOW CH 3_UPP CH 3-LOW CH 4_UPP CH 4_LOW
11
9
7
5
0
0.2
0.4
0.6
0.8
1
4
6
8
10
12
14
IOM (A)
VCC (V)
17
FAN8037 (KA3037)
Typical Performance Characteristics (Continued)
VOM(V)
12
TEMP & VOM
6 5 4
VO1 (V)
VCC & VO1
8
3
4
VOM1 VOM 2
2
VO _CH5
1 0
VO _CH6 VO _CH7
0 -50
-30
-10
10
30
50
70
90
110
6
8
10
12
14
TEMP (C)
VCC (V)
14 12 10
VO(V)
Vctl & VO (Loading)
12 10 8
VO(V)
TEMP & VO (Loading)
8
6
6 4 2 0 0 2 4 6
VO_12 ohm VO_24 ohm
4
VO1
2 0 -50
VO2 VO3
-30
-10
10
30
50
70
90
110
Vctl (V)
TEMP (C)
6 5 4 3 2 1 0
VREG(V)
VCC & VREG
6 5 4 3 2
VREG1 VREG2
VREG(V)
TEMP & VREG
1 0 -50
VREG1 VREG2
4
6
8
10
12
14
-30
-10
10
30
50
70
90
110
VCC (V)
TEMP (C)
18
FAN8037 (KA3037)
Typical Performance Characteristics (Continued)
Isource (mA)
7 6 5 4 3 2 1 0
VCC & Isource
50 45 40 35 30 25 20 15 10 5 0
Isink (mA)
VCC & Isink
4
6
8
10
12
14
VCC (V)
4
6
8
10
12
14
VCC (V)
19
FAN8037 (KA3037)
Test Circuits
VCC
1
VREF
50 R2 + 1000F RIPPLE R1 22F + IL
2.5V OP IN (+) OP IN (-) OP OUT 48 OUT1 47 IN1.2 46 IN1.1
100F +
2
RL1
DO1+
DO1-
REGOX
SVCC
RESX
REGX
VREF
PVCC1
DO2+
OP IN (+) OP IN (-) OP OUT
IN2.1 1
45
44
43
42
41
40
39
38
37 36 DO2-
RL2
2 IN2.2 3 OUT2 4 IN3.1 5 IN3.2 6 OUT3
PGND2 35 DO3+ 34 RL3 DO3- 33 DO4+ 32 RL4 DO4- 31
OP IN (+) OP IN (-) OP OUT
FAN8037
OP IN (+) OP IN (-) OP OUT 7 IN4.1 8 IN4.2 9 OUT4 10 CTL1 PVCC2 SGND MUTE FWD2 FWD3 REV2 REV3 11 FWD1 CTL2 REV1 IN1B 12 DO5+ 30 RL5 DO5- 29 PGND1 28 DO6+ 27 DO6- DO7- RL6 26 DO7+ 25 RL7 IL IL IL IL
CTL1 IN1A
CTL3
SB 20
13
14
15
16
17
18
19
21
PS
22
23
24
IL CTL2 IN2A IN2B IN3A IN3B CTL3
IL
OP-AMP PART
OPIN(+) OPIN(-) OPOUT
A 1 VPULSE 2 VA 3 1
B D 2 VB C 1 2 VCC 3 50 VOUT
20
FAN8037 (KA3037)
Typical Application Circuits 1
[Voltage control mode]
VCC REGOUT R2 22F R1 +
FOCUS
TRACKING
48 OUT1 IN2.1 1
47 IN1.2
46 IN1.1
45 SVCC
44 VREF
43 RESX
42 REGX
41 REGOX
40 PVCC1
39 DO1+
38 DO1-
37 DO2+ 36 DO2-
2 IN2.2 3 OUT2 4 IN3.1 5 IN3.2 6 OUT3
PGND2 35 DO3+ 34 M SLED DO3- 33 DO4+ 32 M SPINDLE DO4- 31
FAN8037
7 IN4.1 8 IN4.2 9 OUT4 10 CTL1 PVCC2 SGND MUTE FWD2 FWD3 REV2 REV3 11 FWD1 CTL2 12 REV1 DO5+ 30 DO5- 29 PGND2 28 M TRAY
DO6+ 27
M CHANGER DO6- 26 DO7- 24 DO7+ 25 M PANEL CLT3
SB 20
13
14
15
16
17
18
19
21
PS
22
23
ALL MUTE POWER SAVE FOCUS, TRACKING, SLED SPINDLE MUTE
VREF
FOCUS TRACKING SLED SPINDLE INPUT INPUT INPUT INPUT
TY CG PL TRAY CHANGER PANEL INPUT CONTROL INPUT INPUT
Where TY is tray motor. CG is changer motor PL is panel motor
[SERVO PRE AMP]
[CONTROLLER]
Notes: Radiation pin is connected to the internal GND of the package. Connect the pin to the external GND.
21
FAN8037 (KA3037)
Typical Application Circuits 2
[Differential PWM control mode ]
VCC REGOUT R2 22F R1 +
FOCUS
TRACKING
48 OUT1 IN2.1 1
47 IN1.2
46 IN1.1
45 SVCC
44 VREF
43 RESX
42 REGX
41 REGOX
40 PVCC1
39 DO1+
38 DO1-
37 DO2+ 36 DO2-
2 IN2.2 3 OUT2 4 IN3.1 5 IN3.2 6 OUT3
PGND2 35 DO3+ 34 M SLED DO3- 33 DO4+ 32 M SPINDLE DO4- 31
FAN8037
7 IN4.1 8 IN4.2 9 OUT4 10 CTL1 PVCC2 SGND MUTE FWD2 FWD3 REV2 REV3 11 FWD1 CTL2 12 REV1 DO5+ 30 DO5- 29 PGND2 28 M TRAY
DO6+ 27
M CHANGER DO6- 26 DO7- 24 DO7+ 25 M PANEL CLT3
SB 20
13
14
15
16
17
18
19
21
PS
22
23
ALL MUTE POWER SAVE FOCUS, TRACKING, SLED SPINDLE MUTE
VREF
FOCUS TRACKING SLED SPINDLE INPUT INPUT INPUT INPUT
TY CG PL TRAY CHANGER PANEL CONTROL INPUT INPUT INPUT
Where TY is tray motor. CG is changer motor PL is panel motor
[SERVO PRE AMP]
[CONTROLLER]
Notes: Radiation pin is connected to the internal GND of the package. Connect the pin to the external GND
22
FAN8037 (KA3037)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 12/1/00 0.0m 001 Stock#DSxxxxxxxx 2000 Fairchild Semiconductor International
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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