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CXA1782CQ/CR
RF Signal Processing Servo Amplifier for CD players For the availability of this product, please contact the sales office.
Description The CXA1782CQ/CR is a bipolar IC with built-in RF signal processing and various servo ICs. A CD player servo can be configured by using this IC, DSP and driver. Features * Low operating voltage (VCC - VEE = 3.0 to 11.0V) * Low power consumption (39mW, VCC = 3.0V) * Supports pickup of either current output, voltage output * Automatic adjustment comparator for tracking balance gain * Single power supply and positive/negative dual power supplies Applications * RF I-V amplifier, RF amplifier * Focus and tracking error amplifier * APC circuit * Mirror detection circuit * Defect detection and prevention circuits * Focus servo control * Tracking servo control * Sled servo control * Comparators of tracking adjustment for balance and gain Structure Bipolar silicon monolithic IC CXA1782CQ 48 pin QFP (Plastic) CXA1782CR 48 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25C) 12 V * Supply voltage VCC * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 833 (CXA1782CQ) mW 457 (CXA1782CR) mW Recommended Operating Condition Operating supply voltage VCC - VEE 3.0 to 11.0
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E95908C78
CXA1782CQ/CR
Block Diagram
RF_M
PHD2
PHD1
PHD
RF_O
RF_I
CP
36
35
34
33
32
31
30
29
28
CB
27
26
25
APC LEVEL S I IL 24 SENS
FOK
CC1
CC2
LD
TTL
23 C.OUT
RF IV AMP1 MIRR FOK DFCT 22 XRST
TTL RF IV AMP2 FE_BIAS 37 TTL *I IL DATA REGISTER *INPUT SHIFT REGISTER *ADRESS.DECODER
21 DATA
I IL
20 XLT
F 38
FE AMP F IV AMP
I IL
*OUTPUT DECODER
19 CLK
E 39 FZC COMP E IV AMP EI 40 TE AMP
TOG1 to 3 FS1 to 4 TG1 to 2 TM1 to 7 BAL1 to 3
PS1 to 4
18 Vcc
BAL2
BAL1
BAL3
HPF COMP LPF COMP
*TRACKING PHASE COMPENSATION TM6
*I SET
17 ISET
VEE 41 TEO 42 TG1
16 SL_O TM5
TOG2
TOG1
TOG3
TM4 TZC COMP DFCT TM1 *FCS PHASE COMPENSATION FS1 TM7 TM3 TM2
15 SL_M
LPFI 43 14 SL_P TEI 44 ATSC 45 TZC 46 TDFCT 47 DFCT VC 48 FS4 *WINDOW COMP. ATSC FS2 TG2
13 TA_O
1
2
3
4
5
6
7
8
9
10
11
*F SET
12
FE_M
FDFCT
SRCH
FE_O
TGU
FSET
FLB
FEI
* * * *
The switch state in Block Diagram is for initial resetting. Switch turns to side for 1 and to * side for 0 in Serial Data Truth Table. DFCT switch turns to side when defect signal generates for DEFECT = E in Serial Data Truth Table. TG1 switch turns to side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1. -2-
TA_M
FEO
FGD
TG2
CXA1782CQ/CR
Pin Description Pin No. Symbol I/O Equivalent circuit Description
25p 147 1 174k 51k 300 10k 9k
1
FEO
O
Focus error amplifier output. Connected internally to the FZC comparator input.
2
FEI
I
2
147 100k 147
Focus error input.
3
FDFCT
I
3
Capacitor connection pin for defect time constant.
68k 147
4
FGD
I
4 130k 20
Ground this pin through a capacitor when decreasing the focus servo high-frequency gain.
5
FLB
I
40k 5
External time constant setting pin for increasing the focus servo lowfrequency.
6
FE_O
O
6
Focus drive output.
13
TA_O
O
13 16
Tracking drive output.
16
SL_O
O
250
Sled drive output.
147
90k
7
FE_M
I
7 50k
Focus amplifier inverted input.
-3-
CXA1782CQ/CR
Pin No.
Symbol
I/O
Equivalent circuit
Description
147
8
SRCH
I
8 50k 11
External time constant setting pin for generating focus servo waveform.
110k
9
TGU
I
20k 9 82k
External time constant setting pin for switching tracking high-frequency gain.
10
TG2
I
10 470k 2
External time constant setting pin for switching tracking high-frequency gain.
147k
11
FSET
I
11 15k 15k
High cut-off frequency setting pin for focus and tracking phase compensation amplifier.
100k
12
TA_M
I
147 12 11
Tracking amplifier inverted input.
14
SL_P
I
147 14
Sled amplifier non-inverted input.
147
15
SL_M
I
15 22
Sled amplifier inverted input.
-4-
CXA1782CQ/CR
Pin No.
Symbol
I/O
Equivalent circuit
Description
147
17
ISET
I
17
Setting pin for Focus search, Track jump, and Sled kick current.
19 20 21 22
CLK XLT DATA XRST
I
15
Serial data transfer clock input from CPU. (no pull-up resistance) Latch input from CPU. (no pull-up resistance) Serial data input from CPU. (no pull-up resistance) Reset input; resets at Low. (no pull-up resistance)
I I I
19 20 21 22
147
1k
23
C. OUT
O
20k 147 23 24
Track number count signal output.
24
SENS
O
100k
Outputs FZC, DFCT, TZC, gain, balance, and others according to the command from CPU.
20k
25
FOK
O
147 25 40k
Focus OK comparator output.
100k
26
CC2
I
147 28 147 27
Input for the DEFECT bottom hold output with capacitance coupled.
27
CC1
O
DEFECT bottom hold output.
147 26
28
CB
I
Connection pin for DEFECT bottom hold capacitor.
-5-
CXA1782CQ/CR
Pin No.
Symbol
I/O
Equivalent circuit
Description
147 29
29
CP
I
Connection pin for MIRR hold capacitor. MIRR comparator non-inverted input.
30
RF_I
I
147 30
Input for the RF summing amplifier output with capacitance coupled. RF sunning amplifier output. Eye-pattern check point.
147 31 147 32
31
RF_O
O
32
RF_M
I
RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between this pin and RFO pin.
10k 1k
33
LD
O
33
APC amplifier output.
17
34
PHD
I
147 34
APC amplifier input.
10k
35 36
PHD1 PHD2
I I
147 35 36 100 11.6k
RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + D pins.
-6-
CXA1782CQ/CR
Pin No.
Symbol
I/O
Equivalent circuit
Description
32k
164k
37
FE_BIAS
I
37 25p 8
Bias adjustment of focus error amplifier.
12p 260k
38 39
F E
I I
147 38 39 10 513
F I-V and E I-V amplifier inverted input. Connect these pins to photo diodes F and E.
6.8k 102k 57k 260k
28k
40
EI
--
40
20.3k
I-V amplifier E gain adjustment. (When not using automatic balance adjustment)
147
42
TEO
O
42
12k 23k 11k 150k 10k
4.8k
Tracking error amplifier output. E-F signal is output.
150k
147
43
LPFI
I
43
Comparator input for balance adjustment. (Input from TEO through LPF)
-7-
CXA1782CQ/CR
Pin No.
Symbol
I/O
Equivalent circuit
Description
44
TEI
I
44
147
100k
Tracking error input.
147
47
TDFCT
I
47
Capacitor connection pin for defect time constant.
1k 10k
100k
45
ATSC
I
45 100k 1k
Window comparator input for ATSC detection.
10k
46
TZC
I
46 75k
Tracking zero-cross comparator input.
48
VC
O
50 48
120
(VCC + VEE)/2 DC voltage output.
120
VC
-8-
Electrical Characteristics
SW conditions 4 10 RST 18 41 -20 -50 1kHz input ratio V1 = 100mVDC V1 = -100mVDC 1 V1 = 1kHz I/O ratio V1 = 1kHz I/O ratio 25.1 1.2 -- -120 27.0 27.0 -3.0 V1 = 100mVDC V1 = 100mVDC 42 3F 3E V1 = 1kHz TOG1, 2, 3: OFF V1 = 1kHz TOG1: ON Reference to F0 3D V1 = 1kHz TOG2: ON Reference to F0 3B O O 37 36 V1 = 1kHz TOG3: ON Reference to F0 V1 = 1kHz TOG1, 2, 3: OFF V1 = 1kHz BAL1: ON Reference to E0 35 V1 = 1kHz BAL2: ON Reference to E0 1.0 -- -25 0.5 -2.33 0 28.1 1.3 -0.9 0 30.0 30.0 0 1.3 -1.3 0 3.5 -1.83 -14 31 10 14 20 -10 50 31.1 -- -0.3 120 33.0 33.0 3.0 -- -1.0 25 6.5 -1.33 11 13 12 14 15 16 Min. Typ. 5 6 7 8 17 18 9 SD ment pin Max. mA mA mV dB V V mV dB dB dB V V mV dB dB
Measure-
(VCC = 1.5V, VEE = -1.5V, Ta = 25C)
Ratings Measurement conditions Unit
Item
1
2
3
T1
Current consumption 1
T2
Current consumption 2
T3
Offset
T4
Voltage gain
O
O
RF amplifier
T5
Max. output voltage-High O
T6
Max. output voltage-Low
O
T7
Offset
T8
Voltage gain 1
O
T9
Voltage gain 1
O
FE amplifier
T10
Voltage gain difference
TE amplifier
-9-
O
T11
Max. output voltage-High
O
T12
Max. output voltage-Low
O
T13
Offset
T14
Voltage gain F0
O
T15
Voltage gain F1
O
T16
Voltage gain F2
O
-3.93
-3.43
-2.93
dB
T17
Voltage gain F3
O
-6.69 -0.6 0.1
-6.19 2.4 0.4
-5.69 5.4 0.7
dB dB dB
T18
Voltage gain E0
T19
Voltage gain E1
CXA1782CQ/CR
T20
Voltage gain E2
0.4
0.7
1.0
dB
SW conditions 4 6 10 33 3F O O O O O O O 08 6 T29 + T8 (or T9) O O O O O 08 08 02 03 00 O 25 24 13 T37 + T14 O O O Output gain difference between SD = 20 and SD = 25. V1 = -0.5VDC 1.0 1.3 Pin 1 threshold (preliminary) 00 Output gain difference between SD = 00 and SD = 08. V1 = 200mVDC V1 = -200mVDC 1.0 -- -640 360 185 12.25 16.1 1.3 -1.3 -500 500 225 14.6 18.1 48 O 0.8mA sink V2 = 170mV V2 = 145mV 33 V2 = 120mV -900 -900 -180 -200 -100 18 49 21.0 51 3F V1 = 1VDC BAL2: ON -- V1 = 1VDC BAL2: ON 0.5 -0.6 0.6 42 V1 = 1kHz BAL3: ON Reference to E0 1.08 1.38 1.68 -- -0.5 -480 380 1120 500 100 24 53 -35 -- -1.0 -360 640 265 17.6 20.1 -39 11 12 13 16 Typ. Min. 14 15 Max. dB V V mV mV mV mV mV dB dB dB V V mV mV mV dB dB dB 7 O 5 17 18 8 9 SD ment pin
Measure-
Ratings Measurement conditions Unit
Item
1
2
3
T21
Voltage gain E3
TE amplifier
T22
Max. output voltage-High
O
T23
Max. output voltage-Low
T24
Output voltage 1
APC
T25
Output voltage 2
T26
Output voltage 3
T27
Output voltage 4
T28
Center amplifier output offset
T29
DC voltage gain
FCS servo
TRK servo
- 10 -
T30
FCS total gain
T31
Feed through
T32
Max. output voltage-High
T33
Max. output voltage-Low
T34
Search voltage (-)
T35
Search voltage (+)
T36
FZC threshold
O
T37
DC voltage gain
T38
TRK total gain
T39
Feed through
CXA1782CQ/CR
T40
Max. output voltage-High
V
SW conditions 4 6 10 O -1.3 -640 -500 500 -15 15 -20 12 120 25 25 20 25 16 Output gain difference between SD = 20 and SD = 25. V1 = +0.4VDC V1 = -0.4VDC 23 22 O O O O 10 24 O O 14 23 Measures at C. OUT pin. Measures at C. OUT pin. Measures at C. OUT pin. Measures at SENS pin. Measures at SENS pin. Measures at SENS pin. Measures at SENS pin. 1.8 2.5 0.5 1.8 1 -750 450 30 0.3 1.0 1.3 -1.3 -600 600 -1.0 -450 750 -400 50 -34 0 17 130 -356 360 10 7 24 -25 -360 640 -7 25 20 22 140 -330 -1.0 2C 28 O O O O O O O O O O 38 30 25 25 25 25 13 V1 = +0.5VDC V mV mV mV mV mV mV mV mV dB dB V V mV mV kHz Vp-p Vp-p kHz kHz Vp-p 11 12 13 16 Min. Typ. 14 15 Max. O 7 5 8 17 18 9 SD ment pin
Measure-
Ratings Measurement conditions Unit
Item
1
2
3
T41
Max. output voltage-Low
T42
Jump output voltage (-)
T43
Jump output voltage (+)
T44
ATSC threshold (-)
T46
TRK Servo
T45
ATSC threshold (+)
TZC threshold
T47
BAL COMP threshold
T48
GAIN COMP threshold
T49
FOK threshold
T50
DC open gain
T51
Feed through
T53
Sled
MIRR
DEFECT
- 11 -
T52
Max. output voltage-High
Max. output voltage-Low
T54
Kick voltage (-)
T55
Kick voltage (+)
T56
Max. operating frequency
T57
Min. input operating voltage
T58
Max. input operating voltage
T59
Min. operating frequency O
O
T60
Max. operating frequency
O
O
T61
Min. input operating voltage O
O
CXA1782CQ/CR
T62
Max. input operating voltage
O
O
Vp-p
CXA1782CQ/CR
Electrical Characteristics Measurement Circuit
VEE Vcc V2
S17
S16
10k
3000p
S2
1000p
S1
10k
36
35
10k
22k
34
33
32
31
S15
30
29
28
27
26
25
RF_I
RF_M
RF_O
37 S3 S4 10k 390k 390k
CC1
FOK
PD2
PD1
CC2
PD
CP
CB
LD
10k
3300p
FE_BIAS
SENS
24 10k
Vcc Vcc 10k XRST DATA XLT CLK
38 F 39 E 40 EI
C. OUT 23 XRST 22 DATA 21 XLT 20 CLK 19 Vcc 18 ISET 17
VEE
A
S18 S5
41 VEE 42 TEO 43 LPFI
A
240k
Vcc
V1 AC DC
S6 44 TEI S7 45 ATSC S8 46 TZC 47 TDFCT VEE
SL_O 16
60k
SL_M 15 SL_P 14 S14
13k 5.1k 10k
FDFCT
FE_M
FSET
FGD
TGU
FEO
FEI
FLB
TG2
200k S13
48 VC
TA_M
FE_O
V
SRCH
0.1 S9
TA_O
13
1
2
3
4
5
6 100k
7
8
9
10 S12
11
12
0.1
10k
S10
47k
S11
- 12 -
10k
200k
0.015
510k
100k
CXA1782CQ/CR
Application Circuit (Dual 5V power supplies)
Vcc Vcc 1k 1/0.3V A C B D VEE 10H 10
100/6.3V
1/6.3V
100 500
0.033
22k 0.01
0.033
CP
RF M
47k F E
37 VEE FE_BIAS 38 F 39 E 40 EI 41 VEE VEE 42 TEO
RF O
CC1
FOK
CC2
PD1
PD2
LD
Vcc
36
35
34
33
32
31
0.01
30
29
28
27
26
RF I
PD
CB
MICRO COMPUTER
25 24 DSP DSP MICRO COMPUTER DSP DSP DSP SENS C. OUT 23 XRST 22 DATA 21 XLT 20 CLK 19 Vcc 18 120k ISET 17 VEE
100k 150k
Vcc
0.01
0.01
43 LPFI 44 TEI 45 ATSC 46 TZC 47 TDFCT
0.022
8.2k 100k
SL M 15 SL P 14
FDFCT
SRCH
0.1
FE M
TA M
FE O
FGD
TGU
FEO
10
FLB
TG2
FEI
48 VC
FSET
TA O
13 22 15k 100k
2200p 0.1
680k
0.1
22k
4.7
82k
Driver DSP DSP MICRO COMPUTER DSP DSP DSP Driver
1
2
3
4
5
6
7
8
9
10
11
12
0.1
0.033 Vcc
Application Circuit (Single +3V power supply)
Vcc Vcc 1k 1/0.3V A C B D 10H 10
100/6.3V
1/6.3V
Driver
CP
RF M
47k F E
37
RF O
CC1
FOK
CC2
PD1
PD2
LD
Vcc
36
35
34
33
32
31
0.01
22k 0.01
0.033
100 500
0.033
30
29
28
27
26
RF I
PD
CB
MICRO COMPUTER
25 24
FE_BIAS
SENS
38 F 39 E 40 EI 41 VEE 42 TEO
C. OUT 23 XRST 22 DATA 21 XLT 20 CLK 19 Vcc 18 120k ISET 17 Vcc
100k 150k
0.01
0.01
43 LPFI 44 TEI 45 ATSC 46 TZC 47 TDFCT
0.022
8.2k 100k
SL M 15 SL P 14
FDFCT
SRCH
0.1 10 Vcc 10
FE M
TA M
FE O
FGD
TGU
FEO
FLB
TG2
FEI
48 VC
FSET
TA O
13 22 15k 100k
2200p 0.1
0.1 680k
0.1
22k
4.7
82k
1
2
3
4
5
6
7
8
9
10
11
12
0.015
BPF
SL O 16
0.015
100k
510k
3.3
Driver
Vcc
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 13 -
0.015
100k
0.033
510k
0.015
3.3
BPF
SL O 16
Driver
Driver
CXA1782CQ/CR
Description of Functions RF Amplifier The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted via a 58k equivalent resistor by the PD I-V amplifiers. these signals are added by the RF summing amplifier, and the photo diode (A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be performed at this pin.
1k 3.3
22k RF_M A 58k C PD1 35 iPD1 PD1 IV AMP VC PD2 iPD2 36 PD2 IV AMP VC VB 10k 58k VC VA 10k 32 RF_O 31
B
RF SUMMING AMP
D
The low frequency component of the RFO output voltage is VRFO = 2.2 x (VA + VB) = 127.6k x (iPD1 + iPD2).
Focus Error Amplifier The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and output current-voltage converted voltage of the photo diode (A + C - B - D).
25p 174k VB VA 32k 1 FEO 32k 25p 87k 164k FE_BIAS 37 VEE 47k VCC FE AMP
- (B + D) - (A + C)
VC
The FEO output voltage (low frequency) is VFEO = 5.4 x (VA - VB) = (iPD2 - iPD1) x 315k. Be aware that the rotation of the focus bias volume has reversed for the usual CD RF IC.
- 14 -
CXA1782CQ/CR
Tracking Error Amplifier The photo diode currents input to E and F pins are each current-voltage converted by the E I-V and F I-V amplifiers.
1k 3.3
RF1 260k 12p F 38 VF 30k
TE AMP 96k
13k
RF2
iF
VC
96k
F I-V AMP
30k
12k
26k
RF3
42
TOG1 22k
TOG2 10k
TOG3 4.8k
10k
TEO
RE1 260k 12p
VC
VC
6.8k
E iE 39 VE
RE2
VC
20.3k
BAL1 102k
VC 40 EI
The CXA1782 tracking block has built-in circuits for balance and gain adjustments to enable software-based automatic adjustment. The balance adjustment is performed by varying the combined resistance value of the T-configured feedback resistance at E I-V AMP. F I-V AMP feedback resistance = RF1 + RF2 + RF1 x RF2 = 403k RF3 E I-V AMP feedback resistance = RE1 + RE2 + RE1 x RE2 RE3
Vary the value of RE3 in the formula above by using the balance adjustment switches (BAL1 to BAL3). For the gain adjustment, the TE AMP output is resistance-divided by the gain adjustment switches (TOG1 to TOG3), and it is output at Pin 42. These balance and gain adjustment switches are controlled through software commands.
- 15 -
BAL2
BAL3
RE3
VC
E I-V AMP
57k
28k
CXA1782CQ/CR
Tracking Automatic Adjustment for Gain/Balance
-CON TZC DFCT FZC SENS 24 LPF HPF 23 LPF
+ -
100k 42 TEO
150k 43
BUFFER AMP
Balance OK Gain OK
0.01
0.01
LPFI C. OUT Frequency check
Balance
Gain Resistance switching
The CXA1782 has balance control, gain control, and comparator circuits required to perform tracking automatic adjustment. LPF is set externally at approximately 100Hz.
* Balance adjustment This adjustment is performed by routing the tracking error signal (TE signal) through the LPF, extracting the offset DC, and comparing it to the reference level. However, the TE signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through the LPF leaves lower frequency components, and the complete DC offset can not be extracted. To extract it, monitor the TE signal frequency at all times, and perform adjustment only when, a frequency that can lower a sufficient gain appears on the LPF. Use the C. OUT output to check this frequency. * Gain adjustment This adjustment is performed by passing the TE signal through the HPF and comparing the AC component to the reference level. The HPF signal is implemented by taking the difference between the TE signal and the LPF component input to Pin 43. The comparison signal is output from Pin 24 (SENS). Address 3 selects the automatic adjustment comparator output, and HPF for data (D3) = 1 or LPF for data (D3) = 0 is selected. * The anti-shock circuit always operates in the CXA1782 so that TG1 and TG2 (address 1 : D3) should be set to 1 for tracking adjustment to prevent this effect. When the anti-shock function is not used, Pin 45 (ATSC) should be fixed to VC.
- 16 -
CXA1782CQ/CR
Center Voltage Generation Circuit (Single voltage application; Connect to GND when it's positive/negative dual power supplies.) Maximum current is approximately 3mA. Output impedance is approximately 50.
Vcc
30k
VC VC 48
50
APC Circuit When the laser diode is driven with constant current, the optical output possesses large negative temperature characteristics. Therefore, the current must be controlled with the monitor photo diode to ensure the output remains constant.
Vcc
30k
VEE
100/6.3V
LD 33 1k Vcc 56k 34 10k 55k 56k 10k VREF 1.25V VEE VEE
10H
PD
1/6.3V
10k
LD
PD
VEE
GND
- 17 -
CXA1782CQ/CR
Focus Servo
FE 9k 51k FEO 10k 22k 2200p 3 0.47 1 2 FEI 100k FDFCT FGD 4 680k 40k 0.1 ISET 120k 17 50k FS2 FLB 5 0.1 FSET 11 510k 0.01 SRCH 8 4.7 FS1 11 22 50k FE_M 7 100k DFCT FS4 68k Focus 100k phase Compensation FE_O 6 FZC
FOCUS COIL
The above figure shows a block diagram of the focus servo. Ordinarily the FE signal is input to the focus phase compensation circuit through a 68k resistance; however, when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal 100k resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used, leave Pin 3 open. The defect switch operation can be enabled and disabled with command. The capacitor connected between Pin 5 and GND is a time constant to raise the low frequency in the normal playback state. The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510 is connected to Pin 11. The focus search height is approximately 1.1Vp-p when using the constants indicated in the above figure. This height is inversely proportional to the resistance connected between Pin 17 and VEE. However, changing this resistance also changes the height of the track jump and sled kick as well. The FZC comparator inverted input is set to 15% of VCC and VC (Pin 48); (VCC - VC) x 15%. 510k resistance is recommended for Pin 11.
- 18 -
CXA1782CQ/CR
Tracking Sled Servo
TE 42 TEO
+ -
HPF 130mV
100k
150k
BUFFER AMP 43
0.01
0.01
LPFI 17mV
LPF
SL_O 16 TEI 44 100k TDFCT 47 100k 680k 66p TM6 TM5 ATSC 45 1k 1k ATSC 22A 15 DFCT TM1 680k TG1 SL_M
SLED MOTOR
M
0.015
3.3 22 15k
0.47
TM2 22A 14
SL_P
0.047 470k
330k
47p
0.022 46
TZC TZC 9 TGU TG2 TG2 470k
100k
TM4 11A TM3 11A 90k
82k TA_M 12 100k
20k
0.033 10
Tracking Phase Compensation
10k TM7
TA_O
13
FSET 11 510k 0.01
The above figure shows a block diagram of the tracking and sled servo. The capacitor connected between Pins 9 and 10 is a time constant to decrease the high-frequency gain when TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510k resistance connected to Pin 11. In the CXA1782, TG1 and TG2 are inter-linked switches. To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be more specific, Track jump peak voltage = TM3 (or TM4) current x feedback resistance value The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15; Sled kick peak voltage = TM5 ( or TM6) current x feedback resistance The values of the current for each switch are determined by the resistance connected between Pin 17 and VEE. When this resistance is 120k: TM3 ( or TM4) = 11A, and TM5 (or TM6) = 22A. As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the internal resistance (100k) and the capacitance connected to Pin 47. - 19 -
120k
8.2k
TRACKING COIL
CXA1782CQ/CR
Focus OK Circuit
RF VCC
RF_O 31 C5 0.01 RF_I
x1
20k 54k 25 FOK
30 15k
VG 92k 0.625V
FOCUS OK AMP
FOCUS OK COMPARATOR
The focus OK circuit creates the timing window okaying the focus servo from the focus search state. The HPF output is obtained at Pin 30 from Pin 31 (RF signal), and the LPF output (opposite phase) of the focus OK amplifier output is also obtained. The focus OK output reverses when VRFI - VRFO -0.37V. Note that, C5 determines the time constant of the HPF for the EFM comparator and mirror circuit and the LPF of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01F selected, the fc is equal to 1kHz, and block error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented. DEFECT Circuit After the RFI signal is reverted, two time constants, long and short, are held at bottom. The short time constant bottom hold responds to 0.1ms or greater disc mirror defects, and the long time constant bottom hold holds the pre-defect mirror level. By differentiating and level-shifting these constants with capacitor coupling and comparing both signals, the mirror defect detection signal is generated.
0.033 CC1 27 CC2 26
RF_O 31
a
x2
b
c d
e 24 SENS
DEFECT AMP
DEFECT SW 28 0.01 DEFECT BOTTOM HOLD DEFECT COMPARATOR
CB
a
RFO
b
DEFECT AMP
BOTTOM c HOLD (1) ; solid Line: CC1 e H DEFECT L
d
BOTTOM HOLD (2) ; dotted Line: CC2
- 20 -
CXA1782CQ/CR
Mirror Circuit The mirror circuit performs peak and bottom hold after the RFI signal has been amplified. The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation.
RF_O
31
RF
MIRROR HOLD AMP 0.033 29 PEAK& BOTTOM HOLD H
x1
RF_I
30
CP J K
x 1.4
G MIRROR AMP
I
20k MIRROR COMPARATOR
LOGIC
RF_O 0V G (RF_I)
0V
H (PEAK HOLD)
0V
I (BOTTOM HOLD) J K (MIRROR HOLD)
0V
MIRR
H L
The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time constant must be sufficiently large compared with the traverse signal. In the CXA1782, this mirror output is used only during braking operations, and no external output pin is attached. Accordingly, when connecting DSP such as the CXD2500 with MIRR input pin, input the C. OUT output to the MIRR input of the DSP. - 21 -
CXA1782CQ/CR
Commands The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F. Commands for the CXA1782 can be broadly divided into four groups ranging in value from $0X to $3X. 1. $0X ("FZC" at SENS pin (Pin 24)) These commands are related to focus servo control. The bit configuration is as shown below. D7 0 D6 0 D5 0 D4 0 D3 FS4 D2 DEFECT D1 FS2 D0 FS1
Four focus-servo related switches exist: FS1, FS2, FS4, and DEFECT corresponding to D0 to D3, respectively. $00 $02 When FS1 = 0, Pin 8 is charged to (22A - 11A) x 50k = 0.55V. If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V. From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output to Pin 6. This voltage level is obtained by equation 1 below. (22A - 11A) x 50k x $03 resistance between Pins 6 and 7 50k .... Equation 1
From the state described above, FS1 becomes 1, and a current source of +22A is split off. Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as shown in Fig. 1 below.
0V
Fig. 1. Voltage at Pin 8 when FS1 gose from 0 1
This time constant is obtained with the 50k resistance and an external capacitor. By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
0V
$
00 02
03
02
03
02
00
Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6) $04 When the fact that the RF signal is missing is detected and the scratches on the disc are detected with DEFECT = 0, DFCT (FS3) is turned ON. - 22 -
CXA1782CQ/CR
1-1. FS4 This switch is provided between the focus error input (Pin 2) and the focus phase compensation, and is in charge of turning the focus servo ON and OFF. $00 $08 Focus OFF Focus ON 1-2. Procedure of focus activation For description, suppose that the polarity is as described below. a) The lens is searching the disc from far to near; b) The output voltage (Pin 6) is changing from negative to positive; and c) The focus S-curve is varying as shown below.
A t
Fig. 3. S-curve The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig. 3. To prevent misoperation, this signal is ANDed with the focus OK signal. In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 24) as the point A transit signal. In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case). Following the line of the above description, focusing can be well obtained by observing the following timing chart.
(20ms) (200ms) $02 ($00) $03 $08
Drive voltage
The broken lines in the figure
Focus error
indicate the voltage assuming the signal is not in focus.
SENS pin (FZC) The instant the signal is brought into focus.
Focus OK
Fig. 4. Focus ON timing chart - 23 -
CXA1782CQ/CR
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ? YES
NO
Transfer $08
F. OK ? YES Transfer $08
F. OK ? NO YES FZC ? YES NO
NO
Latch
Latch
(A)
(B)
Fig. 5. Poor and good software command sequences 1-3. SENS pin (Pin 24) The output of the SENS pin differs depending on the input data as shown below. $0X: FZC $1X: DEFECT $2X: TZC $3X: Automatic adjustment comparator output $4X to 7X: HIGH-Z
2. $1X ("DEFECT" at SENS pin (Pin 24)) These commands deal with switching TG1/TG2, brake circuit ON/OFF, and the sled kick output. The bit configuration is as follows Sled kick height Relative D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 value (PS1) (PS0) 0 0 0 1 TG1, TG2 Break Sled kick 1 0 0 circuit height 2 0 1 ON/OFF ON/OFF 3 1 0 4 1 1 TG1, TG2 The purpose of these switches is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked switches. The brake circuit (TM7) is to prevent the occurrence of such frequently occurring phenomena as extremely degraded actuator settling due to the servo motor exceeding the linear range causing what should be a 100-track jump to fall back down to a 10-track jump after a 100 or 10-track jump has been performed. To do this, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the tracking error is 180out-of-phase to cut the unneeded portion of the tracking error and apply braking. - 24 -
CXA1782CQ/CR
[A] RF_I 30 Tracking error (TZC) 46
Envelope Detection
[B]
Waveform Shaping
D2 (MIRR) [C] [F] (Latch) [G] BRK TM7 Low: open High: make
DQ CK
[D]
Waveform Shaping
[E]
Edge Detection
CXA1782
Fig. 6. TMI movement during braking operation
From inner to outer track [A] [B] [C] [D]
From outer to inner track
("MIRR")
("TZC") [E] [F] [G] [H] Braking is applied from here.
0V
Fig. 7. Internal waveform
3. $2X ("TZC" at SENS pin (Pin 24)) These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse and fast forward pulse during access operations. D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 Tracking control 00: OFF 01: Servo ON 10: F-JUMP 11: R-JUMP TM1, TM3, TM4 Sled control 00: OFF 01: Servo ON 10: F-FAST FORWARD 11: R-FAST FORWARD TM2, TM5, TM6
- 25 -
CXA1782CQ/CR
4. $3X These commands control the balance and gain control circuit switches used during automatic tracking adjustment. In the initial resetting state, BAL1 to BAL3 switches are OFF and TOG1 to TOG3 switches are ON.
* Balance adjustment The balance adjustment switches BAL1 to BAL3 can be controlled by setting D3 = 0. The switches are set using D0 to D2. At this time, the balance adjustment LPF comparator output is selected at the SENS pin. Data is set by specifying switch conditions D0 to D2 and sending a latch pulse with D3 = 0. Sending a latch pulse with D3 = 1 does not change the balance switch settings.
START
BAL1 to BAL3 Switch Control
C. OUT Is the frequency high enough ? YES SENS output Balance OK ?
NO
Adjustment Completed
Balance adjustment * Gain adjustment The gain adjustment switches TOG1 to TOG3 can be controlled by setting D3 = 1. These switches are set using D0 to D2. At this time, the balance adjustment HPF comparator output is selected for SENS pin. In a fashion similar to the method used with the balance adjustment, set the data by sending a latch pulse with D3 = 1, specifying the switch conditions D0 to D2.
START
TOG1 to TOG3 Switch control SENS GAIN OK ? YES Adjustment Completed
NO
Gain adjustment - 26 -
CXA1782CQ/CR
CPU Serial Interface Timing Chart
DATA D0 tWCK CLK 1/fck tD XLT tWL tCD D1 D2 tWCK D3 tSU D4 th D5 D6 D7 D0
(VCC = 3.0V) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width Data transfer interval Symbol fck fwck 500 500 500 500 1000 1000 Min. Type. Max. 1 Unit MHz ns ns ns ns ns ns
tsu th tD tWL tCD
System Control ADRESS Item D7 D6 D5 D4 0 0 0 D3 D2 DATA D1 D0 SENS output
Focus Control
FS4 FS1 DEFECT (FS3) FS2 0 Focus Search Disable = 1 Search ON = 1, OFF = 0 Enable = 0 ON = 1, OFF = 0 Up = 1, Down = 0 TG1, TG2 Brake Sled ON = 1, OFF = 0 ON = 1, OFF = 0 Kick + 2 0 Tracking Mode 1 Sled Mode 2 1 1 Automatic tracking adjustment mode Sled Kick + 1
FZC DEFECT TZC Gain/Bal
Tracking Control 0 Tracking Mode 0 Select 0
0 0 0
0 1 1
1 TRACKING MODE D3 OFF ON FWD JUMP REV JUMP 0 0 1 1 D2 0 1 0 1
2 SLED MODE D1 OFF ON FWD MOVE REV MOVE 0 0 1 1 D0 0 1 0 1
- 27 -
CXA1782CQ/CR
Serial Data Truth Table Serial Data FOCUS CONTROL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F Hex FS4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Functions FS = 4321 DEFECT FS2 E E E E D D D D E E E E D D D D 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DEFECT E: enable D: disable
TRACKING MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Hex $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F
TM = 6 5 4 3 2 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
- 28 -
CXA1782CQ/CR
Automatic adjustment mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
TOG SW Hex $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F 321 - - - - - - - - 1 1 1 1 0 0 0 0 - - - - - - - - 1 1 0 0 1 1 0 0 - - - - - - - - 1 0 1 0 1 0 1 0
BAL SW 321 1 1 1 1 0 0 0 0 - - - - - - - - 1 1 0 0 1 1 0 0 - - - - - - - - 1 0 1 0 1 0 1 0 - - - - - - - - DATA D3 = 0: Balance switch setting DATA D3 = 1: Gain switch setting
Note) 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values of each bit for serial data.
Initial State (resetting state) ADDRESS Item Focus Control Tracking Control Tracking Mode Select DATA HEXADECIMAL 0 0 0 1 0 $00 $10 $20 $37 $38
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0
The above data means the following operation modes. Focus Control Tracking Control Tracking Mode Select Focus off, Defect enable, Focus Search off, Focus Search down TG1 - TG2 off, Brake off, Sled Kick + 2 off, Sled Kick + 1 off Tracking off, Sled off Tracking gain min. (TOG SW: 1 1 1) Tracking balance: RE3 max. (TBAL SW: 0 0 0)
- 29 -
CXA1782CQ/CR
Notes on Operation 1. FSET pin The FSET pin determines the fc for the focus and tracking high-frequency phase compensation. 2. ISET pin ISET current = 1.27V/R = Focus search current = Tracking jump current 1 = Sled kick current ($1X: PS1 = PS0 = 0) x 2 Use the setting resistance within the range of 120k to 240k. If the resistance value is out of this range, the oscillation may be occurred in the ISET block. 3. FE (focus error)/TE (tracking error) gain changing method 1) High gain: Resistance between FE pins (pins 6 and 7) 100k Large Resistance between TE pins (pins 12 and 13) 100k Large 2) Low gain: A signal, whose resistance is divided between Pins 1 and 2, is input to FE. The internal gain adjustment circuit is used for TE. 4. Input voltage at Pins 19 to 22 of the microcomputer interface should be as follows: VIH VCC x 90% or more VIL VCC x 10% or less 5. Focus OK circuit 1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the mirror amplifier HPF.
VCC 20k FOK 40k 100k VCC VEE VEE 25 RL
The FOK and comparator output are as follows: Output voltage High: VFOKH near VCC Output voltage Low: VFOKL Vsat (NPN)
6. Sled amplifier The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB. Sled/Tracking internal phase compensation and reference design material Item FCS 1.2kHz gain 1.2kHz phase 1.2kHz gain TRK 1.2kHz phase 2.7kHz gain 2.7kHz phase 08 08 25 25 2513 2513 13 CTGU = 0.1F SD Measurement pin 6 Conditions CFLB = 0.1F CFGD = 0.1F Typ. 21.5 63 13 -125 26.5 -130 Unit dB deg dB deg dB deg
- 30 -
CXA1782CQ/CR
Package Outline CXA1782CQ
Unit: mm
48PIN QFP (PLASTIC)
15.3 0.4 + 0.4 12.0 - 0.1 + 0.1 0.15 - 0.05
36
25
0.15
37
24
48
13
+ 0.2 0.1 - 0.1
1 + 0.15 0.3 - 0.1
12 0.9 0.2 + 0.35 2.2 - 0.15
EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g
0.8
0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
CXA1782CR
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24
(8.0)
A 48 1 0.5 0.08 + 0.08 0.18 - 0.03 0.1 0.1 + 0.2 1.5 - 0.1 12 13
(0.22)
+ 0.05 0.127 - 0.02 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 QFP048-P-0707-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY
0.2g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 31 -
0.5 0.2
13.5

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