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IMP1 232LP/LPS
POWER MANAGEMENT
5V P Power Supply Monitor and Reset Circuit
- Selectable Trip -Point Tolerance and Watchdog Period - Push-Button Reset
Key Features
x Pin compatible with the Dallas Semiconductor DS1232LP/1232LPS -- 40% lower supply current x 5V supply monitor x Selectable watchdog period x Debounce manual push-button reset input x Precision temperature-compensated voltage reference and comparator x Power-up, power-down and brownout detection x 250ms reset time x Active LOW open-drain reset and active HIGH push-pull output x Selectable trip point tolerance: 5% or 10% x Low-cost, surface mount packages: 8/16-pin SO, 8-pin DIP and 8-pin MicroSO x Wide operating temperature - 40C to +85C (N/EPA suffixed devices)
The IMP1232LP/LPS microprocessor supervisor can halt and restart a "hung-up" or "stalled" microprocessor, restart a microprocessor after a power failure, and debounce and interface a manual push-button microprocessor reset switch. The low-power supervisors feature 40% lower supply current than the pin compatible Dallas Semiconductor DS1232LP/LPS. Precision temperature compensated reference and comparator circuits monitor the 5V, VCC input voltage. During power-up or when the VCC power supply falls outside selectable tolerance limits, both the RESET and RESET become active. When VCC rises above the threshold voltage, the reset signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to stabilize. The trip point tolerance signal, TOL, selects the trip level tolerance to be either 5- or 10-percent.
Each device has both a push-pull, active HIGH reset output and an open drain, active LOW reset output. 150ms, 610ms and 1,200ms. If the ST input is not strobed A debounced manual reset input activates the reset outputs for a mini- LOW before the time-out period expires, a reset is issued. mum period of 250ms. Devices are available in 8-pin DIP, 8/16-pin SO and comAlso included is a watchdog timer to stop and restart a microprocessor pact 8-pin MicroSO packages. that is "hung-up". Three watchdog time-out periods are selectable:
Block Diagram
VCC TOL 8 (15)
IMP1232LP/LPS
3 (6) 5%/10% Tolerance Selection (16-Pin Package)
6 (11)
RESET
+
5 (9) VCC Reference
-
RESET
40k PBRST 1 (2) Push Button Debounce Watchdog Timebase Selection Watchdog Transition Detector 4 (8)
1232_03.eps
TD
2 (4)
Reset & Watchdog Timer
ST
7 (13)
GND
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
1
IMP1 232LP/LPS
Pin Configuration
DIP/SO/MicroSO
NC 1 PBRST 1 TD 2 8 VCC IMP1232LP 7 ST IMP1232LPS-2 TOL 3 IMP1232LPCMA 6 RESET IMP1232LPEMA 5 RESET GND 4
1232_01.eps
SO
16 NC 15 VCC IMP1232LPSN 14 NC 13 ST 12 NC 11 RESET 10 NC 9 RESET
1232_02.eps
PBRST 2 NC 3 TD 4 NC 5 TOL 6 NC 7 GND 8
Pin Descriptions
Pin Number 8-Pin Pac k ag e
1 2 3 4 5
Pin Number 16-Pin Pac k ag e
2 4 6 8 9
N ame
PBRST TD TOL GND RESET
F unction
Debounced manual pushbutton RESET input Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms for TD = Open, and tTD =1200ms for TD = VCC) Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC) trip point tolerance Ground Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. Active LOW reset output. (See RESET) Strobe Input 5V power No internal connection
6 7 8 --
11 13 15 1, 3, 5, 7, 10, 12, 14, 16
RESET ST VCC NC
Ordering Information
Part Number
IMP1232LP IMP1232LPS IMP1232LPS-2 IMP1232LPCMA IMP1232LPEMA IMP1232LPN IMP1232LPSN-2 IMP1232LPSN
Package
8-DIP 16-SO 8-SO 8-MicroSO 8-MicroSO 8-DIP 8-SO 16-SO
Operating Temperature Range
0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
Maximum Supply Current (A)
30 30 30 30 30 30 30 30
Voltage Monitoring Application
5V 5V 5V 5V 5V 5V 5V 5V
1232_t01.eps
2
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(c) 1999 IMP, Inc.
IMP1 232LP/LPS
Absolute Maximum Ratings
Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Voltage on ST, TD . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V Voltage on PBRST, RESET, RESET . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature Range . . . . . . . . . . . -40C to 85C (N/EMA version) 0C to 70C Voltages measured with respect to ground. These are stress ratings only and functional operation is not implied. Soldering Temperature . . . . . . . . . . . . . . . . . . 260C for 10 seconds Storage Temperature . . . . . . . . . . . . . . . . . . . -55C to 125C
Electrical Characteristics
Unless otherwise stated, 4.5V VCC 5.5V and over the operating temperature range of 0C to +70C (-40C to +85C for N/EMA devices). All voltages are referenced to ground.
Parameter
Supply Voltage (VCC) ST and PBRST Input High Level ST and PBRST Input Low Level VCC Trip Point (TOL = GND) VCC Trip Point (TOL = VCC) Watchdog Time-Out Period Watchdog Time-Out Period Watchdog Time-Out Period Output Voltage Output Current Output Current Input Leakage RESET Low Level Internal Pull-Up Resistor Operating Current (CMOS) Input Capacitance Output Capacitance PBRST Manual Reset Minimum Low Time Reset Active Time ST Pulse Width VCC Fail Detect to RESET or RESET VCC Slew Rate PBRST Stable LOW to RESET and RESET Active VCC Detect to RESET or RESET Inactive VCC Slew Rate
Symbol
VCC VIH VIL VCCTP VCCTP tTD tTD tTD VOH IOH IOL IIL VOL
Conditions
Min
4.5 2 - 0.3 4.50 4.25
Typ
Max
5.5 VCC + 0.3V 0.8
Units
V V V V V ms ms ms V mA mA
4.62 4.37 150 1200 610 VCC - 0.1V -10
4.74 4.49 250 2000 1000
TD = GND TD = VCC TD floating I = -500A, Note 3 Output = 2.4V , Note 2 Output = 0.4V, Note 1 Note 1
62.5 500 250 VCC - 0.5V -8 10 -1.0
1.0 0.4 40 30 5 10
A V k A pF pF ms
ICC1 CIN COUT tPB tRST tST tRPD tF tPDLY tRPU tR tRISE = 5s 4.25V to 4.75V 250 0 610 4.75V to 4.25V 300 Note 4 PBRST = VIL 20 250 20 5 610
1000 8
ms ns s s
20 1000
ms ms ns
Notes: 1. PBRST is internally pulled HIGH to VCC through a nominal 40k resistor. 2. RESET is an open drain output. 3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC falls below 2.0V. 4. Must not exceed the minimum watchdog time-out period (tTD). The watchdog circuit cannot be disabled. To avoid a reset, ST must be strobed.
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
3
IMP1 232LP/LPS
Application Information
Supply Voltage Monitor
Reset Signal Polarity and Output Stage Structure RESET is an active LOW signal. It is developed with an open drain driver. If a pullup resistor is required, typical values are 10k to 50k. RESET is an active High signal developed by a CMOS push-pull output stage and is the logical opposite to RESET. Trip Point Tolerance Selection With TOL connected to VCC, RESET and RESET become active whenever VCC falls below 4.5V. RESET and RESET become active when VCC falls below 4.75V if TOL is connected to ground. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. On power-down, once VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or less until VCC drops below 1.2V. The active HIGH reset signal is valid down to a VCC level of 1.2V also.
tR 4.75V VCCTP PBRST tPB tPDLY VIL VCC tRST tRPU RESET VOH RESET RESET VOH VOL
1232_08.eps
Tolerance Select
TOL = VCC TOL = GND
TRIP Point Voltage (V) Tolerance
10% 5%
Min
4.25 4.5
Nominal
4.37 4.62
Max
4.49 4.74
1232_t02.eps
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset signals. The pushbutton input is debounced and is normally pulled HIGH through an internal 40k resistor. When PBRST is held LOW for the minimum time tPB , both resets become active and remain active for approximately a minimum time period of 250ms after PBRST returns HIGH. The debounced input is guaranteed to recognize pulses greater than 20ms. No external pull-up resistor is required, since PBRST is pulled HIGH by an internal 40k resistor. The PBRST can be driven from a TTL or CMOS logic line or shorted to ground with a mechanical switch.
4.25V
VIH
VOL
Figure 3. Timing Diagram: Pushbutton Reset
RESET
1232_05.eps
Figure 1. Timing Diagram: Power Up
1 tF VCC 4.75V VCCTP 2 4.25V 3 4
5V IMP1232LP/LPS PBRST TD TOL GND VCC ST RESET RESET 8 7 6 5 P
RESET
1232_06.eps
RESET
tRPD
Figure 4. Application Circuit: Pushbutton Reset
RESET
VOH VOL
1232_04.eps
Figure 2. Timing Diagram: Power Down
4
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(c) 1999 IMP, Inc.
IMP1 232LP/LPS
Application Information
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is "hung-up". Through the time delay input, TD, three watchdog time-out periods are selectable: 150ms, 610ms and 1,200ms. If the strobe input, ST, is not strobed LOW prior to timeout, reset signals become active. On power-up or after the supply voltage returns to an in-tolerance condition, the reset signal remains active for 250ms minimum, allowing the power supply and system microprocessor to stabilize. ST Pulses as short as 20ns can be detected.
Valid Strobe Valid Strobe Invalid Strobe
A HIGH-to-LOW ST signal transition must be regularly issued no later than the minimum time-out period defined by the state of the TD signal. This guarantees the watchdog timer does not time-out. Timeouts periods of approximately 150ms, 610ms or 1,200ms are selected through the TD pin.
TD Voltage Level
GND Floating VCC
Watchdog Time-Out Period (ms) Min
62.5 250 500
Nominal
150 610 1200
Max
250 1000 2000
1232_t03.eps
ST
tST tRST RESET tTD (Min) tTD (Max)
1232_09.eps
The watchdog timer cannot be disabled. It must be strobed with a high-to-low transition to avoid a watchdog timeout.
Note: ST is ignored whenever a reset is active.
Figure 5. Timing Diagram: Strobe Input
5V IMP1232LP/LPS 1 2 3 4 PBRST TD TOL GND VCC ST RESET RESET 8 7 6 5
1232_07.eps
MREQ 10k P RESET
Address Bus
Decoder
Figure 6. Application Circuit: Watchdog Timer
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
5
IMP1 232LP/LPS
Package Dimensions
MicroSO (8-Pin)
a
Inches Min
A A1 A2 b C D e E E1 L a A A1 B C e E H L D
Millimeters Max Min Max MicroSO (8-Pin)*
E1 E
L D A2 A e b A1
0.10mm 0.004in
C
----- 0.0433 0.0020 0.0059 0.0295 0.0374 0.0098 0.0157 0.0051 0.0091 0.1142 0.1220 0.0256 BSC 0.193 BSC 0.1142 0.1220 0.0157 0.0276 0 6 0.053 0.004 0.013 0.007 0.050 0.150 0.228 0.016 0.189 0.157 0.244 0.050 0.197 0.069 0.010 0.020 0.010
---- 1.10 0.050 0.15 0.75 0.95 0.25 0.40 0.13 0.23 2.90 3.10 0.65 BSC 4.90 BSC 2.90 3.10 0.40 0.70 0 6 1.35 0.10 0.33 0.19 1.27 3.80 5.80 0.40 4.80 ---- 0.38 2.92 0.36 1.14 0.80 9.02 0.13 7.62 6.10 2.54 7.62 ----- 2.92 10.92 3.81
1232_t04.at3
D
+
MicroSO (8-Pin).eps
SO (8-Pin)**
1.75 0.25 0.51 0.25 4.00 6.20 1.27 2.00 5.33 ----- 4.95 0.56 1.78 1.14 10.16 ----- 8.26 7.11
SO (8-Pin)
0- 8
L
E
H
Plastic DIP (8-Pin)***
A ----- 0.210 A1 0.015 ----- A2 0.115 0.195 b 0.014 0.022 b2 0.045 0.070 b3 0.030 0.045 D 0.355 0.400 D1 0.005 ----- E 0.300 0.325 E1 0.240 0.280 e 0.100 ----- eA 0.300 ----- eB ----- 0.430 eC ----- 0.060 L 0.115 0.150 *** JEDEC Drawing MO-187AA *** JEDEC Drawing MS-112AA *** JEDEC Drawing MS-001BA
C D A
e B A1
SO (8-Pin).eps
Plastic DIP (8-Pin)
D1
E D A A2 E1
L A1 e b b2
0-15 C eA eB
Plastic DIP (8-Pin)a.eps
6
408-432-9100/www.impweb.com
(c) 1999 IMP, Inc.
IMP1 232LP/LPS
Package Dimensions
SO (16-Pin)
Inches Min Max SO (16-Pin)*
E H
Millimeters Min Max
D 0- 8 A C e B A1 L
SO (14-Pin).eps
A 0.926 0.1043 A1 0.0040 0.0118 B 0.013 0.020 C 0.0091 0.0125 D 0.3977 0.4133 E 0.2914 0.2662 e 0.050 BSC H 0.394 0.419 L 0.016 0.050 * JEDEC Drawing MS-013AA
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 BSC 10.00 10.65 0.40 1.27
2524/26_t03.at3
IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners.
(c) 1999 IMP, Inc. Printed in USA Publication #: 1011 Revision: B Issue Date: 11/08/99 Type: Preliminary

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