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LIN D O C #: 1840
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
T
HE
I
NFINITE
P
OWER
OF
I
N N O VAT I O N
P
RODUCTION
D
ATA
S
HEET
DESCRIPTION The UC184xA family of control ICs provides all the necessary features to implement off-line fixed-frequency, current-mode switching power supplies with a minimum of external components. The current mode architecture demonstrates improved load regulation, pulse-by-pulse current limiting and inherent protection of the power supply output switch. The IC includes: A bandgap reference trimmed to 1% accuracy, an error amplifier, a current sense comparator with internal clamp to 1V, a high current totem pole output stage for fast switching of power MOSFET's, and an externally programmable oscillator to set frequency and maximum duty cycle. The undervoltage lock-out is designed to operate with 250A typ. start-up current, allowing an efficient bootstrap supply voltage design. Available options for this family of products, such as start-up voltage hysteresis and duty cycle, are summarized below in the Available Options section. The UC184xA family of control ICs is also available in 14-pin SOIC package which makes the Power Output Stage Collector and Ground pins available.
K E Y F E AT U R E S
s LOW START-UP CURRENT. (0.5mA max.) s TRIMMED OSCILLATOR DISCHARGE CURRENT. (See Product Highlight) p OPTIMIZED FOR OFF-LINE AND DC-TO-DC CONVERTERS. p AUTOMATIC FEED FORWARD COMPENSATION. p PULSE-BY-PULSE CURRENT LIMITING. p ENHANCED LOAD RESPONSE CHARACTERISTICS. p UNDER-VOLTAGE LOCKOUT WITH HYSTERESIS. p DOUBLE PULSE SUPPRESSION. p HIGH-CURRENT TOTEM POLE OUTPUT. p INTERNALLY TRIMMED BANDGAP REFERENCE. p 500KHz OPERATION. p LOW RO ERROR AMPLIFIER.
PRODUCT HIGHLIGHT
COMPARISON
OF
UC384XA
VS.
SG384X DISCHARGE CURRENT
A P P L I C AT I O N S SG384x
Max. Limit
UC384xA
SG384x
Min. Limit
TA=25C
s ECONOMICAL OFF-LINE FLYBACK OR FORWARD CONVERTERS. s DC-DC BUCK OR BOOST CONVERTERS. s LOW COST DC MOTOR CONTROL.
A
VAILABLE
O
PTIONS
Part # UCx842A UCx843A
7.5 7.8 8.3 Mean 8.8 9.3
Start-Up Hysteresis Max. Duty Voltage Cycle 16V 8.4V 16V 8.4V 6V 0.8V 6V 0.8V <100% <100% <50% <50%
-3
+3
UCx844A UCx845A
Discharge Current Distribution - mA
PA C K A G E O R D E R I N F O R M AT I O N TA (C) 0 to 70 -40 to 85 -55 to 125
M
Plastic DIP 8-pin
UC384xAM UC284xAM --
DM Plastic SOIC 8-pin
UC384xADM UC284xADM --
D Plastic SOIC 14-pin
UC384xAD UC284xAD --
Y Ceramic DIP 8-pin
-- UC284xAY UC184xAY
Note: All surface-mount packages are available in Tape & Reel. Append the letter "T" to part number. (i.e. UC3842ADMT)
F O R F U R T H E R I N F O R M AT I O N C A L L ( 7 1 4 ) 8 9 8 - 8 1 2 1
Copyright (c) 1995 Rev. 1.2 12/95
11861 WESTERN AVENUE, GARDEN GROVE, CA. 92841
1
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
A B S O L U T E M A X I M U M R AT I N G S
(Note 1)
PACKAGE PIN OUTS
COMP VFB ISENSE RT/CT
1 2 3 4 8 7 6 5
Supply Voltage (Low Impedance Source) (VCC) ......................................................... 30V Supply Voltage (ICC < 30mA) .......................................................................... Self Limiting Output Current ............................................................................................................. 1A Output Energy (Capacitive Load) ................................................................................. 5J Analog Inputs (VFB & ISENSE) ........................................................................ -0.3V to +6.3V Error Amp Output Sink Current ............................................................................... 10mA Power Dissipation at TA = 25C (M Package) .............................................................. 1W Storage Temperature Range .................................................................... -65C to +150C Lead Temperature (Soldering, 10 Seconds) ............................................................. 300C
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Pin numbers refer to DIL packages only.
VREF VCC OUTPUT GND
M & Y PACKAGE (Top View)
COMP VFB ISENSE RT/CT
1 2 3 4
8 7 6 5
VREF VCC OUTPUT GND
T H E R MAL DATA
M PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA DM PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA D PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA Y PACKAGE: THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA 130C/W 120C/W 165C/W 95C/W
COMP N.C. VFB N.C. ISENSE N.C. RT/CT
DM PACKAGE (Top View)
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VREF N.C. VCC VC OUTPUT GND PWR GND
D PACKAGE (Top View)
Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow
2
Copyright (c) 1995 Rev. 1.2 12/95
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for UC384xA with 0C TA 70C, UC284xA with -40C TA 85C, UC184xA with -55C TA 125C; VCC=15V; RT=10K; C T=3.3nF. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter Reference Section
Output Voltage Line Regulation Load Regulation Temperature Stability (Note 2 & 7) Total Output Variation Output Noise Voltage (Note 2) Long Term Stability (Note 2) Output Short Circuit Current
Symbol
Test Conditions
UC184xA/284xA UC384xA Units Min. Typ. Max. Min. Typ. Max.
4.95 5.00 5.05 4.90 5.00 5.10 6 20 6 20 6 25 6 25 0.2 0.4 0.2 0.4 4.9 5.1 4.82 5.18 50 50 5 25 5 25 -30 -100 -180 -30 -100 -180 47 52 0.2 5 1.7 8.3 57 1 47 52 0.2 5 1.7 8.3 57 1 V mV mV mV/C V V mV mA kHz % % V mA mA V A dB MHz dB mA mA V V V/V V dB A ns V V V V ns ns V
VREF
TJ = 25C, IL = 1mA 12 VIN 25V 1 IO 20mA Over Line, Load, and Temperature 10Hz f 10kHz, TJ = 25C TA = 125C, t = 1000hrs
VN ISC
Oscillator Section
Initial Accuracy (Note 6) Voltage Stability Temperature Stability (Note 2) Amplitude (Note 2) Discharge Current TJ = 25C 12 VCC 25V TMIN TA TMAX TJ = 25C, VPIN 4 = 2V VPIN 4 = 2V, TMIN TA TMAX VPIN 1 = 2.5V IB AVOL UGBW PSRR IOL I OH VOH VOL AVOL PSRR IB Tpd VPIN 1 = 5V 12 VCC 25V VPIN 3 = 0 to 2V ISINK = 20mA ISINK = 200mA ISOURCE = 20mA ISOURCE = 200mA TJ = 25C, CL = 1nF TJ = 25C, CL = 1nF VCC = 5V, ISINK = 10mA 2 V O 4V Tj = 25C 12 VCC 25V VPIN 2 = 2.7V, VPIN 1 = 1.1V VPIN 2 = 2.3V, VPIN 1 = 5V VPIN 2 = 2.3V, RL = 15K to ground VPIN 2 = 2.7V, RL = 15K to VREF
7.8 7.5
8.8 8.8
7.8 7.6
8.8 8.8
Error Amp Section
Input Voltage Input Bias Current Open Loop Gain Unity Gain Bandwidth (Note 2) Power Supply Rejection Ratio (Note 3) Output Sink Current Output Source Current Output Voltage High Level Output Voltage Low Level 2.45 2.50 2.55 2.42 2.50 2.58 -0.3 -1 -0.3 -2 65 90 65 90 0.7 1 0.7 1 60 70 60 70 2 6 2 6 -0.5 -0.8 -0.5 -0.8 5 6 5 6 0.7 1.1 0.7 1.1 2.85 0.9 3 1 70 -2 150 0.1 1.5 13.5 13.5 50 50 0.7 3.15 2.85 1.1 0.9 -10 300 0.4 2.2 13 12 150 150 1.2 3 1 70 -2 150 0.1 1.5 13.5 13.5 50 50 0.7 3.15 1.1 -10 300 0.4 2.2
Current Sense Section
Gain (Note 3 & 4) Maximum Input Signal (Note 3) Power Supply Rejection Ratio (Note 3) Input Bias Current Delay to Output (Note 2)
Output Section
Output Low Level Output High Level Rise Time (Note 2) Fall Time (Note 2) UVLO Saturation VOL VOH TR TF VSAT
13 12
150 150 1.2
( E l e c tr i c a l Cha r a ct er i st i cs cont i nu e next pa g e.)
Copyright (c) 1995 Rev. 1.2 12/95
3
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
ELECTRICAL CHARACTERISTICS Parameter Under-Voltage Lockout Section
Start Threshold Min. Operation Voltage After Turn-On x842A/4A x843A/5A x842A/4A x843A/5A x842A/3A x844A/5A
(Con't.)
Symbol
Test Conditions
UC184xA/284xA UC384xA Units Min. Typ. Max. Min. Typ. Max.
15 7.8 9 7.0 94 47 16 8.4 10 7.6 96 48 17 9.0 11 8.2 100 50 0 0.5 17 30 14.5 7.8 8.5 7.0 94 47 16 8.4 10 7.6 96 48 17.5 9.0 11.5 8.2 100 50 0 0.5 17 V V V V % % % mA mA V
PWM Section
Maximum Duty Cycle Minimum Duty Cycle
Total Standby Section
Start-Up Current Operating Supply Current Zener Voltage I CC VZ 0.3 11 35 0.3 11 35
ICC = 25mA
30
Notes: 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VVFB = 0. 4. Gain defined as: AVOL = V COMP ; 0 V ISENSE 0.8V. VISENSE
7. "Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation: VREF (max.) - VREF (min.) Temp Stability = T J (max.) - TJ (min.) V REF (max.) & V REF (min.) are the maximum & minimum reference voltage measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature."
5. Adjust VCC above the start threshold before setting at 15V. 6. Output frequency equals oscillator frequency for the UC1842A and UC1843A. Output frequency is one half oscillator frequency for the UC1844A and UC1845A.
BLOCK DIAGRAM
VCC *
34V
UVLO
Hysteresis 6V (1842A/4A) 0.8V (1843A/5A)
GROUND
**
UVLO 16V (1842A/4A) 8.4V (1843A/5A) 2.5V
S/R
5V Ref Internal Bias
VREF 5.0V 50mA
VREF Good Logic RT/CT Oscillator *** Error Amp VFB COMP CURRENT SENSE 2R R 1V S R Current Sense Comparator PWM Latch T
* VC
OUTPUT
** POWER GROUND
* - V CC and VC are internally connected for 8 pin packages. ** - POWER GROUND and GROUND are internally connected for 8 pin packages. *** - Toggle flip flop used only in x844A and x845A series.
4
Copyright (c) 1995 Rev. 1.2 12/95
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
CHARACTERISTIC CURVES
FIGURE 1. -- OSCILLATOR FREQUENCY vs. TIMING RESISTOR
VREF 8
Oscillator Frequency - (Hz)
1M
CT = 1nF
RT RT/CT 4 CT GROUND 5
CT = 2.2nF
100k
10k
CT = 4.7nF
For RT > 5k, f
0 300 1.0k 3.0k 10.0k 30.0k 100k
1.72 RT CT
Note: Output drive frequency is half the oscillator frequency for the UCx844A/5A devices.
RT - (ohms)
FIGURE 2. -- MAXIMUM DUTY CYCLE vs. TIMING RESISTOR
100.0
Maximum Duty Cycle - (%)
80.0
60.0
40.0
20.0
0 300 1.0k 3.0k 10.0k 30.0k 100k
RT - (ohms)
Copyright (c) 1995 Rev. 1.2 12/95
5
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
T Y P I C A L A P P L I C AT I O N C I R C U I T S
FIGURE 3. -- CURRENT SENSE SPIKE SUPPRESSION
VCC DC BUS
FIGURE 4. -- MOSFET PARASITIC OSCILLATIONS
VCC DC BUS
7 Q1
7 R1 Q1
UCx84xA
6 5
CHANGE
UCx84xA
IPK IPK(MAX) = 1.0V RS
6
RS 5
3 C RS
The RC low pass filter will eliminate the leading edge current spike caused by parasitics of Power MOSFET.
A resistor (R1) in series with the MOSFET gate will reduce overshoot & ringing caused by the MOSFET input capacitance and any inductance in series with the gate drive. (Note: It is very important to have a low inductance ground path to insure correct operation of the I.C. This can be done by making the ground paths as short and as wide as possible.)
FIGURE 5. -- EXTERNAL DUTY CYCLE CLAMP AND MULTI-UNIT SYNCHRONIZATION
8 RA 7 RB 6 555 TIMER 8 4
UCx84xA
3 4
2 5 0.01
1.44 (R A + 2RB)C RB RA + 2R B
1 5 To other UCx84xA devices
f= f=
Precision duty cycle limiting as well as synchronizing several parts is possible with the above circuitry.
6
Copyright (c) 1995 Rev. 1.2 12/95
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
T Y P I C A L A P P L I C AT I O N C I R C U I T S
FIGURE 6. -- SLOPE COMPENSATION
(continued)
VCC
DC BUS
UCx84xA
5V 8(14)
7(12) VO
UVLO S R 5V REF INTERNAL BIAS 2.5V VREF GOOD LOGIC
RT
2N222A
7(11)
RSLOPE From VO CT
4(7) OSCILLATOR 6(10) Q1 C.S. COMP 1V R PWM LATCH 5(8) R 3(5) 5(9) C RS
Ri
2R 2(3) CF RF 1(1) ERROR AMP
Rd
Due to inherent instability of current mode converters running above 50% duty cycle, slope compensation should be added to either the current sense pin or the error amplifier. Figure 6 shows a typical slope compensation technique.
FIGURE 7. -- OPEN LOOP LABORATORY FIXTURE
VREF RT 2N2222 4.7K 100K 1K ERROR AMP ADJUST 4.7K 5K ISENSE ADJUST 3 ISENSE OUTPUT 6 1
UCx84xA
COMP VREF 8
A
VCC
2
VFB
VCC
7
0.1F
0.1F
1K OUTPUT
4
RTCT
GROUND
5
CT
GROUND
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Copyright (c) 1995 Rev. 1.2 12/95
7
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P
RODUCTION
D
ATA
S
HEET
T Y P I C A L A P P L I C AT I O N C I R C U I T S
FIGURE 8. -- OFF-LINE FLYBACK REGULATOR
4.7kW 1W 220F 250V 140kW 1/2W AC INPUT 1N4004 1N4004 1N4935 16V 20kW 4.7kW 2W 3600pF 400V
(continued)
TI
MBR735
1N4004
1N4004
4700F 10V
5V 2-5A
1N4935
UC3844A
2 150kW 1 VFB COMP
7 VCC
1N4935
0.01F
10F 20V
820pF 2.5kW
27kW
IRF830
OUT 6
3.6kW
100pF 8 10kW 4 RT/CT VREF CUR 3 SEN GND 5 1kW 470pF
0.85kW ISOLATION BOUNDARY
0.01F
.0022F
SPECIFICATIONS
Input line voltage: Input frequency: Switching frequency: Output power: Output voltage: Output current: Line regulation: Load regulation: Efficiency @ 25 Watts, VIN = 90VAC: VIN = 130VAC: Output short-circuit current: 90VAC to 130VAC 50 or 60Hz 40KHz 10% 25W maximum 5V +5% 2 to 5A 0.01%/V 8%/A* 70% 65% 2.5Amp average * This circuit uses a low-cost feedback scheme in which the DC voltage developed from the primary-side control winding is sensed by the UC3844A error amplifier. Load regulation is therefore dependent on the coupling between secondary and control windings, and on transformer leakage inductance.
8
Copyright (c) 1995 Rev. 1.2 12/95

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