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INTEGRATED CIRCUITS
DATA SHEET
P80CL31; P80CL51 Low voltage 8-bit microcontrollers with UART
Product specification Supersedes data of January 1995 File under Integrated circuits, IC20 1997 Apr 15
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
CONTENTS 1 2 2.1 3 4 5 6 7 7.1 7.2 8 8.1 8.2 9 9.1 9.2 9.3 9.4 10 10.1 10.2 10.3 10.4 11 12 12.1 12.2 12.3 12.4 12.5 13 13.1 13.2 FEATURES GENERAL DESCRIPTION Versions: P80CL31 and P80C51 APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION OVERVIEW General CPU timing MEMORY ORGANIZATION Program Memory Data Memory Special Function Registers (SFRs) Addressing I/O FACILITIES Ports Port options Port 0 options SET/RESET options TIMERS/EVENT COUNTERS REDUCED POWER MODES Idle mode Power-down mode Wake-up from Power-down mode Power Control Register (PCON) Status of external pins STANDARD SERIAL INTERFACE SIO0: UART Multiprocessor communications Serial Port Control and Status Register (S0CON) 25 26 26.1 26.2 26.3 27 28 13.3 14 14.1 14.2 14.3 15 16 16.1 16.2 17 17.1 17.2 18 19 20 21 22 23 24 24.1 24.2 24.3 Baud rates
P80CL31; P80CL51
INTERRUPT SYSTEM External interrupts INT2 to INT9 Interrupt priority Interrupt registers OSCILLATOR CIRCUITRY RESET External reset using the RST pin Power-on-reset MASK OPTIONS FOR P80CL31 AND P80C51 P80CL31: ROMless version P80C51: 5V standard version SPECIAL FUNCTION REGISTERS OVERVIEW INSTRUCTION SET LIMITING VALUES DC CHARACTERISTICS FOR P80CL31 AND P80CL51 DC CHARACTERISTICS FOR P80C51 AC CHARACTERISTICS P85CL000HFZ `PIGGY-BACK' SPECIFICATION General description Feature differences/additional features with respect to P80CL51 Common specification/feature differences between P85CL000HFZ and P83CL410/P80CL51 PACKAGE OUTLINES SOLDERING Introduction DIP QFP and VSO DEFINITIONS LIFE SUPPORT APPLICATIONS
1997 Apr 15
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
1 FEATURES 2 * Full static 80C51 Central Processing Unit * 8-bit CPU, ROM, RAM, I/O in a 40-lead DIP, 40-lead VSO or 44-lead QFP package * 128 bytes on-chip RAM Data Memory * 4 kbytes on-chip ROM Program Memory for P80CL51 * External memory expandable up to 128 kbytes: RAM up to 64 kbytes and ROM up to 64 kbytes * Four 8-bit ports; 32 I/O lines * Two 16-bit Timer/Event counters * On-chip oscillator suitable for RC, LC, quartz crystal or ceramic resonator * Thirteen source, thirteen vector, nested interrupt structure with two priority levels * Full duplex serial port (UART) * Enhanced architecture with: - non-page oriented instructions - direct addressing - four 8-byte RAM register banks - stack depth limited only by available internal RAM (maximum 128 bytes) - multiply, divide, subtract and compare instructions * Reduced power consumption through Power-down and Idle modes * Wake-up via external interrupts at Port 1 * Frequency range: 0 to 16 MHz (P80C51: 3.5 MHz min.) * Supply voltage: 1.8 to 6.0 V (P80C51: 5.0 V 10%) * Very low current consumption * Operating ambient temperature range: -40 to +85 C. 3 APPLICATIONS
P80CL31; P80CL51
GENERAL DESCRIPTION
The P80CL31; P80CL51 (hereafter generally referred to as the P80CLx1) is manufactured in an advanced CMOS technology. The P80CLx1 has the same instruction set as the 80C51, consisting of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. The device operates over a wide range of supply voltages and has low power consumption; there are two software selectable modes for power reduction: Idle and Power-down. For emulation purposes, the P85CL000 (piggy-back version) with 256 bytes of RAM is recommended. This data sheet details the specific properties of the P80CL31; P80CL51. For details of the 80C51 core see "Data Handbook IC20". 2.1 Versions: P80CL31 and P80C51
The P80CL31 is the ROMless version of the P80CL51. The mask options on the P80CL31 are fixed as follows: * All ports have option `1S' (standard, HIGH after reset) * Oscillator option: Oscillator 3 * Power-on-reset option: OFF. The P80C51 is a restricted-voltage range version of the P80CL51. The operating voltage is 5.0 V 10%.
The P80CLx1 is especially suited for real-time applications such as instrumentation, industrial control, intelligent computer peripherals and consumer products. The P80CLx1 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
4 ORDERING INFORMATION TYPE NUMBER(1) ROMless P80CL31HFP P80CL31HFT P80CL31HFH - - - Note ROM P80CL51HFP P80CL51HFT P80CL51HFH P80C51HFP P80C51HFT P80C51HFH NAME DIP40 PACKAGE DESCRIPTION
P80CL31; P80CL51
VERSION SOT129-1 SOT158-1 SOT307-2 SOT129-1 SOT158-1 SOT307-2
plastic dual in-line package; 40 leads (600 mil)
VSO40 plastic very small outline package; 40 leads QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm DIP40 plastic dual in-line package; 40 leads (600 mil) VSO40 plastic very small outline package; 40 leads QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
1. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program.
1997 Apr 15
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5
1997 Apr 15
counter (1) T0 T1
frequency reference
Philips Semiconductors
BLOCK DIAGRAM
XTAL2
XTAL1
OSCILLATOR AND TIMING
PROGRAM MEMORY (4K x 8 ROM) DATA MEMORY (128 x 8 RAM) TWO 16-BIT TIMER/EVENT COUNTERS
P80CL31 P80CL51
CPU
Low voltage 8-bit microcontrollers with UART
5
64 kbyte BUS EXPANSION CONTROL PROGRAMMABLE I/O PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT control parallel ports, address/data bus and I/O pins RXD (1) TXD
MLA556
10
3
internal interrupts
external interrupts (1)
(1) Pins shared with parallel port pins.
P80CL31; P80CL51
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
6 FUNCTIONAL DIAGRAM
P80CL31; P80CL51
VSS
handbook, full pagewidth
VDD
RST
XTAL1
XTAL2 address and data bus
port 0
EA
PSEN
ALE
P80CL31 P80CL51
port 1
INT2/INT9
RXD / data TXD / clock INT0 alternative functions INT1 T0 T1 WR RD
MLA557
port 3
port 2
address bus
Fig.2 Functional diagram.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
7 7.1 PINNING INFORMATION Pinning
P80CL31; P80CL51
handbook, halfpage
P1.0/INT2 P1.1/INT3 P1.2/INT4 P1.3/INT5 P1.4/INT6 P1.5/INT7 P1.6/INT8 P1.7/INT9 RST
1 2 3 4 5 6 7 8 9
40 V DD 39 38 37 36 35 34 33 32 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9
P3.0/RXD/data 10 P3.0/TXD/clock 11
P80CL31 P80CL51
31 30 29 28 27 26 25 24 23 22
P3.2/INT0 12 P3.3/INT1 13 P3.4/T0 14 P3.5/T1 15 P3.6/WR 16 P3.7/RD 17 XTAL2 18 XTAL1 19 VSS 20
MLA558
21 P2.0/A8
Fig.3 Pin configuration for DIP40 and VSO40 packages.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
44 P1.4/INT6
43 P1.3/INT5
42 P1.2/INT4
41 P1.1/INT3
40 P1.0/INT2
37 P0.0/AD0
36 P0.1/AD1
35 P0.2/AD2
handbook, full pagewidth
34 P0.3/AD3
38 VDD
39 n.c.
P1.5/INT7 P1.6/INT8 P1.7/INT9 RST P3.0/RXD/data n.c. P3.1/TXD/clock P3.2/INT0 P3.3/INT1
1 2 3 4 5 6 7 8 9
33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 EA
P80CL31 P83CL51
28 n.c. 27 ALE 26 PSEN 25 P2.7/A15 24 P2.6/A14 23 P2.5/A13
P3.4/T0 10 P3.5/T1 11
P3.6/WR 12
P3.7/RD 13
XTAL2 14
XTAL1 15
VSS 16
n.c. 17
P2.0/A8 18
P2.1/A9 19
P2.2/A10 20
P2.3/A11 21
P2.4/A12 22
MBK034
Fig.4 Pin configuration for QFP44 package.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
7.2 Pin description
P80CL31; P80CL51
Table 1 Pin description for DIP40 (SOT190-1), VSO40 (SOT319-2) and QFP44 (SOT307-2) packages For more extensive description of the port pins see Chapter 10 "I/O facilities". PIN SYMBOL P1.0/INT2 P1.1/INT3 P1.2/INT4 P1.3/INT5 P1.4/INT6 P1.5/INT7 P1.6/INT8 P1.7/INT9 RST P3.0/RXD/data P3.1/TXD/clock P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD DIP40 VSO40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DESCRIPTION QFP44 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 Reset: a HIGH level on this pin for two machine cycles while the oscillator is running resets the device. * Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7). Same characteristics as Port 1. * Alternative functions: - RXD/data is the serial port receiver data input (asynchronous) or data input/output (synchronous) - TXD/clock is the serial port receiver data output (asynchronous) or clock output (synchronous) - INT0 and INT1 are external interrupts 0 and 1 - T0 and T1 are external inputs for timers 0 and 1 - WR is the external Data Memory write strobe - RD is the external Data Memory read strobe. XTAL2 XTAL1 VSS P2.0 to P2.7 A8 to A15 18 19 20 21 to 28 14 15 16 18 to 25 Crystal oscillator output: output of the inverting amplifier of the oscillator. Left open when external clock is used. Crystal oscillator input: input to the inverting amplifier of the oscillator, also the input for an externally generated clock source. Ground: circuit ground potential. * Port 2: 8-bit bidirectional I/O port (P2.0 to P2.7) with internal pull-ups. Same characteristics as Port 1. * High-order addressing: Port 2 emits the high-order address byte (A8 to A15) during accesses to external memory that use 16-bit addresses (MOVX @DPTR). In this application it uses the strong internal pull-ups when emitting logic 1s. During accesses to external memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. PSEN 29 26 Program Store Enable. Output read strobe to external Program Memory. When executing code out of external Program Memory, PSEN is activated twice each machine cycle. However, during each access to external Data Memory two PSEN activations are skipped. * Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Port pins that have logic 1s written to them are pulled HIGH by internal pull-ups, and in this state can be used as inputs. As inputs, Port 1 pins that are externally pulled LOW will source current (IIL, see Chapter 21) due to the internal pull-ups. Port 1 output buffers can sink/source 4 LS TTL loads. * Alternative functions: - INT2 to INT9 are external interrupt inputs.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
PIN SYMBOL ALE DIP40 VSO40 30
P80CL31; P80CL51
DESCRIPTION QFP44 27 Address Latch Enable. Output pulse for latching the low byte of the address during access to external memory. ALE is emitted at a constant rate of 16 x fosc, and may be used for external timing or clocking purposes (assuming MOVX instructions are not used). External Access. When EA is held HIGH the CPU executes out of internal program memory (unless the program counter exceeds 0FFFH). Holding EA LOW forces the CPU to execute out of external memory regardless of the value of the program counter. * Port 0: 8-bit open-drain bidirectional I/O port. As an open-drain output port it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written to them float, and in that state will function as high impedance inputs. * Low-order addressing: Port 0 is also the multiplexed low-order address and data bus during access to external memory. The strong internal pull-ups are used while emitting logic 1s within the low order address.
EA
31
29
P0.7 to P0.0 AD7 to AD0
32 to 39
30 to 37
VDD n.c.
40 -
38
Power supply.
6, 17, 28, Not connected. 39
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
8 FUNCTIONAL DESCRIPTION OVERVIEW
P80CL31; P80CL51
The P80CLx1 contains 4 kbytes Program Memory (ROM; P80CL51 only); a static 128 bytes Data Memory (RAM); 32 I/O lines; two16-bit timer/event counters; a thirteen-source, two priority-level, nested interrupt structure and on-chip oscillator and timing circuit. A standard UART serial interface is also provided. The device has two software-selectable modes of reduced activity for power reduction: * Idle mode; freezes the CPU while allowing the timers, serial I/O and interrupt system to continue functioning. * Power-down mode; saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. 8.2 CPU timing
This chapter gives a brief overview of the device. The detailed functional description is in the following chapters as follows: Chapter 9 "Memory organization" Chapter 10 "I/O facilities" Chapter 11 "Timers/event counters" Chapter 12 "Reduced power modes" Chapter 13 "Standard serial interface SIO0: UART" Chapter 14 "Interrupt system" Chapter 15 "Oscillator circuitry" Chapter 16 "Reset". 8.1 General
The P80CLx1 is a stand-alone high-performance CMOS microcontroller designed for use in real-time applications such as instrumentation, industrial control, intelligent computer peripherals and consumer products. The device provides hardware features, architectural enhancements and new instructions to function as a controller for applications requiring up to 64 kbytes of Program Memory and/or up to 64 kbytes of Data Memory.
A machine cycle consists of a sequence of 6 states. Each state lasts for two oscillator periods, thus a machine cycle takes 12 oscillator periods or 1 s if the oscillator frequency (fosc) is 12 MHz.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
9 MEMORY ORGANIZATION
P80CL31; P80CL51
internal ROM. Fetches from addresses 1000H to FFFFH are directed to external ROM. Program Counter values greater than 0FFFH are automatically addressed to external memory regardless of the state of the EA pin. 9.2 Data Memory
The P80CLx1 has 4 kbytes of Program Memory (ROM; P80CL51 only) plus 128 bytes of Data Memory (RAM) on board.The device has separate address spaces for Program and Data Memory (see Fig.5). Using Port latches P0 and P2, the P80CLx1 can address a maximum of 64 kbytes of program memory and a maximum of 64 kbytes of data memory. The CPU generates both read (RD) and write (WR) signals for external Data Memory accesses, and the read strobe (PSEN) for external Program Memory. 9.1 Program Memory
The P80CL51 contains 4 kbytes of internal ROM. After reset the CPU begins execution at location 0000H. The lower 4 kbytes of Program Memory can be implemented in either on-chip ROM or external Program Memory. If the EA pin is tied to VDD, then Program Memory fetches from addresses 0000H to 0FFFH are directed to the
The P80CLx1 contains 128 bytes of internal RAM and 25 Special Function Registers (SFR). The memory map (Fig.5) shows the internal Data Memory space divided into the lower 128, the upper 128, and the SFR space. The lower 128 bytes of the internal RAM are organized as mapped in Fig.6. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions refer to these registers within a register bank as R0 through R7. Two bits in the Program Status Word select which register bank is in use. The next 16 bytes above the register banks form a block of bit-addressable memory space. The 128 bits in this area can be directly addressed by the single-bit manipulation instructions. The remaining registers (30H to 7FH) are directly and indirectly byte addressable.
handbook, full pagewidth
64K
EXTERNAL
64K
4096
4095
4095
OVERLAPPED SPACE
INTERNAL (EA = 1)
EXTERNAL (EA = 0)
255
127 INTERNAL DATA RAM 0
SPECIAL FUNCTION REGISTERS
0
PROGRAM MEMORY
INTERNAL DATA MEMORY
MLA559
EXTERNAL DATA MEMORY
Fig.5 Memory map.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, halfpage
7FH
30H 2FH bit-addressable space (bit addresses 0 to 7F)
R7 R0 R7 R0 R7 R0 R7 R0
20H 1FH 18H 17H 10H 0FH 08H 07H 0 4 banks of 8 registers (R0 to R7)
MLA560 - 1
Fig.6 The lower 128 bytes of internal RAM.
9.3
Special Function Registers (SFRs)
The upper 128 bytes are the address locations of the SFRs. Figure 7 shows the SFR space. The SFRs include the port latches, timers, peripheral control, serial I/O registers, etc. These registers can only be accessed by direct addressing. There are 128 directly addressable locations in the SFR address space (SFRs with addresses divisible by eight). 9.4 Addressing
The first three methods can be used for addressing destination operands. Most instructions have a `destination/source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand. Access to memory addressing is as follows: * Registers in one of the four register banks through register, direct or register-indirect * Internal RAM (128 bytes) through direct or register-indirect * Special Function Registers through direct * External data memory through register-indirect * Program Memory look-up tables through base-register plus index-register-indirect.
The P8xCL410 has five methods for addressing source operands: * Register * Direct * Register-indirect * Immediate * Base-register plus index-register-indirect.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
book, full pagewidth
REGISTER MNEMONIC IP1 B IX1 IEN1 ACC PSW IRQ1 IP0 P3 IEN0 P2 S0BUF S0CON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0 87 86 8F 8E 9F 97 9E 96 B7 B6 FF FE F7 F6
BIT ADDRESS FD F5 FC F4 FB F3 FA F2 F9 F1
DIRECT BYTE ADDRESS (HEX) F8 F0 F8H F0H E9H
EF EE ED E7 E6 E5 D5 C5 BD B5
EC EB EA E4 D4 C4 E3 D3 C3 E2 D2 C2
E9 E1
E8 E0
E8H E0H D0H C0H B8H B0H A8H A0H 99H SFRs containing directly addressable bits
D7 D6 C7 C6
D1 D0 C1 C0 B9 B1 A9 A1 B8 B0 A8 A0
BC BB BA B4 B3 B2
AF AE AD A7 A6 A5
AC AB AA A4 A3 A2
9D 95
9C 94
9B 93
9A 92
99 91
98 90
98H 90H 8DH 8CH 8BH 8AH 89H
8D
8C
8B
8A
89
88
88H 87H 83H 82H 81H
85
84
83
82
81
80
MLA561
80H
Fig.7 Special Function Register memory map.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
10 I/O FACILITIES 10.1 Ports
P80CL31; P80CL51
Option 3 Push-pull; output with drive capability in both polarities. Under this option, pins can only be used as outputs; see Fig.8(c). 10.3 Port 0 options
The P80CLx1 has 32 I/O lines treated as 32 individually addressable bits or as four parallel 8-bit addressable ports. Ports 0, 1, 2 and 3 perform the alternative functions detailed below. To enable a port pin alternate function, the port bit latch in its SFR must contain a logic 1. Port 0 Provides the multiplexed low-order address and data bus for expanding the device with standard memories and peripherals. Port 1 Provides the inputs for the external interrupts INT2 to INT9. Port 2 Provides the high-order address when expanding the device with external Program or Data Memory. Port 3 Pins can be configured individually to provide: * External interrupt request inputs: INT1 and INT0 * Timer/counter inputs: T1 and T0 * Control signals to read and write to external memories: RD and WR * UART input and output: RXD/data and TXD/clock. Each port consists of a latch (SFRs P0 to P3), an output driver and input buffer. Ports 1, 2, and 3 have internal pull-ups Figure 8(a) shows that the strong transistor `p1' is turned on for only 2 oscillator periods after a LOW-to-HIGH transition in the port latch. When on, it turns on `p3' (a weak pull-up) through the inverter. This inverter and `p3' form a latch which holds the logic 1. In Port 0 the pull-up `p1' is only on when emitting logic 1s for external memory access. Writing a logic 1 to a Port 0 bit latch leaves both output transistors switched off so that the pin can be used as a high-impedance input. 10.2 Port options
The definition of port options for Port 0 is slightly different. Two cases are considered. First, access to external memory (EA = 0 or access above the built-in memory boundary) and second, I/O accesses. 10.3.1 EXTERNAL MEMORY ACCESSES
Option 1 True logic 0 and logic 1 are written as address to the external memory (strong pull-up to be used). Option 2 An external pull-up resistor is required for external accesses. Option 3 Not allowed for external memory accesses as the port can only be used as output. 10.3.2 I/O ACCESSES
Option 1 When writing a logic 1 to the port latch, the strong pull-up `p1' will be on for 2 oscillator periods. No weak pull-up exists. Without an external pull-up, this option can be used as a high-impedance input. Option 2 Open-drain; quasi-directional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor. See Fig.8(b). Option 3 Push-Pull; output with drive capability in both polarities. Under this option pins can only be used as outputs. See Fig.8(c). 10.4 SET/RESET options
The pins of port 1, port 2 and port 3 may be individually configured with one of the following options. These options are also shown in Fig.8. Option 1 Standard Port; quasi-bidirectional I/O with pull-up. The strong booster pull-up `p1' is turned on for two oscillator periods after a LOW-to-HIGH transition in the port latch; Fig.8(a). Option 2 Open-drain; quasi-bidirectional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor; see Fig.8(b). 1997 Apr 15 15
Individual mask selection of the post-reset state is available with any of the above pins. The required selection is made by appending `S' or `R' to Options 1, 2, or 3 above. Option R RESET, at reset this pin will be initialized LOW. Option S SET, at reset this pin will be initialized HIGH.
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
strong pull-up 2 oscillator periods p1
+5 V
p2 p3 I/O pin
Q from port latch
n
input data read port pin INPUT BUFFER (a) Standard
+5 V
external pull-up Q from port latch I/O pin n
input data read port pin INPUT BUFFER
(b) Open-drain
strong pull-up +5 V
p1 I/O pin Q from port latch n
(c) Push-pull
MGD677
Fig.8 Port configuration options.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
11 TIMERS/EVENT COUNTERS The P80CLx1 contains two16-bit timer/event counter registers; Timer 0 and Timer 1, which can perform the following functions: * Measure time intervals and pulse durations * Count events * Generate interrupt requests. In the `Timer' operating mode the register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 112 x fosc. In the `Counter' operating mode, the register is incremented in response to a HIGH-to-LOW transition. Since it takes 2 machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition, the maximum count rate is 124 x fosc. To ensure a given level is sampled, it should be held for at least one complete machine cycle. Timer 0 and Timer 1 can be programmed independently to operate in four modes: Mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. Mode 1 16-bit time-interval or event counter. Mode 2 8-bit time-interval or event counter with automatic reload upon overflow. Mode 3 Timer 0 establishes TL0 and TH0 as two separate counters. 12 REDUCED POWER MODES There are two software selectable modes of reduced activity for further power reduction: Idle and Power-down. 12.1 Idle mode
P80CL31; P80CL51
The following functions remain active during the Idle mode: * Timer 0 and Timer 1 * UART * External interrupt. These functions may generate an interrupt or reset; thus ending the Idle mode. There are two ways to terminate the Idle mode: 1. Activation of any enabled interrupt will cause IDL (PCON.0) to be cleared by hardware thus terminating the Idle mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the Idle mode. The flag bits GF0 (PCON.2) and GF1 (PCON.3) may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When the Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. 2. The second way of terminating the Idle mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. Reset redefines all SFRs but does not affect the on-chip RAM. 12.2 Power-down mode
Operation in Power-down mode freezes the oscillator. The internal connections which link both Idle and Power-down signals to the clock generation circuit are shown in Fig.9. Power-down mode is entered by setting the PD bit in the Power Control Register (PCON.1, see Table 2). The instruction that sets PD is the last executed prior to going into the Power-down mode. Once in the Power-down mode, the oscillator is stopped. The contents of the on-chip RAM and the SFRs are preserved. The port pins output the value held by their respective SFRs. ALE and PSEN are held LOW. In the Power-down mode, VDD may be reduced to minimize circuit power consumption. The supply voltage must not be reduced until the Power-down mode is entered, and must be restored before the hardware reset is applied which will free the oscillator. Reset should not be released until the oscillator has restarted and stabilized.
Idle mode operation permits the external interrupts, UART, and timer blocks to continue to function while the clock to the CPU is halted. Idle mode is entered by setting the IDL bit in the Power Control Register (PCON.0, see Table 2). The instruction that sets IDL is the last instruction executed in the normal operating mode before the Idle mode is activated. Once in Idle mode, the CPU status is preserved along with the Stack Pointer, Program Counter, Program Status Word and Accumulator. The RAM and all other registers maintain their data during Idle mode. The status of the external pins during Idle mode is shown in Table 3.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
12.3 Wake-up from Power-down mode 12.4
P80CL31; P80CL51
Power Control Register (PCON)
When in Power-down mode the controller can be woken-up with either the external interrupts INT2 to INT9, or a reset operation. The wake-up operation has two basic approaches as explained in Section 12.3.1; 12.3.2 and illustrated in Fig.10. 12.3.1 WAKE-UP USING INT2 TO INT9
See Tables 2 and 3. Idle and Power-down modes are activated by software using this SFR. PCON is not bit-addressable. 12.5 Status of external pins
If any of the interrupts INT2 to INT9 are enabled, the device can be woken-up from the Power-down mode with the external interrupts. To ensure that the oscillator is stable before the controller restarts, the internal clock will remain inactive for 1536 oscillator periods. This is controlled by an on-chip delay counter. 12.3.2 WAKE-UP USING RST
The status of the external pins during Idle and Power-down mode is shown in Table 4. If the Power-down mode is activated whilst accessing external Program Memory, the port data that is held in the Special Function Register P2 is restored to Port 2. If the data is a logic 1, the port pin is held HIGH during the Power-down mode by the strong pull-up transistor `p1'; see Fig.8(a).
To wake-up the P80CLx1, the RST pin must be kept HIGH for a minimum of 24 periods. The on-chip delay counter is inactive. The user must ensure that the oscillator is stable before any operation is attempted. Table 2 7 SMOD Table 3 BIT 7 6, 5, 4 3 and 2 1 0 Table 4 Power Control Register (address 87H) 6 - 5 - 4 - 3 GF1 2 GF0 1 PD 0 IDL
Description of PCON bits SYMBOL SMOD - PD IDL reserved Power-down bit; setting this bit activates the Power-down mode Idle mode bit; setting this bit activates the Idle mode DESCRIPTION Double Baud rate bit; see description of UART
GF1 and GF0 General purpose flag bits
Status of external pins during Idle and Power-down modes MEMORY internal external internal external ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 port data floating port data floating PORT 1 port data port data port data port data PORT 2 port data address port data port data PORT 3 port data port data port data port data PORT 4 port data port data port data port data
MODE Idle Power-down
1997 Apr 15
18
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
XTAL2
XTAL1
OSCILLATOR
interrupts serial ports timer blocks CLOCK GENERATOR CPU
PD
IDL
MLA563
Fig.9 Internal clock control in Idle and Power-down mode.
handbook, full pagewidth
power-down
RST pin
external interrupt
oscillator
MGD679
delay counter 1536 periods
24 periods
Fig.10 Wake-up operation.
1997 Apr 15
19
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
13 STANDARD SERIAL INTERFACE SIO0: UART This serial port is full duplex which means that it can transmit and receive simultaneously. It is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte has not been read by the time the reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed via the Special Function Register S0BUF. Writing to S0BUF loads the transmit register and reading S0BUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight bits are transmitted/received (LSB first). The baud rate is fixed at 112 x fosc. Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). On receive, the stop bit goes into RB8 in Special Function Register S0CON. The baud rate is variable. Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). On transmit, the 9th data bit (TB8 in S0CON) can be assigned the value of a logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in S0CON, while the stop bit is ignored. The baud rate is programmable to either 132 or 164 x fosc. Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable.
P80CL31; P80CL51
In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. 13.1 Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th bit goes into RB8. The following bit is the stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated, but only if RB8 = 1. This feature is enabled by setting bit SM2 in S0CON. One use of this feature, in multiprocessor systems, is as follows. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is HIGH in an address byte and LOW in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be sent. The slaves that were not being addressed leave their SM2 bits set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 13.2 Serial Port Control and Status Register (S0CON)
The Serial Port Control and Status Register is the Special Function Register S0CON. The register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).
1997 Apr 15
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
Table 5 7 SM0 Table 6 BIT 7 6 5 Serial Port Control Register (address 98H) 6 SM1 5 SM2 4 REN 3 TB8 2 RB8
P80CL31; P80CL51
1 TI
0 RI
Description of S0CON bits SYMBOL SM0 SM1 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In these modes, if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be a logic 0. Enables serial reception and is set by software to enable reception, and cleared by software to disable reception. Is the 9th data bit that will be transmitted in Modes 2 and 3; set or cleared by software as desired. In Modes 2 and 3, is the 9th data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop bit that was received; in Mode 0, RB8 is not used. The transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. Must be cleared by software. The receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (except see SM2). Must be cleared by software. DESCRIPTION These bits are used to select the serial port mode; see Table 7.
4 3 2 1
REN TB8 RB8 TI
0
RI
Table 7 SM0 0 0 1 1
Selection of the serial port modes SM1 0 1 0 1 MODE Mode 0 Mode 1 Mode 2 Mode 3 DESCRIPTION Shift register 8-bit UART 9-bit UART 9-bit UART
1 32
BAUD RATE
1 12
x fosc
variable or 164 x fosc variable
1997 Apr 15
21
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
13.3 Baud rates follows:
P80CL31; P80CL51
The baud rate in Mode 0 is fixed and may be calculated as: f osc Baud Rate = -------12 The baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON and may be calculated as: 2 Baud Rate = ---------------- x f osc 64 * If SMOD = 0 (value on reset), the baud rate is 164 x fosc * If SMOD = 1, the baud rate is 132 x fosc The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. 13.3.1 USING TIMER 1 TO GENERATE BAUD RATES
SMOD
2 Baud Rate = ---------------- x Timer 1 Overflow Rate. 32 The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either `timer' or `counter' operation in any of its 3 running modes. In most typical applications, it is configured for `timer' operation, in the Auto-reload mode (high nibble of TMOD = 0010B). In this case the baud rate is given by the formula:
SMOD f osc 2 Baud Rate = ---------------- x ------------------------------------------------------32 { 12 x ( 256 - TH1 ) }
SMOD
When Timer 1 is used as the Baud Rate Generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of the SMOD bit as Table 8 Commonly used baud rates generated by Timer 1 fosc (MHz) 16.000 16.000 16.000 11.059 11.059 11.059 11.059 11.059 11.986 6.000 12.000 SMOD X(2) 1 1 1 0 0 0 0 0 0 0
By configuring Timer 1 to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload, very low baud rates can be achieved. Table 8 lists commonly used baud rates and how they can be obtained from Timer 1.
BAUD RATE (kbits/s) 1330.0(1) 500.0(3) 83.3(4) 19.2 9.6 4.8 2.4 1.2 137.5 110.0 110.0 Notes 1. Maximum in Mode 0. 2. X = don't care. 3. Maximum in Mode 2.
C/T X X 0 0 0 0 0 0 0 0 0
TIMER 1 MODE X X Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 1
RELOAD VALUE X X FFH FDH FDH FAH F4H E8H 1DH 72H FEEBH
4. Maximum in Modes 1 and 3.
1997 Apr 15
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
andbook, full pagewidth
INTERNAL BUS
write to SBUF RXD P3.0 ALT output function SHIFT
DS CL
Q
S0 BUFFER
ZERO DETECTOR
START S6 TX CLOCK
TX CONTROL
T1
SHIFT SEND
serial port interrupt SHIFT CLOCK R1
TXD P3.1 ALT output function
RX CLOCK REN RI START
RECEIVE
RX CONTROL
SHIFT 1 1 11111 0
INPUT SHIFT REGISTER SHIFT LOAD SBUF
RXD P3.0 ALT input function
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC752
Fig.11 Serial port Mode 0.
1997 Apr 15
23
P80CL31; P80CL51
Product specification
Fig.12 Serial port Mode 0 timing.
handbook, full pagewidth
1997 Apr 15
D1 D2 D3 D4 D5 D6 D7 T R A N S M I T S6P1
...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6
Philips Semiconductors
ALE
WRITE TO SBUF
SEND
S6P2
SHIFT
RXD (DATA OUT)
D0
TSC (SHIFT CLOCK)
S3P1
WRITE TO SCON (CLEAR R1)
Low voltage 8-bit microcontrollers with UART
24
D0 D1 D2 D3 D4 D5
RI
RECEIVE
R E C E I V E D6 D7
SHIFT RXD (DATA IN)
S5P2
MLA567
TXD (SHIFT CLOCK)
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
dbook, full pagewidth
INTERNAL BUS TB8
Timer 1 overflow
Timer 2 overflow
write to SBUF
2 0 SMOD RTCLK 1 0 1
DS Q CL
S0 BUFFER
TXD
ZERO DETECTOR
SHIFT
START 16 TX CLOCK
TX CONTROL
T1
SHIFT DATA SEND
serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC755
Fig.13 Serial port Mode 1.
1997 Apr 15
25
P80CL31; P80CL51
Product specification
Fig.14 Serial port Mode 1 timing.
handbook, full pagewidth
1997 Apr 15
D0 D1 D6 D2 D3 D7 D4 D5 STOP BIT T R A N S M I T /16 RESET
Philips Semiconductors
TX CLOCK
WRITE TO SBUF
SEND
DATA
S1P1
SHIFT
TXD
START BIT
TI
Low voltage 8-bit microcontrollers with UART
RX CLOCK START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT
26
RXD
R E C E I V E
BIT DETECTOR SAMPLE TIME
SHIFT
RI
MLA569
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF
phase 2 clock (fosc / 2)
DS CL
Q
S0 BUFFER
TXD
2 0 CSMOD at PCON.7 1 SHIFT ZERO DETECTOR
STOP BIT START 16 TX CLOCK
TX CONTROL
T1
SHIFT DATA SEND
serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC754
Fig.15 Serial port Mode 2.
1997 Apr 15
27
P80CL31; P80CL51
Product specification
Fig.16 Serial port Mode 2 timing.
handbook, full pagewidth
1997 Apr 15
D0 STOP BIT D1 D2 D3 D7 TB8 D4 D5 D6 T R A N S M I T /16 RESET
Philips Semiconductors
TX CLOCK
WRITE TO SBUF
SEND
DATA
S1P1
SHIFT
TXD
START BIT
TI
STOP BIT GEN
RX CLOCK START BIT D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP BIT
Low voltage 8-bit microcontrollers with UART
28
RXD
R E C E I V E
BIT DETECTOR SAMPLE TIME
SHIFT
MLA571
RI
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF Timer 1 overflow Timer 2 overflow
DS CL
Q
S0 BUFFER
TXD
2 0 SMOD RTCLK SHIFT DATA SEND T1 serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT 1 0 1 ZERO DETECTOR SHIFT
START 16 TX CLOCK
TX CONTROL
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC753
Fig.17 Serial port Mode 3.
1997 Apr 15
29
P80CL31; P80CL51
Product specification
Fig.18 Serial port Mode 3 timing.
handbook, full pagewidth
1997 Apr 15
D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT T R A N S M I T /16 RESET
Philips Semiconductors
TX CLOCK
WRITE TO SBUF
DATA
SEND
S1P1
SHIFT
TXD
START BIT
TI
Low voltage 8-bit microcontrollers with UART
RX CLOCK START BIT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT
30
RXD
R E C E I V E
BIT DETECTOR SAMPLE TIME
SHIFT
RI
MLA573
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
14 INTERRUPT SYSTEM External events and the real-time-driven on-chip peripherals require service by the CPU at unpredictable times. To tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. The system is shown in Fig.19. The P80CLx1 acknowledges interrupt requests from thirteen sources as follows: * INT0 to INT9 * Timer 0 and Timer 1 * UART. Each interrupt vectors to a separate location in Program Memory for its service routine. Each source can be individually enabled or disabled by corresponding bits in the Interrupt Enable Registers (IEN0 and IEN1). The priority level is selected via the Interrupt Priority Registers (IP0 and IP1). All enabled sources can be globally disabled or enabled. Figure 19 shows the interrupt system. 14.1 External interrupts INT2 to INT9 Table 9 14.2 Interrupt priority
P80CL31; P80CL51
Each interrupt source can be set to either a high priority or to a low priority. If a low priority interrupt is received simultaneously with a high priority interrupt, the high priority interrupt will be dealt with first. If interrupts of the same priority are requested simultaneously, the processor will branch to the interrupt polled first, according to the sequence shown in Table 9 and in Fig.19. The `vector address' is the ROM location where the appropriate interrupt service routine starts. Interrupt vector polling sequence VECTOR ADDRESS (HEX) 0003 002B 0053 000B 005B 0013 003B 0063 001B 0043 006B 004B 0073 SOURCE External 0 UART External 5 Timer 0 External 6 External 1 External 2 External 7 Timer 1 External 3 External 8 External 4 External 9
SYMBOL X0 (first) S0 X5 T0 X6 X1 X2 X7 T1 X3 X8 X4 X9 (last)
Port 1 lines serve an alternative purpose as eight additional interrupts INT2 to INT9. When enabled, each of these lines may wake-up the device from the Power-down mode. Using the Interrupt Polarity Register (IX1), each pin may be initialized to be either active HIGH or active LOW. IRQ1 is the Interrupt Request Flag Register. If the interrupt is enabled, each flag will be set on an interrupt request but must be cleared by software, i.e. via the interrupt software or when the interrupt is disabled. Port 1 interrupts are level sensitive. A Port 1 interrupt will be recognized when a level (HIGH or LOW depending on the Interrupt Polarity Register) on P1.n is held active for at least one machine cycle. The interrupt request is not serviced until the next machine cycle. Figure 20 shows the external interrupt configuration.
A low priority interrupt routine can only be interrupted by a high priority interrupt. A high priority interrupt routine cannot be interrupted.
1997 Apr 15
31
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
INTERRUPT SOURCES X0
IEN0/1 REGISTERS
IP0/1
PRIORITY HIGH LOW
S0
X5
T0
X6 INTERRUPT POLLING SEQUENCE GLOBAL ENABLE
MLA574
X1
X2
X7
T1
X3
X8
X4
X9
Fig.19 Interrupt system.
1997 Apr 15
32
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
IX1
IEN1
IRQ1 X9
P1.7
P1.6
X8
P1.5
X7
P1.4
X6
P1.3
X5
P1.2
X4
P1.1
X3
P1.0
X2
MLA575
WAKE-UP
Fig.20 External interrupt configuration.
14.3
Interrupt registers
The registers used in the interrupt system are listed in Table 10. Tables 11 to 22 describe the contents of these registers. Table 10 Special Function Registers related to the interrupt system ADDRESS A8H E8H B8H F8H E9H C0H REGISTER IEN0 IEN1 IP0 IP1 IX1 IRQ1 Interrupt Enable Register Interrupt Enable Register (INT2 to INT9) Interrupt Priority Register Interrupt Priority Register (INT2 to INT9 Interrupt Polarity Register Interrupt Request Flag Register DESCRIPTION
1997 Apr 15
33
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
14.3.1 INTERRUPT ENABLE REGISTER (IEN0)
P80CL31; P80CL51
Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 11 Interrupt Enable Register (SFR address A8H) 7 EA 6 - 5 - 4 ES0 3 ET1 2 EX1 1 ET0 0 EX0
Table 12 Description of IEN0 bits BIT 7 6 5 4 3 2 1 0 14.3.2 SYMBOL EA - - ES0 ET1 EX1 ET0 EX0 DESCRIPTION general enable/disable control. If EA = 0, no interrupt is enabled; if EA = 1, any individually enabled interrupt will be accepted reserved reserved enable UART SIO interrupt enable Timer 1 interrupt (T1) enable external interrupt 1 enable Timer 0 interrupt (T0) enable external interrupt 0
INTERRUPT ENABLE REGISTER (IEN1)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 13 Interrupt Enable Register (SFR address E8H) 7 EX9 6 EX8 5 EX7 4 EX6 3 EX5 2 EX4 1 EX3 0 EX2
Table 14 Description of IEN1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2 enable external interrupt 9 enable external interrupt 8 enable external interrupt 7 enable external interrupt 6 enable external interrupt 5 enable external interrupt 4 enable external interrupt 3 enable external interrupt 2 DESCRIPTION
1997 Apr 15
34
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
14.3.3 INTERRUPT PRIORITY REGISTER (IP0)
P80CL31; P80CL51
Bit values: 0 = low priority; 1 = high priority. Table 15 Interrupt Priority Register (SFR address B8H) 7 - 6 - 5 - 4 PS0 3 PT1 2 PX1 1 PT0 0 PX0
Table 16 Description of IP0 bits BIT 7 6 5 4 3 2 1 0 14.3.4 SYMBOL - - - PS0 PT1 PX1 PT0 PX0 reserved reserved reserved UART SIO interrupt priority level Timer 1 interrupt priority level external interrupt 1 priority level Timer 0 interrupt priority level external interrupt 0 priority level DESCRIPTION
INTERRUPT PRIORITY REGISTER (IP1)
Bit values: 0 = low priority; 1 = high priority. Table 17 Interrupt Priority Register (SFR address F8H) 7 PX9 6 PX8 5 PX7 4 PX6 3 PX5 2 PX4 1 PX3 0 PX2
Table 18 Description of IP1 bits BIT 7 6 5 4 3 SYMBOL PX9 PX8 PX7 PX6 PX5 external interrupt 9 priority level external interrupt 8 priority level external interrupt 7 priority level external interrupt 6 priority level external interrupt 5 priority level DESCRIPTION
1997 Apr 15
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
BIT 2 1 0 14.3.5 SYMBOL PX4 PX3 PX2 external interrupt 4 priority level external interrupt 3 priority level external interrupt 2 priority level DESCRIPTION
P80CL31; P80CL51
INTERRUPT POLARITY REGISTER (IX1)
Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external interrupt to an active HIGH or active LOW respectively. Table 19 Interrupt Polarity Register (SFR address E9H) 7 IL9 6 IL8 5 IL7 4 IL6 3 IL5 2 IL4 1 IL3 0 IL2
Table 20 Description of IX1 bits BIT 7 6 5 4 3 2 1 0 14.3.6 SYMBOL IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 external interrupt 9 polarity level external interrupt 8 polarity level external interrupt 7 polarity level external interrupt 6 polarity level external interrupt 5 polarity level external interrupt 4 polarity level external interrupt 3 polarity level external interrupt 2 polarity level DESCRIPTION
INTERRUPT REQUEST FLAG REGISTER (IRQ1)
Table 21 Interrupt Request Flag Register (SFR address C0H) 7 IQ9 6 IQ8 5 IQ7 4 IQ6 3 IQ5 2 IQ4 1 IQ3 0 IQ2
Table 22 Description of IRQ1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 external interrupt 9 request flag external interrupt 8 request flag external interrupt 7 request flag external interrupt 6 request flag external interrupt 5 request flag external interrupt 4 request flag external interrupt 3 request flag external interrupt 2 request flag DESCRIPTION
1997 Apr 15
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
15 OSCILLATOR CIRCUITRY The on-chip oscillator circuitry of the P80CLx1 is a single-stage inverting amplifier biased by an internal feedback resistor. The oscillator circuit is shown in Fig.22. For operation as a standard quartz oscillator, no external components are needed, except for the 32 kHz option. When using external capacitors, ceramic resonators, coils and RC networks to drive the oscillator, five different configurations are supported (see Table 23 and Fig.21). In the Power-down mode the oscillator is stopped and XTAL1 is pulled HIGH. The oscillator inverter is switched off to ensure no current will flow regardless of the voltage at XTAL1, for configurations (a), (b), (c), (d), (e) and (g) of Fig.21. Table 23 Oscillator options OPTION Oscillator 1 Oscillator 2 Oscillator 3 Oscillator 4 RC oscillator APPLICATION
P80CL31; P80CL51
To drive the device with an external clock source, apply the external clock signal to XTAL1, and leave XTAL2 to float, as shown in Fig.21(f). There are no requirements on the duty cycle of the external clock, since the input to the internal clocking circuitry is buffered by a flip-flop. Various oscillator options are provided for optimum on-chip oscillator performance; these are specified in Table 23 and shown in Fig.21. The required option should be stated when ordering.
for 32 kHz clock applications with external trimmer for frequency adjustment; a 4.7 M bias resistor is needed for use in parallel with the crystal; see Fig.21(c) low-power, low-frequency operations using LC components; see Fig.21(e) medium frequency range applications high frequency range applications RC oscillator configuration; see Figs 21(g) and 23
handbook, full pagewidth
STANDARD QUARTZ OSCILLATOR XTAL1 XTAL2
QUARTZ OSCILLATOR WITH EXTERNAL CAPACITORS
32 kHz OSCILLATOR XTAL1 XTAL2
XTAL1
XTAL2
(a)
(b)
(c)
CERAMIC RESONATOR XTAL1 XTAL2
LC - OSCILLATOR XTAL1 XTAL2
EXTERNAL CLOCK XTAL1 XTAL2 n.c.
RC - OSCILLATOR XTAL1 n.c. VDD XTAL2
(d)
(e)
(f)
(g)
MLA577
Fig.21 Oscillator configurations.
1997 Apr 15
37
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
VDD
P80CL31 P80CL51
VDD PD
to internal timing circuits
VDD
C1 i
R bias
C2 i
XTAL1
XTAL2
MLA576
Fig.22 Standard oscillator.
MLA579
handbook, halfpage
600
f osc (kHz)
400
200
0 0 2 4 RC (s) 6
RC oscillator frequency is externally adjustable; 100 kHz fosc 500 kHz.
Fig.23 RC oscillator frequency as a function of RC.
1997 Apr 15
38
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
Table 24 Oscillator type selection guide RESONATOR Quartz FREQUENCY (MHz) 0.032 1.0 3.58 4.0 6.0 10.0 12.0 16.0 PXE 0.455 1.0 3.58 4.0 6.0 10.0 12.0 LC - Oscillator 3 Oscillator 4 Oscillator 2 Oscillator 2 Oscillator 4 Oscillator 3 Oscillator 2 OPTION (see Table 23) Oscillator 1 C1 EXT. (pF) MIN. 0 0 0 0 0 0 0 0 40 15 0 0 0 0 10 20 MAX. 0 30 15 20 10 15 10 15 50 50 40 40 20 15 40 90
P80CL31; P80CL51
C2 EXT. (pF) MIN. 5 0 0 0 0 0 0 0 40 15 0 0 0 0 10 20 MAX. 15 30 15 20 10 15 10 15 50 50 40 40 20 15 40 90
RESONATOR MAX. SERIES RESISTANCE 15 k(1) 600 100 75 60 60 40 20 10 100 10 10 5 6 6 10 H = 1 100 H = 5 1 mH = 75
Note 1. 32 kHz quartz crystals with a series resistance >15 k will reduce the guaranteed supply voltage range to 2.5 to 3.5 V.
1997 Apr 15
39
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
Rf
handbook, full pagewidth
XTAL1 C1 i V1 gm R2 C2 i
XTAL2
MLA578
Fig.24 Oscillator equivalent circuit diagram.
Table 25 Oscillator equivalent circuit parameters The equivalent circuit data of the internal oscillator compares with that of matched crystals. SYMBOL gm PARAMETER transconductance OPTION Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 C1i input capacitance Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 C2i output capacitance Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 R2 output resistance Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 CONDITION Tamb = +25 C; VDD = 4.5 V MIN. - 200 400 1000 - - - - - - - - - - - - TYP. 15 600 1500 4000 3.0 8.0 8.0 8.0 23 8.0 8.0 8.0 3800 65 18 5.0 MAX. - 1000 4000 - - - - - - - - - - - - UNIT S S S pF pF pF pF pF pF pF pF k k k k
10000 S
1997 Apr 15
40
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
16 RESET To initialize the P80CLx1 a reset is performed by either of three methods: * Applying an external signal to the RST pin * Via Power-on-reset circuitry. A reset leaves the internal registers as shown in Chapter 18. The reset state of the port pins is mask-programmable and can be defined by the user. 16.1 External reset using the RST pin 16.2 Power-on-reset
P80CL31; P80CL51
The reset input for the P80CLx1 is RST. A Schmitt trigger is used at the input for noise rejection. The output of the Schmitt trigger is sampled by the reset circuitry every machine cycle. A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU responds by executing an internal reset. Port pins adopt their reset state immediately after the RST goes HIGH. During reset, ALE and PSEN are held HIGH. The external reset is asynchronous to the internal clock. The RST pin is sampled during state 5, phase 2 of every machine cycle. After a HIGH is detected at the RST pin, an internal reset is repeated until RST goes LOW. The internal RAM is not affected by reset. When VDD is turned on, the RAM contents are indeterminate.
The device contains on-chip circuitry which switches the port pins to the customer defined logic level as soon as VDD exceeds 1.3 V; if the mask option `ON' has been chosen. As soon as the minimum supply voltage is reached, the oscillator will start up. However, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the CPU for a further 1536 oscillator periods. During that time the CPU is held in a reset state. A hysteresis of approximately 50 mV at a typical power-on switching level of 1.3 V will ensure correct operation (see Fig.27). The on-chip Power-on-reset circuitry can also be switched off via the mask option `OFF'. This option reduces the Power-down current to typically 800 nA and can be chosen if external reset circuitry is used. For applications not requiring the internal reset, option `OFF' should be chosen. An automatic reset can be obtained by connecting the RST pin to VDD via a 10 F capacitor. At power-on, the voltage on the RST pin is equal to VDD minus the capacitor voltage, and decreases from VDD as the capacitor charges through the internal resistor (RRST) to ground. The larger the capacitor, the more slowly VRST decreases. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start-up time, plus 2 machine cycles. The Power-on-reset circuitry is shown in Fig.26.
DD handbook, halfpage
V
VDD
handbook, halfpage
SCHMITT TRIGGER RESET CIRCUITRY
MLA580
10 F
P80CL31 P80CL51
RST
RST
R RST
MLA582
Fig.25 Reset configuration.
Fig.26 Recommended Power-on-reset circuitry.
1997 Apr 15
41
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
switching level POR
handbook, full pagewidth SUPPLY
VOLTAGE
hysteresis
POWER-ON-RESET (INTERNAL)
OSCILLATOR
CPU RUNNING
MLA581
Start-up time
1536 oscillator periods delay
Fig.27 Power-on-reset switching level.
17 17.1
MASK OPTIONS FOR P80CL31 AND P80C51 P80CL31: ROMless version
17.2
P80C51: 5 V standard version
The P80CL31 is a low voltage ROMless version of the P80CL51 microcontroller. The mask options for the P80CL31 are fixed as follows: * Port options: all ports have option "1S", i.e. standard port, HIGH after reset * Oscillator option: Oscillator 3 * Power-on-reset option: OFF.
The P80C51 is a 5 V version of the low voltage P80CL51 microcontroller. All functional features of the P80CL51 are maintained in the P80C51 with the exception of the mask options. The mask options on the P80C51 are fixed as follows: * Port options: all ports have option "1S", i.e. standard port, HIGH after reset * Oscillator option: Oscillator 3 * Power-on-reset option: OFF.
1997 Apr 15
42
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
18 SPECIAL FUNCTION REGISTERS OVERVIEW The P80CLx1 has 25 SFRs available to the user. ADDRESS (HEX) F8 F0 E9 E8 E0 D0 C0 B8 B0 A8 A0 99 98 90 8D 8C 8B 8A 89 88 87 83 82 81 80 Notes 1. Bit addressable register. 2. Port reset state determined by the customer. B(1) IX1 IEN1(1) ACC(1) PSW(1) IRQ1(1) IP0(1) P3(1) IEN0(1) P2(1) S0BUF S0CON(1) P1(1) TH1 TH0 TL1 TL0 TMOD TCON(1) PCON DPH DPL SP P0(1) NAME IP1(1) RESET VALUE (B) 00000000 00000000 00000000 00000000 00000000 00000000 00000000 X0000000 XXXXXXXX(2) 00000000 XXXXXXXX(2) XXXXXXXX 00000000 XXXXXXXX(2) 00000000 00000000 00000000 00000000 00000000 00000000 0XX00000 00000000 00000000 00000111 XXXXXXXX(2) B Register Interrupt Polarity Register Interrupt Enable Register 1 Accumulator Program Status Word Interrupt Request Flag Register Interrupt Priority Register 0 Digital I/O Port Register 3 Interrupt Enable Register Digital I/O Port Register 2 Serial Data Buffer Register 0 Serial Port Control Register 0 Digital I/O Port Register 1 Timer 1 High byte Timer 0 High byte Timer 1 Low byte Timer 0 Low byte Timer 0 and 1 Mode Control Register
P80CL31; P80CL51
FUNCTION Interrupt Priority Register (INT2 to INT9)
Timer 0 and 1 Control/External Interrupt Control Register Power Control Register Data Pointer High byte Data Pointer Low byte Stack Pointer Digital I/O Port Register 0
1997 Apr 15
43
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
19 INSTRUCTION SET
P80CL31; P80CL51
The P80CLx1 uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes byte efficiency and execution speed. Assigned opcodes add new high-power operation and permit new addressing modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz oscillator, 64 instructions execute in 1 s and 45 instructions execute in 2 s. Multiply and divide instructions execute in 4 s. For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 30. Table 26 Instruction set description: Arithmetic operations MNEMONIC Arithmetic operations ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A Rr direct @Ri A Rr direct @Ri DPTR AB AB A add register to A add direct byte to A add indirect RAM to A add immediate data to A add register to A with carry flag add direct byte to A with carry flag add indirect RAM to A with carry flag add immediate data to A with carry flag subtract register from A with borrow subtract direct byte from A with borrow subtract indirect RAM from A with borrow subtract immediate data from A with borrow increment A increment register increment direct byte increment indirect RAM decrement A decrement register decrement direct byte decrement indirect RAM increment data pointer multiply A and B divide A by B decimal adjust A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 2* 25 26, 27 24 3* 35 36, 37 34 9* 95 96, 97 94 04 0* 05 06, 07 14 1* 15 16, 17 A3 A4 84 D4 DESCRIPTION BYTES CYCLES OPCODE (HEX)
1997 Apr 15
44
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
Table 27 Instruction set description: Logic operations MNEMONIC Logic operations ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A A A A A A A AND register to A AND direct byte to A AND indirect RAM to A AND immediate data to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR indirect RAM to A OR immediate data to A OR A to direct byte OR immediate data to direct byte exclusive-OR register to A exclusive-OR direct byte to A exclusive-OR indirect RAM to A exclusive-OR immediate data to A exclusive-OR A to direct byte exclusive-OR immediate data to direct byte clear A complement A rotate A left rotate A left through the carry flag rotate A right rotate A right through the carry flag swap nibbles within A DESCRIPTION
P80CL31; P80CL51
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1
1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1
5* 55 56, 57 54 52 53 4* 45 46, 47 44 42 43 6* 65 66, 67 64 62 63 E4 F4 23 33 03 13 C4
1997 Apr 15
45
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
Table 28 Instruction set description: Data transfer MNEMONIC Data transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD Note 1. MOV A,ACC is not permitted. A,Rr A,@Ri A,#data Rr,A Rr,direct Rr,#data direct,A direct,Rr direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data A,@A+DPTR A,@A+PC A,@Ri A,@DPTR @Ri,A @DPTR,A direct direct A,Rr A,direct A,@Ri A,@Ri move register to A move indirect RAM to A move immediate data to A move A to register move direct byte to register move immediate data to register move A to direct byte move register to direct byte move direct byte to direct move indirect RAM to direct byte move immediate data to direct byte move A to indirect RAM move direct byte to indirect RAM move immediate data to indirect RAM move code byte relative to DPTR to A move code byte relative to PC to A move external RAM (8-bit address) to A move external RAM (16-bit address) to A move A to external RAM (8-bit address) move A to external RAM (16-bit address) push direct byte onto stack pop direct byte from stack exchange register with A exchange direct byte with A exchange indirect RAM with A exchange LOW-order digit indirect RAM with A DESCRIPTION
P80CL31; P80CL51
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1
1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1
E* E5 E6, E7 74 F* A* 7* F5 8* 85 86, 87 75 F6, F7 A6, A7 76, 77 90 93 83 E2, E3 E0 F2, F3 F0 C0 D0 C* C5 C6, C7 D6, D7
A,direct (note 1) move direct byte to A
DPTR,#data 16 load data pointer with a 16-bit constant
1997 Apr 15
46
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
Table 29 Instruction set description: Boolean variable manipulation, Program and machine control MNEMONIC Boolean variable manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C clear carry flag clear direct bit set carry flag set direct bit complement carry flag complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag move direct bit to carry flag move carry flag to direct bit 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 *1 12 22 32 1 02 80 73 60 70 40 50 20 30 10 B5 B4 B* B6, B7 D* D5 00 DESCRIPTION BYTES CYCLES OPCODE (HEX)
Program and machine control ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr11 addr16 rel @A+DPTR rel rel rel rel bit,rel bit,rel bit,rel A,direct,rel A,#data,rel Rr,#data,rel Rr,rel direct,rel addr11 addr16 absolute subroutine call long subroutine call return from subroutine return from interrupt absolute jump long jump short jump (relative address) jump indirect relative to the DPTR jump if A is zero jump if A is not zero jump if carry flag is set jump if carry flag is not set jump if direct bit is set jump if direct bit is not set jump if direct bit is set and clear bit compare direct to A and jump if not equal compare immediate to A and jump if not equal compare immediate to register and jump if not equal decrement register and jump if not zero decrement direct and jump if not zero no operation 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
@Ri,#data,rel compare immediate to indirect and jump if not equal
1997 Apr 15
47
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
Table 30 Description of the mnemonics in the Instruction set MNEMONIC Data addressing modes Rr direct @Ri #data #data 16 bit addr16 addr11 rel working register R0-R7 128 internal RAM locations and any special function register (SFR) DESCRIPTION
P80CL31; P80CL51
indirect internal RAM location addressed by register R0 or R1 of the actual register bank 8-bit constant included in instruction 16-bit constant included as bytes 2 and 3 of instruction direct addressed bit in internal RAM or SFR. 16-bit destination address. Used by LCALL and LJMP; the branch will be anywhere within the 64 kbytes Program Memory address space 111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes page of Program Memory as the first byte of the following instruction signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps; range is -128 to +127 bytes relative to first byte of the following instruction
Hexadecimal opcode cross-reference * * 8, 9, A, B, C, D, E, F 1, 3, 5, 7, 9, B, D, F 0, 2, 4, 6, 8, A, C, E
1997 Apr 15
48
Table 31 Instruction map Second hexadecimal character of opcode 3
RR A 0 0 0 0 0 0 0 0 0 0 0 0 0 DJNZ direct,rel MOV A,direct (1) CPL A MOV direct,A 0 0 0 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 1 0 7 RRC A RL A RLC A ORL direct,#data ANL direct,#data XRL direct,#data JMP @A+DPTR MOVC A,@A+PC MOVC A,@A+DPTR INC DPTR CPL C CLR C DA A CLR A SWAP A CJNE A,#data,rel CJNE A,direct,rel XCH A,direct MUL AB SUBB A,#data SUBB A,direct DIV AB MOV direct,direct MOV A,#data MOV direct,#data XRL A,#data XRL A,direct ANL A,#data ANL A,direct ORL A,#data ORL A,direct ADDC A,#data ADDC A,direct ADD A,#data ADD A,direct DEC A DEC direct INC A INC direct INC @Ri
First hexadecimal character of opcode 2 4 5 6 7 8 F
1997 Apr 15
0
1
0
NOP
AJMP addr11
LJMP addr16
Philips Semiconductors
1
JBC bit,rel
ACALL addr11
LCALL addr16
2
JB bit,rel
AJMP addr11
RET
3
JNB bit,rel
ACALL addr11
RETI
4
JC rel
AJMP addr11
ORL direct,A
5
JNC rel
ACALL addr11
ANL direct,A
6
JZ rel
AJMP addr11
XRL direct,A
Low voltage 8-bit microcontrollers with UART
7
JNZ rel
ACALL addr11
ORL C,bit
49
8
SJMP rel
AJMP addr11
ANL C,bit
9
MOV DTPR,#data16
ACALL addr11
MOV bit,C
A
ORL C,/bit
AJMP addr11
MOV bit,C
B
ANL C,/bit
ACALL addr11
CPL bit
C
PUSH direct
AJMP addr11
CLR bit
D
POP direct
ACALL addr11
E
MOVX A,@DTPR
AJMP addr11
F
MOVX @DTPR,A
ACALL addr11
SETB SETB bit C MOVX A,@Ri 0 1 MOVX @Ri,A 0 1
DEC @Ri 0 1 ADD A,@Ri 0 1 ADDC A,@Ri 0 1 ORL A,@Ri 0 1 ANL A,@Ri 0 1 XRL A,@Ri 0 1 MOV @Ri,#data 0 1 MOV direct,@Ri 0 1 SUBB A,@Ri 0 1 MOV @Ri,direct 0 1 CJNE @Ri,#data,rel 0 1 XCH A,@Ri 0 1 XCHD A,@Ri 0 1 MOV A,@Ri 0 1 MOV @Ri,A 0 1
9ABCDE INC Rr 123456 DEC Rr 123456 ADD A,Rr 123456 ADDC A,Rr 123456 ORL A,Rr 123456 ANL A,Rr 123456 XRL A,Rr 123456 MOV Rr,#data 123456 MOV direct,Rr 123456 SUB A,Rr 123456 MOV Rr,direct 123456 CJNE Rr,#data,rel 123456 XCH A,Rr 123456 DJNZ Rr,rel 123456 MOV A,Rr 123456 MOV Rr,A 123456
P80CL31; P80CL51
Note
Product specification
1. MOV A, ACC is not a valid instruction.
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
20 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II IO Ptot Tstg Tamb Tj supply voltage input voltage on any pin with respect to ground (VSS) DC current on any input DC current on any output total power dissipation storage temperature operating ambient temperature operating junction temperature PARAMETER
P80CL31; P80CL51
MIN. -0.5 -0.5 -5.0 -5.0 - -65 -40 -
MAX. +6.5 VDD + 0.5 +5.0 +5.0 300 +150 +85 +125 V V
UNIT
mA mA mW C C C
21 DC CHARACTERISTICS FOR P80CL31 AND P80CL51 VSS = 0 V; Tamb = -40 to +85 C; all voltages with respect to VSS unless otherwise specified. SYMBOL VDD PARAMETER supply voltage operating RAM retention in Power-down mode Supply current (note 1, note 2) IDD operating supply current Oscillator 1; fclk = 32 kHz; VDD = 1.8 V; Tamb = 25 C Oscillator 2; fclk = 3.58 MHz; VDD = 3 V Oscillator 3; fclk = 16 MHz; VDD = 5 V Oscillator 4; fclk = 16 MHz; VDD = 5 V Supply current (Idle mode) (note 2, note 3) IDD(idle) supply current (Idle mode) Oscillator 1; fclk = 32 kHz; VDD = 1.8 V; Tamb = 25 C Oscillator 2; fclk = 3.58 MHz; VDD = 3 V Oscillator 3; fclk = 16 MHz; VDD = 5 V Oscillator 4; fclk = 16 MHz; VDD = 5 V Supply current (Power-down mode) (note 2, note 4) IDD(pd) supply current (Power-down mode) VDD = 1.8 V; Tamb = 25 C - 10 A - - - - 25 1.0 10 12 A mA mA mA - - - - 50 2.5 24 26 A mA mA mA VSS = 0 V 1.8 1.0 6.0 - V V CONDITIONS MIN. MAX. UNIT
1997 Apr 15
50
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
SYMBOL Inputs VIL VIH IIL IITL ILI IOL IOH RRST Notes LOW level input voltage HIGH level input voltage input current logic 0 (port 1,2,3) input current logic 0, HIGHto-LOW transition (port 1,2,3) input leakage current (port 0, EA) VDD = 5 V; VI = 0.4 V VDD = 2.5 V; VI = 0.4 V VDD = 5 V; VI = 0.5VDD VDD = 2.5 V; VI = 0.5VDD VSS < VI < VDD VDD = 5 V; VOL = 0.4 V VDD = 2.5 V; VOL = 0.4 V HIGH level output current (push-pull options) RST pull-down resistor VDD = 5 V; VOH = VDD - 0.4 V VDD = 2.5 V; VOH = VDD - 0.4 V PARAMETER CONDITIONS
P80CL31; P80CL51
MIN.
MAX.
UNIT
VSS - - - - -
0.3VDD V V A A mA A A -100 -50 -1.0 -500 10 - - - - 200
0.7VDD VDD
Port outputs LOW level output current 1.6 0.7 -1.6 -0.7 10 mA mA mA mA k
1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns; VIL = VSS; VIH = VDD; XTAL 2 not connected; EA = RST = Port 0 = VDD; all open drain outputs connected to VSS. 2. Circuits with Power-on-reset option `OFF' are tested at VDD(min) = 1.8 V; within option `ON' (typically 1.3 V) they are tested at VDD(min) = 2.3 V. Please note, option `ON' is only available on P80CL51. 3. The Idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns; VIL = VSS. XTAL 2 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS. 4. The Power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS.
1997 Apr 15
51
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
22 DC CHARACTERISTICS FOR P80C51 VSS = 0 V; VDD = 5.0V 10%; fclk = 3.5 to 16 MHz; Tamb = -40 to +85 C all voltages with respect to VSS unless otherwise specified. Note that the Power-on-reset option is `OFF' and the Oscillator option is `Oscillator 3'. SYMBOL VDD operating RAM retention in Power-down mode IDD IDD(idle) IDD(pd) Inputs VIL VIH IIL ITL ILI IOL IOH RRST Notes 1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns; VIL = VSS; VIH = VDD; XTAL 2 not connected; EA = RST = Port 0 = VDD; all open drain outputs connected to VSS. 2. The Idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns; VIL = VSS. XTAL 2 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS. 3. The Power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS. LOW level input voltage HIGH level input voltage input current logic 0 (port 1,2,3) input current logic 0, HIGH- to-LOW transition (port 1,2,3) input leakage current (port 0, EA) VI = 0.4 V VI = 0.5VDD VSS < VI < VDD VOL = 0.4 V VOH = VDD - 0.4 V VSS 0.7VDD - - - 0.3VDD VDD 100 1.0 10 - - 200 V V A mA A operating supply current supply current (Idle mode) supply current (Power-down mode) PARAMETER supply voltage VSS = 0 V 4.5 1.0 fclk = 16 MHz; VDD = 5.0 V; note 1 - fclk = 16 MHz; VDD = 5.0 V; note 2 - VDD = 5.0 V; note 3 - 5.5 - 24 10 50 V V mA mA mA CONDITIONS MIN. MAX. UNIT
Port outputs LOW level output current HIGH level output current (push-pull options) RST pull-down resistor 1.6 -1.6 10 mA mA k
1997 Apr 15
52
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, halfpage
20
MBK035
fXTAL (MHz)
handbook, halfpage
20
MBK036
IDD (mA)
16
16 MHz
16
12
12
8
12 MHz 8 8 MHz
4
4 3.58 MHz
0 0 2 4 VDD (V) 6
0 0 2 4 VDD (V) 6
Tamb = 25 C.
Fig.28 Frequency operating range.
Fig.29 Typical operating current as a function of frequency and VDD.
handbook, halfpage
6
MBK046
handbook, halfpage
6
MLA592
IDD (idle) 4
16 MHz
IDD(pd) (A)
12 MHz
4
8 MHz 2 2
3.58 MHz 0 0 2 4 VDD (V) 6 0
0
2
4
VDD (V)
6
Tamb = 25 C.
Tamb = 25 C.
Fig.30 Typical Idle current as a function of frequency and VDD.
Fig.31 Typical Power-down current as a function of VDD.
1997 Apr 15
53
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
23 AC CHARACTERISTICS VDD = 5 V; VSS = 0 V; Tamb = -40 to +85 C; CL = 50 pF for Port 0, ALE and PSEN; CL = 40 pF for all other outputs unless specified; tCLK = 1/ fCLK. SYMBOL PARAMETER fosc = 12 MHz MIN. Program Memory (Fig.32) tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tPLAZ tRLRH tWLWH tLLAX tRLDV tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ ALE pulse width address valid to ALE LOW address hold after ALE LOW ALE LOW to valid instruction in ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid instruction in input instruction hold after PSEN input instruction float after PSEN PSEN to address valid address to valid instruction in PSEN LOW to address float 127 43 48 - 58 215 - 0 - 75 - 12 - - - 233 - - 125 - 63 - 302 - - - - 150 97 517 585 300 - 123 - - - 12 - 3tCLK - 50 4 tCLK - 40 tCLK - 60 7tCLK - 150 tCLK - 50 - 2tCLK - 40 tCLK - 40 tCLK - 35 - tCLK - 25 3tCLK - 35 - 0 - tCLK - 8 - 0 6tCLK - 100 6tCLK - 100 tCLK - 35 - - - - - 4tCLK - 100 - - 3tCLK - 125 - tCLK - 20 - 5tCLK - 115 - - - - 5tCLK - 165 2tCLK - 70 8tCLK - 150 9tCLK - 165 3tCLK + 50 - tCLK + 40 - - - 12 ns ns ns ns ns ns ns ns ns ns ns ns MAX. fosc = VARIABLE MIN. MAX. UNIT
External Data Memory (Figs 33 and 34) RD pulse width WR pulse width address hold after ALE LOW RD LOW to valid data in data float after RD ALE LOW to valid data in address to valid data in ALE LOW to RD or WR LOW address valid to RD or WR LOW RD or WR HIGH to ALE HIGH data valid to WR transition data valid time WR HIGH data hold after WR RD LOW to address float 400 400 48 - - - - 200 203 43 23 433 33 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1997 Apr 15
54
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
t CY t LHLL t LLIV
ALE t LLPL t PLPH PSEN t LLAX t AVLL PORT 0 A0 to A7 t PLAZ t AVIV PORT 2 address A8 to A15 address A8 to A15
MGD680
t PXAV t PLIV inst. input t PXIX t PXIZ A0 to A7 inst. input
Fig.32 Read from Program Memory.
handbook, full pagewidth
t CY t LHLL t LLDV t WHLH
ALE
PSEN t LLWL RD t AVLL t LLAX t AVWL PORT 0 A0 to A7 t RLAZ tAVDV PORT 2 address A8 to A15 (DPH) or Port 2
MGA177
t RLRH
t RHDZ t RLDV t RHDX data input
Fig.33 Read from Data Memory.
1997 Apr 15
55
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
t CY t LHLL t WHLH
ALE
PSEN t LLWL t WLWH
WR t AVWL t AVLL t LLAX t QVWX PORT 0 A0 to A7 data output t QVWH t WHQX
PORT 2
address A8 to A15 (DPH) or Port 2
MGA178
Fig.34 Write to Data Memory.
1997 Apr 15
56
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, full pagewidth
one machine cycle S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2
one machine cycle S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2
dotted lines are valid when RD or WR are active
XTAL1 INPUT
ALE
only active during a read from external data memory only active during a write to external data memory
PSEN
RD
WR
external program memory fetch
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
read or write of external data memory
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
data output or data input
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15 or Port 2 output
address A8 - A15
PORT 0, 2, 3 OUTPUT
old data
new data
PORT 1 OUTPUT
old data
new data
PORT 0, 2, 3 INPUT
sampling time of I/O port pins during input
SERIAL PORT SHIFT CLOCK (MODE 0)
MGD681
Fig.35 Instruction cycle timing.
1997 Apr 15
57
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
handbook, halfpage
0.7 VDD
0.7 VDD
0.9 VDD test points 0.4 VDD 0.3 VDD 0.3 VDD
MLA586
Fig.36 AC testing input waveform.
handbook, 4 columns
-500 A
IIL(T)
MGD682
IL
-100 A
IIL 0.5 VDD VDD
Fig.37 Input current.
1997 Apr 15
58
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
24 P85CL000HFZ `PIGGY-BACK' SPECIFICATION The differences between the masked version and the piggy-back are described below. 24.1 General description 24.2
P80CL31; P80CL51
Feature differences/additional features with respect to P80CL51
* No internal ROM * 8-bit CPU, RAM, I/O in a single 40-lead package with DIP pin-out * Socket for up to 16 kbytes external EPROM * 256 bytes RAM, expandable externally to 64 kbytes * I2C-bus interface for serial transfer on two lines * On-chip oscillator: Oscillator 4 option only.
The P85CL000HFZ is a piggy-back version with 256 bytes of RAM used for emulation of the P80CL51 and the P83CL410 microcontrollers. The P85CL000HFZ is manufactured in an advanced CMOS technology. The instruction set of the P85CL000HFZ is based on that of the 8051. The device has low power consumption and a wide supply voltage range. The P85CL000HFZ has two software selectable modes of reduced activity for further power reduction: Idle and Power-down. For timing and AC/DC characteristics, please refer to the P80CL51 specifications. 24.3
Common specification/feature differences between P85CL000HFZ and P83CL410/P80CL51 PARAMETER P83CL410/P80CL51 128 4K 1, 2, 3 Oscillator 1, 2, 3, 4, RC standard dual in-line, small outline IDD full specification P85CL000HFZ `PIGGY-BACK' 256 EPROM size dependent (max. 16K) 1 Oscillator 4 same pin-out as SOT129-1, but larger package size IDD (Oscillator 4) + IEPROM full, limited by EPROM not tested (different package)
RAM size ROM size Port options Oscillator options Mechanical dimensions Current consumption Voltage range ESD
1997 Apr 15
59
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
25 PACKAGE OUTLINES DIP40: plastic dual in-line package; 40 leads (600 mil)
P80CL31; P80CL51
SOT129-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 40 21 MH wM (e 1)
pin 1 index E
1
20
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.70 1.14 0.067 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 15.24 0.60
L 3.60 3.05 0.14 0.12
ME 15.80 15.24 0.62 0.60
MH 17.42 15.90 0.69 0.63
w 0.254 0.01
Z (1) max. 2.25 0.089
52.50 51.50 2.067 2.028
14.1 13.7 0.56 0.54
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT129-1 REFERENCES IEC 051G08 JEDEC MO-015AJ EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1997 Apr 15
60
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
VSO40: plastic very small outline package; 40 leads
SOT158-1
D
E
A X
c y HE vMA
Z 40 21
Q A2 A1 pin 1 index Lp L 1 e bp 20 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.70 0.11 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 bp 0.42 0.30 c 0.22 0.14 D (1) 15.6 15.2 E (2) 7.6 7.5 0.30 0.29 e 0.762 0.03 HE 12.3 11.8 0.48 0.46 L 2.25 Lp 1.7 1.5 Q 1.15 1.05 v 0.2 w 0.1 y 0.1 Z (1) 0.6 0.3
0.012 0.096 0.017 0.0087 0.61 0.010 0.004 0.089 0.012 0.0055 0.60
0.067 0.089 0.059
0.045 0.024 0.008 0.004 0.004 0.041 0.012
7 0o
o
Notes 1. Plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT158-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-24
1997 Apr 15
61
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
P80CL31; P80CL51
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1997 Apr 15
62
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
26 SOLDERING 26.1 Introduction
P80CL31; P80CL51
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 26.3.2 WAVE SOLDERING
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 26.2 26.2.1 DIP SOLDERING BY DIPPING OR BY WAVE
26.3.2.1
QFP
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 26.2.2 REPAIRING SOLDERED JOINTS
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1).
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 26.3 26.3.1 QFP and VSO REFLOW SOLDERING
26.3.2.2
VSO
Wave soldering techniques can be used for all VSO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end.
Reflow soldering techniques are suitable for all QFP and VSO packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Manual" (order code 9397 750 00192). 1997 Apr 15 63
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
26.3.2.3 Method (QFP and VSO)
P80CL31; P80CL51
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 26.3.3 REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. 27 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 28 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Apr 15
64
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
NOTES
P80CL31; P80CL51
1997 Apr 15
65
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
NOTES
P80CL31; P80CL51
1997 Apr 15
66
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART
NOTES
P80CL31; P80CL51
1997 Apr 15
67
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/1200/03/pp68
Date of release: 1997 Apr 15
Document order number:
9397 750 01512

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